TPS70845, TPS70848, TPS70851, TPS70858, TPS70802 DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS WITH INTEGRATED SVS FOR SPLIT VOLTAGE SYSTEMS SLVS301B – JUNE 2000 – REVISED OCTOBER 2002 D Dual Output Voltages for Split-Supply D D D D Applications Independent Enable Functions (See Part Number TPS707xx for Sequenced Outputs) Output Current Range of 250 mA on Regulator 1 and 125 mA on Regulator 2 Voltage Options Are 3.3-V/2.5-V, 3.3-V/1.8-V, 3.3-V/1.5-V, 3.3-V/1.2-V, and Dual Adjustable Outputs Open Drain Power-On Reset With 120-ms Delay Open Drain Power Good for Regulator 1 and Regulator 2 D D D D D D D D D D D Fast Transient Response Ultralow 190 µA (typ) Quiescent Current 1 µA Input Current During Standby Low Noise: 65 µVRMS Without Bypass Capacitor Quick Output Capacitor Discharge Feature One Manual Reset Input 2% Accuracy Over Load and Temperature Undervoltage Lockout (UVLO) Feature 20-Pin PowerPAD TSSOP Package Thermal Shutdown Protection PWP PACKAGE (TOP VIEW) description NC VIN1 VIN1 MR EN1 EN2 RESET GND VIN2 VIN2 The TPS708xx is a low-dropout voltage regulator with integrated SVS (RESET, POR, or power on reset) and power good (PG) functions. These devices are capable of supplying 250 mA and 125 mA by regulator 1 and regulator 2 respectively. Quiescent current is typically 190 µA at full load. Differentiated features, such as accuracy, fast transient response, SVS supervisory circuit (power on reset), manual reset input, and independent enable functions provide a complete system solution. 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 NC – No internal connection TPS70851 PWP 5V 0.1 µF 10 µF VSENSE1 250 kΩ PG1 PG1 MR VIN2 MR >2 V EN1 <0.7 V EN2 >2 V 250 kΩ >2 V <0.7 V 0.1 µF 250 kΩ RESET RESET EN1 PG2 EN2 VSENSE2 I/O 3.3 V VOUT1 VIN1 NC VOUT1 VOUT1 VSENSE1/FB1 PG1 PG2 VSENSE2/FB2 VOUT2 VOUT2 NC PG2 <0.7 V VOUT2 1.8 V Core 10 µF Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments. Copyright 2002, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 TPS70845, TPS70848, TPS70851, TPS70858, TPS70802 DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS WITH INTEGRATED SVS FOR SPLIT VOLTAGE SYSTEMS SLVS301B – JUNE 2000 – REVISED OCTOBER 2002 description (continued) The TPS708xx family of voltage regulators offers very low dropout voltage and dual outputs. These devices have extremely low noise output performance without using any added filter bypass capacitors and are designed to have a fast transient response and be stable with 10 µF low ESR capacitors. These devices have fixed 3.3-V/2.5-V, 3.3-V/1.8-V, 3.3-V/1.5-V, 3.3-V/1.2-V, and adjustable voltage options. Regulator 1 can support up to 250 mA, and regulator 2 can support up to 125 mA. Separate voltage inputs allow the designer to configure the source power. Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (typically 170 mV on regulator 1) and is directly proportional to the output current. Additionally, since the PMOS pass element is a voltage-driven device, the quiescent current is very low and independent of output loading (maximum of 230 µA over the full range of output current and full range of temperature). This LDO family also features a sleep mode; applying a high signal to EN1 or EN2 (enable) shuts down regulator 1 or regulator 2, respectively. When a high signal is applied to both EN1 and EN2, both regulators are in sleep mode, thereby reducing the input current to 2 µA at TJ = 25°C. For each regulator, there is an internal discharge transistor to discharge the output capacitor when the regulator is turned off (disabled). The PG1 pin reports the voltage condition at VOUT1. The PG1 pin can be used to implement a SVS (RESET, POR, or power on reset) for the circuitry supplied by regulator 1. The PG2 pin reports the voltage conditions at VOUT2. The PG2 pin can be used to implement a SVS (power on reset) for the circuitry supplied by regulator 2. The TPS708xx features a RESET (SVS, POR, or power on reset). RESET output initiates a reset in the event of an undervoltage condition. RESET also indicates the status of the manual reset pin (MR). When MR is in the logic high state, RESET goes to a high-impedance state after 120 ms delay. To monitor VOUT1, the PG1 output pin can be connected to MR. To monitor VOUT2, the PG2 output pin can be connected to MR. The device has an undervoltage lockout UVLO circuit which prevents the internal regulators from turning on until VIN1 reaches 2.5V. AVAILABLE OPTIONS TJ – 40°C to 125°C REGULATOR 1 VO (V) REGULATOR 2 VO (V) TSSOP (PWP) 3.3 V 1.2 V TPS70845PWP 3.3 V 1.5 V TPS70848PWP 3.3 V 1.8 V TPS70851PWP 3.3 V 2.5 V TPS70858PWP Adjustable (1.22 V to 5.5 V) Adjustable (1.22 V to 5.5 V) TPS70802PWP NOTE: The TPS70802 is programmable using external resistor dividers (see application information) The PWP package is available taped and reeled. Add an R suffix to the device type (e.g., TPS70802PWPR). 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TPS70845, TPS70848, TPS70851, TPS70858, TPS70802 DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS WITH INTEGRATED SVS FOR SPLIT VOLTAGE SYSTEMS SLVS301B – JUNE 2000 – REVISED OCTOBER 2002 detailed block diagram – fixed voltage version VIN1 (2 Pins) VOUT1 (2 Pins) UVLO Current Sense Shutdown 10 kΩ ENA_1 2.5 V – GND Reference Thermal Shutdown VSENSE1 (see Note A) ENA_1 + Vref FB1 Vref Shutdown PG1 VSENSE1 Rising Edge Deglitch VPGD_1 VIN1 MR RESET Falling Edge Delay UVLO EN1 ENA_1 Shutdown PG2 VSENSE2 Shutdown Rising Edge Deglitch VPGD_2 EN2 Vref ENA_2 – FB2 + Current Sense ENA_2 VSENSE2 (see Note A) ENA_2 10 kΩ VOUT2 (2 Pins) VIN2 (2 Pins) NOTE A: For most applications, VSENSE1 and VSENSE2 should be externally connected to VOUT1 and VOUT2 respectively as close as possible to the device. For other implementations, refer to SENSE terminal connection discussion in the application information section. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 TPS70845, TPS70848, TPS70851, TPS70858, TPS70802 DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS WITH INTEGRATED SVS FOR SPLIT VOLTAGE SYSTEMS SLVS301B – JUNE 2000 – REVISED OCTOBER 2002 detailed block diagram – adjustable voltage version VIN1 (2 Pins) VOUT1 (2 Pins) UVLO Current Sense Shutdown ENA_1 FB1 (see Note A) 2.5 V – GND Thermal Shutdown Reference ENA_1 + Vref Vref Shutdown PG1 VSENSE1 Rising Edge Deglitch VPGD_1 VIN1 MR RESET Falling Edge Delay UVLO EN1 ENA_1 Shutdown Shutdown PG2 VSENSE2 Rising Edge Deglitch VPGD_2 EN2 Vref ENA_2 – Current Sense + ENA_2 ENA_2 FB2 (see Note A) VOUT2 (2 Pins) VIN2 (2 Pins) NOTE A: For most applications, FB1 and FB2 should be externally connected to resistor dividers as close as possible to the device. For other implementations, refer to FB terminals connection discussion in the application information section. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TPS70845, TPS70848, TPS70851, TPS70858, TPS70802 DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS WITH INTEGRATED SVS FOR SPLIT VOLTAGE SYSTEMS SLVS301B – JUNE 2000 – REVISED OCTOBER 2002 RESET timing diagram VIN1 VUVLO VUVLO VRES t VRES MR Input t RESET Output Output Undefined Î Î Î 120 ms Delay 120 ms Delay ÎÎ ÎÎ ÎÎ Output Undefined t NOTE A: VRES is the minimum input voltage for a valid RESET. The symbol VRES is not currently listed within EIA or JEDEC standards for semiconductor symbology. PG1 timing diagram VIN1 VUVLO VUVLO VPG1 VPG1 t VOUT1 VIT+ (see Note B) Threshold Voltage VIT – (see Note B) t ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ PG1 Output Output Undefined ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ PG1 Output Undefined t NOTES: A. VPG1 is the minimum input voltage for a valid PG1. The symbol VPG1 is not currently listed within EIA or JEDEC standards for semiconductor symbology. B. VIT – Trip voltage is typically 5% lower than the output voltage (95%VO) VIT– to VIT+ is the hysteresis voltage. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 TPS70845, TPS70848, TPS70851, TPS70858, TPS70802 DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS WITH INTEGRATED SVS FOR SPLIT VOLTAGE SYSTEMS SLVS301B – JUNE 2000 – REVISED OCTOBER 2002 PG2 timing diagram (assuming VIN1 already powered up) VIN2 t VOUT2 VIT+ (see Note A) Threshold Voltage VIT – (see Note A) t PG2 Output t NOTE A: VIT – Trip voltage is typically 5% lower than the output voltage (95%VO) VIT– to VIT+ is the hysteresis voltage. Terminal Functions TERMINAL NAME NO. I/O DESCRIPTION EN1 5 I Active low enable for VOUT1 EN2 6 I Active low enable for VOUT2 GND 8 Ground MR 4 NC 1, 11, 20 PG1 16 O Open drain output, low when VOUT1 voltage is less than 95% of the nominal regulated voltage PG2 15 O Open drain output, low when VOUT2 voltage is less than 95% of the nominal regulated voltage RESET 7 I Open drain output, SVS (power on reset) signal, active low VIN1 VIN2 VOUT1 VOUT2 VSENSE2/FB2 VSENSE1/FB1 6 I Manual reset input, active low, pulled up internally No connection 2, 3 I Input voltage of regulator 1 9, 10 I Input voltage of regulator 2 18, 19 O Output voltage of regulator 1 12, 13 O Output voltage of regulator 2 14 I Regulator 2 output voltage sense/ regulator 2 feedback for adjustable 17 I Regulator 1 output voltage sense/ regulator 1 feedback for adjustable POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TPS70845, TPS70848, TPS70851, TPS70858, TPS70802 DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS WITH INTEGRATED SVS FOR SPLIT VOLTAGE SYSTEMS SLVS301B – JUNE 2000 – REVISED OCTOBER 2002 detailed description The TPS708xx low dropout regulator family provides dual regulated output voltages with independent enable functions. These devices provide fast transient response and high accuracy with small output capacitors, while drawing low quiescent current. Other features are integrated SVS (power-on reset, RESET) and power good (PG1, PG2) that monitor output voltages and provide logic output to the system. These differentiated features provide a complete power solution. The TPS708xx, unlike many other LDOs, features very low quiescent current which remains virtually constant even with varying loads. Conventional LDO regulators use a PNP pass element, the base current of which is directly proportional to the load current through the regulator (IB = IC/β). The TPS708xx uses a PMOS transistor to pass current; because the gate of the PMOS is voltage driven, operating current is low and stable over the full load range. pin functions enable (EN1 and EN2) The EN terminals are inputs which enable or shut down each respective regulator. If EN is at a voltage high signal the respective regulator is in shutdown mode. When EN goes to voltage low, then the respective regulator is enabled. power good (PG1 and PG2) The PG terminals are open drain, active high outputs which indicate the status of each respective regulator. When the VOUT1 reaches 95% of its regulated voltage, PG1 goes to a high impedance state. When the VOUT2 reaches 95% of its regulated voltage, PG2 goes to a high impedance state. Each PG goes to a low impedance state when its respective output voltage is pulled below 95% (i.e., over load condition) of its regulated voltage. The open drain outputs of the PG terminals require a pullup resistor. manual reset pin (MR) MR is an active low input terminal used to trigger a reset condition. When MR is pulled to logic low, a POR (RESET) occurs. The terminal has a 6-µA pullup current to VIN1. sense (VSENSE1, VSENSE2) The sense terminals of fixed-output options must be connected to the regulator outputs, and the connection should be as short as possible. Internally, the sense terminal connects to high-impedance wide-bandwidth amplifiers through a resistor-divider network and noise pickup feeds through to the regulator output. It is essential to route the sense connection in such a way as to minimize/avoid noise pickup. Adding RC networks between sense terminals and VOUTS to filter noise is not recommended because it can cause the regulators to oscillate. FB1 and FB2 FB1 and FB2 are input terminals used for adjustable-output devices and must be connected to the external feedback resistor divider. FB1 and FB2 connections should be as short as possible. It is essential to route them in such a way as to minimize/avoid noise pickup. Adding RC networks between FB terminals and VOUTS to filter noise is not recommended because it can cause the regulators to oscillate. RESET indicator The TPS708xx features a RESET (SVS, POR, or power on reset). RESET can be used to drive power on reset circuitry or a low-battery indicator. RESET is an active low, open drain output which indicates the status of the manual reset pin (MR). When MR is in high impedance state, RESET goes to a high impedance state after a 120 ms delay. To monitor VOUT1, the PG1 output pin can be connected to MR. To monitor VOUT2, the PG2 output pin can be connected to MR. The open drain output of the RESET terminal requires a pullup resistor. If RESET is not used, it can be left floating. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 TPS70845, TPS70848, TPS70851, TPS70858, TPS70802 DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS WITH INTEGRATED SVS FOR SPLIT VOLTAGE SYSTEMS SLVS301B – JUNE 2000 – REVISED OCTOBER 2002 detailed description (continued) VIN1 and VIN2 VIN1 and VIN2 are inputs to each regulator. Internal bias voltages are powered by VIN1. VOUT1 and VOUT2 VOUT1 and VOUT2 are output terminals of each regulator. absolute maximum ratings over operating junction temperature (unless otherwise noted)† Input voltage range‡: VIN1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V VIN2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V Voltage range at EN1, EN2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V Output voltage range (VOUT1, VSENSE1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Output voltage range (VOUT2, VSENSE2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Maximum RESET, PG1, PG2 voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Maximum MR voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VIN1 Peak output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internally limited Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Tables Operating virtual junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 150°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C ESD rating, HBM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 kV † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. ‡ All voltages are tied to network ground. ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ DISSIPATION RATING TABLE PACKAGE AIR FLOW (CFM) TA ≤ 25°C DERATING FACTOR TA = 70°C TA = 85°C 0 3.067 W 30.67 mW/°C 1.687 W 1.227 W PWP§ 250 4.115 W 2.265 W 1.646 W 41.15 mW/°C § This parameter is measured with the recommended copper heat sink pattern on a 4-layer PCB, 1 oz. copper on 4-in × 4-in ground layer. For more information, refer to TI technical brief SLMA002. recommended operating conditions MIN Input voltage, VI† Output current, IO (regulator 1) Output current, IO (regulator 2) Output voltage range (for adjustable option) MAX UNIT 2.7 6 0 250 mA V 0 125 mA 1.22 5.5 V Operating virtual junction temperature, TJ –40 125 °C † To calculate the minimum input voltage for maximum output current, use the following equation: VI(min) = VO(max) + VDO(max load). 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TPS70845, TPS70848, TPS70851, TPS70858, TPS70802 DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS WITH INTEGRATED SVS FOR SPLIT VOLTAGE SYSTEMS SLVS301B – JUNE 2000 – REVISED OCTOBER 2002 electrical characteristics over recommended operating junction temperature (TJ = –40°C to 125°C) VIN1 or VIN2 = VO(nom) + 1 V, IO = 1 mA, EN = 0, CO = 33 µF(unless otherwise noted) PARAMETER TEST CONDITIONS Reference voltage 1 2 V output 1.2 VO Output voltage (see Notes 1 and 3) FB connected to VO 2.7 V < VI < 6 V, TJ = 25°C 1 5 V output 1.5 TJ = 25°C 2.45 2.55 3.3 4.3 V < VI < 6 V 3.234 TJ = 25°C 3.366 190 See Note 3 230 Load regulation for VOUT1 and VOUT2 TJ = 25°C Regulator 1 TJ = 25°C, See Note 1 See Note 1 0.1% 1 BW = 300 Hz to 50 kHz, kHz CO = 33 µF, µF Regulator 2 TJ = 25°C 1.6 1.9 0.750 1 EN2 = VI, EN1 = VI, EN2 = VI 6 f = 1 kHz, CO = 33 µF, IOUT1 = 250 mA f = 1 kHz, CO = 33 µF, IOUT2 = 125 mA Regulator 1 Power supply ripple rejection Regulator 2 2 TJ = 25°C TJ = 25°C, 60 TJ = 25°C, 50 A °C 150 EN1 = VI, V µVrms 65 Thermal shutdown junction temperature Regulator 1 and Regulator 2 µA mV 65 VO = 0 V Regulator 2 V 0.01% Regulator 1 PSRR 1.836 2.5 TJ = 25°C See Note 3, V 1.53 1.8 TJ = 25°C 4.3 V < VI < 6 V, VO + 1 V < VI ≤ 6 V, VO + 1 V < VI ≤ 6 V, II(standby) ( ) Standby current 1.224 1.764 3.5 V < VI < 6 V Out ut voltage line regulation (∆VO/VO) for Output regulator 1 and regulator 2 (see Note 2) Output current limit 1.244 1.5 2.8 V < VI < 6 V Quiescent current (GND current) for regulator 1 and regulator 2, EN1 = EN2 = 0 V, (see Note 1) 1.196 1.47 3.5 V < VI < 6 V, UNIT 1.22 TJ = 25°C 2.8 V < VI < 6 V, MAX 1.2 2.7 V < VI < 6 V 3 3 V output 3.3 TYP 1.176 2.7 V < VI < 6 V, 2 5 V output 2.5 Output noise voltage FB connected to VO 2.7 V < VI < 6 V 1 8 V output 1.8 Vn MIN 2.7 V < VIN < 6 V, TJ = 25°C 2.7 V < VIN < 6 V, µA dB RESET terminal Minimum input voltage for valid RESET I(RESET) = 300 µA, t(RESET) RESET pulse duration Output low voltage VI = 3.5 V, V(RESET) = 6 V Leakage current V(RESET) ≤ 0.8 V 80 I(RESET) = 1 mA 1.0 1.3 V 120 160 ms 0.15 0.4 V 1 µA NOTES: 1. Minimum input operating voltage is 2.7 V or VO(typ) + 1 V, whichever is greater. Maximum input voltage = 6 V, minimum output current 1 mA. 2. If VO < 1.8 V then VImax = 6 V, VImin = 2.7 V: Line regulation (mV) + ǒ%ńVǓ V O ǒVImax * 2.7 VǓ 100 1000 If VO > 2.5 V then VImax = 6 V, VImin = Vo + 1 V: Line regulation (mV) + ǒ%ńVǓ V O ǒVImax * ǒVO ) 1ǓǓ 1000 100 3. IO = 1 mA to 250 mA for regulator 1 and 1 mA to 125 mA for regulator 2. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 TPS70845, TPS70848, TPS70851, TPS70858, TPS70802 DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS WITH INTEGRATED SVS FOR SPLIT VOLTAGE SYSTEMS SLVS301B – JUNE 2000 – REVISED OCTOBER 2002 electrical characteristics over recommended operating junction temperature (TJ = –40°C to 125°C) VIN1 or VIN2 = VO(nom) + 1 V, IO = 1 mA, EN = 0, CO = 33 µF(unless otherwise noted) (continued) PARAMETER TEST CONDITIONS UVLO threshold MIN TYP 2.4 MAX UNIT 2.65 V FB terminal Input current – TPS70202 FB = 1.8 V µA 1 PG1/PG2 terminal Minimum input voltage for valid PGx I(PGx) = 300 µA, Trip threshold voltage VO decreasing Hysteresis voltage Measured at VO tr(PGx) Rising edge deglitch Output low voltage VI = 2.7 V, Leakage current V(PGx) = 6 V V(PGx) ≤ 0.8 V 92% I(PGx) = 1 mA 1.0 1.3 95% 98% V VO 0.5% VO 30 µs 0.15 0.4 V 1 µA EN1/EN2 terminal High-level ENx input voltage 2 V Low-level ENx input voltage Input current (ENx) –1 0.7 V 1 µA MR terminal High-level input voltage 2 V Low-level input voltage 0.7 Pullup current source V µA 6 VOUT1 terminal Dropout voltage (see Note 4) IO = 250 mA, VIN1 = 3.2 V, TJ = 25°C 83 IO = 250 mA, VIN1 = 3.2 V 140 mV Peak output current 2 ms pulse width 750 mA Discharge transistor current VOUT1 = 1.5 V 7.5 mA Peak output current 2 ms pulse width 375 mA Discharge transistor current VOUT2 = 1.5 V 7.5 mA VOUT2 terminal NOTE 4: Input voltage(VIN1 or VIN2) = VO(Typ) – 100 mV. For the 1.5-V, 1.8-V and 2.5-V regulators, the dropout voltage is limited by input voltage range. The 3.3 V regulator input voltage is set to 3.2 V to perform this test. 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TPS70845, TPS70848, TPS70851, TPS70858, TPS70802 DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS WITH INTEGRATED SVS FOR SPLIT VOLTAGE SYSTEMS SLVS301B – JUNE 2000 – REVISED OCTOBER 2002 TYPICAL CHARACTERISTICS Table of Graphs FIGURE VO Output voltage PSRR Zo 1–3 vs Junction temperature 4–5 Ground current vs Junction temperature Power supply rejection ratio vs Frequency 7 – 10 Output spectral noise density vs Frequency 11 – 14 Output impedance vs Frequency 15 – 18 vs Junction temperature 19, 20 vs Input voltage 21, 22 Dropout voltage VO vs Output current Load transient response 23, 24 Line transient response 25, 26 Output voltage vs Time (start-up) 27, 28 Equivalent series resistance (ESR) vs Output current 30 – 33 TPS70851 TPS70851 OUTPUT VOLTAGE vs OUTPUT CURRENT OUTPUT VOLTAGE vs OUTPUT CURRENT 1.802 3.303 VIN1 = 4.3 V TJ = 25°C VOUT1 3.302 VIN2 = 2.8V TJ = 25°C VOUT2 1.801 3.301 VO – Output Voltage – V VO – Output Voltage – V 6 3.3 3.299 3.298 1.800 1.799 1.798 1.797 3.297 1.796 3.296 1.795 3.295 0 0.05 0.2 0.1 0.15 IO – Output Current – A 0.25 0 0.025 0.05 0.075 0.1 0.125 IO – Output Current – A Figure 1 Figure 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 TPS70845, TPS70848, TPS70851, TPS70858, TPS70802 DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS WITH INTEGRATED SVS FOR SPLIT VOLTAGE SYSTEMS SLVS301B – JUNE 2000 – REVISED OCTOBER 2002 TYPICAL CHARACTERISTICS TPS70851 OUTPUT VOLTAGE vs JUNCTION TEMPERATURE TPS70845 OUTPUT VOLTAGE vs OUTPUT CURRENT 1.201 3.35 VIN2 = 2.7 V TJ = 25°C VOUT2 3.33 VO – Output Voltage – V VO – Output Voltage – V 1.200 VIN1 = 4.3 V VOUT1 1.199 1.198 1.197 1.196 IO = 250 mA 3.31 3.29 IO = 1 mA 3.27 3.25 1.195 0 0.025 0.05 0.075 IO – Output Current – A 0.1 3.23 –40 –25 –10 5 20 35 50 65 80 95 110 125 TJ – Junction Temperature – °C 0.125 Figure 4 Figure 3 TPS70851 OUTPUT VOLTAGE vs JUNCTION TEMPERATURE GROUND CURRENT vs JUNCTION TEMPERATURE 210 1.85 VIN2 = 2.8 V VOUT2 Regulator 1 and Regulator 2 200 1.81 IO = 1 mA 1.79 IO = 250 mA 1.77 Ground Current – µ A VO – Output Voltage – V 1.83 190 180 IOUT1 = 250 mA IOUT2 = 125 mA 170 1.75 160 1.73 –40 –25 –10 5 20 35 50 65 80 95 110 125 TJ – Junction Temperature – °C 150 –40 –25 –10 5 20 35 50 65 Figure 6 POST OFFICE BOX 655303 80 95 110 125 TJ – Junction Temperature – °C Figure 5 12 IOUT1 = 1 mA IOUT2 = 1 mA • DALLAS, TEXAS 75265 TPS70845, TPS70848, TPS70851, TPS70858, TPS70802 DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS WITH INTEGRATED SVS FOR SPLIT VOLTAGE SYSTEMS SLVS301B – JUNE 2000 – REVISED OCTOBER 2002 TYPICAL CHARACTERISTICS TPS70851 TPS70851 POWER SUPPLY REJECTION RATIO vs FREQUENCY POWER SUPPLY REJECTION RATIO vs FREQUENCY 10 PSRR – Power Supply Rejection Ratio – dB PSRR – Power Supply Rejection Ratio – dB –10 IO = 10 mA CO = 22 µF VOUT1 –20 –30 –40 –50 –60 –70 –80 –90 IO = 250 mA CO = 22 µF VOUT1 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 10 100 1k 100 k 10 k 10 1M 100 f – Frequency – Hz Figure 7 100 k 1M Figure 8 TPS70851 TPS70851 POWER SUPPLY REJECTION RATIO vs FREQUENCY POWER SUPPLY REJECTION RATIO vs FREQUENCY 10 –10 IO = 10 mA CO = 22 µF VOUT2 –20 PSRR – Power Supply Rejection Ratio – dB PSRR – Power Supply Rejection Ratio – dB 1k 10 k f – Frequency – Hz –30 –40 –50 –60 –70 –80 IO = 150 mA CO = 22 µF VOUT2 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –90 10 100 1k 10 k f – Frequency – Hz 100 k 1M 10 100 Figure 9 1k 10 k f – Frequency – Hz 100 k 1M Figure 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 TPS70845, TPS70848, TPS70851, TPS70858, TPS70802 DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS WITH INTEGRATED SVS FOR SPLIT VOLTAGE SYSTEMS SLVS301B – JUNE 2000 – REVISED OCTOBER 2002 TYPICAL CHARACTERISTICS OUTPUT SPECTRAL NOISE DENSITY vs FREQUENCY OUTPUT SPECTRAL NOISE DENSITY vs FREQUENCY 10 10 1 0.1 0.01 100 1k 10 k f – Frequency – Hz VIN1 = 4.3 V VOUT1 = 3.3 V IO = 250 mA Hz Output Spectral Noise Density – µV Output Spectral Noise Density – µV Hz VIN1 = 4.3 V VOUT1 = 3.3 V IO = 10 mA 1 0.1 0.01 100 100 k 1k 10 k f – Frequency – Hz Figure 11 Figure 12 OUTPUT SPECTRAL NOISE DENSITY vs FREQUENCY OUTPUT SPECTRAL NOISE DENSITY vs FREQUENCY 10 VIN2 = 2.8 V VOUT2 = 1.8 V IO = 125 mA Hz Output Spectral Noise Density – µV Hz Output Spectral Noise Density – µV 10 VIN2 = 2.8 V VOUT2 = 1.8 V IO = 10 mA 1 0.1 0.01 100 1k 10 k f – Frequency – Hz 100 k 1 0.1 0.01 100 Figure 13 14 100 k 1k 10 k f – Frequency – Hz Figure 14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 100 k TPS70845, TPS70848, TPS70851, TPS70858, TPS70802 DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS WITH INTEGRATED SVS FOR SPLIT VOLTAGE SYSTEMS SLVS301B – JUNE 2000 – REVISED OCTOBER 2002 TYPICAL CHARACTERISTICS OUTPUT IMPEDANCE vs FREQUENCY OUTPUT IMPEDANCE vs FREQUENCY 100 CO = 33 µF IO = 250 mA VOUT1 = 3.3 V TJ = 25°C Z O – Output Impedance – Ω Z O – Output Impedance – Ω 10 1 0.1 0.01 10 100 1k 10 k 100 k 1M 10 1 0.1 0.01 10 M CO = 33 µF IO = 10 mA VOUT1 = 3.3 V TJ = 25°C 10 100 100 k Figure 15 Figure 16 1M 10 M 1M 10 M OUTPUT IMPEDANCE vs FREQUENCY 10 100 CO = 33 µF IO = 125 mA VOUT2 = 1.8 V TJ = 25°C Z O– Output Impedance – Ω Z O – Output Impedance – Ω 10 k f – Frequency – Hz OUTPUT IMPEDANCE vs FREQUENCY 1 0.1 1k f – Frequency – Hz 10 100 1k 10 k 100 k 1M 10 M CO = 33 µF IO = 10 mA VOUT2 = 1.8 V TJ = 25°C 10 1 0.1 0.01 10 100 1k 10 k 100 k f – Frequency – Hz f – Frequency – Hz Figure 17 Figure 18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15 TPS70845, TPS70848, TPS70851, TPS70858, TPS70802 DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS WITH INTEGRATED SVS FOR SPLIT VOLTAGE SYSTEMS SLVS301B – JUNE 2000 – REVISED OCTOBER 2002 TYPICAL CHARACTERISTICS DROPOUT VOLTAGE vs JUNCTION TEMPERATURE DROPOUT VOLTAGE vs JUNCTION TEMPERATURE 120 6 CO = 33 µF VIN1 = 3.2 V CO = 33 µF VIN1 = 3.2 V 5 IO = 10 mA IO = 250 mA Dropout Voltage – mV Dropout Voltage – mV 100 80 60 40 20 4 3 2 1 IO = 0 mA 0 –40 –25 –10 5 20 35 50 65 80 95 110 125 TJ – Junction Temperature – °C 0 –40 –25 –10 5 20 35 50 65 80 95 110 125 TJ – Junction Temperature – °C Figure 19 Figure 20 TPS70802 TPS70802 DROPOUT VOLTAGE vs INPUT VOLTAGE DROPOUT VOLTAGE vs INPUT VOLTAGE 250 140 IO = 250 mA VOUT1 120 IO = 125 mA VOUT2 200 100 Dropout Voltage – mV Dropout Voltage – mV TJ = 125°C TJ = 25°C 80 60 TJ= – 40°C 40 TJ = 125°C 150 TJ = 25°C 100 TJ = – 40°C 50 20 0 2.5 3 3.5 4 4.5 5 0 2.5 VI – Input Voltage – V 3.5 Figure 22 POST OFFICE BOX 655303 4 VI – Input Voltage – V Figure 21 16 3 • DALLAS, TEXAS 75265 4.5 5 TPS70845, TPS70848, TPS70851, TPS70858, TPS70802 DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS WITH INTEGRATED SVS FOR SPLIT VOLTAGE SYSTEMS SLVS301B – JUNE 2000 – REVISED OCTOBER 2002 TYPICAL CHARACTERISTICS LOAD TRANSIENT RESPONSE IO – Output Current – mA IO – Output Current – mA LOAD TRANSIENT RESPONSE CO = 33 µF TJ = 25°C VOUT1 = 3.3 V 250 0 0 20 0 ∆ VO – Change in Output Voltage – mV 20 ∆ VO – Change in Output Voltage – mV CO = 33 µF TJ = 25°C VOUT2 = 1.8 V 125 0 –20 –40 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 –20 –40 –60 –80 2 0 0.2 0.4 0.6 0.8 t – Time – ms Figure 23 VI – Input Voltage – V 4.3 50 0 IO = 250 mA CO = 33 µF VOUT1 20 40 60 1.4 1.6 1.8 2 LINE TRANSIENT RESPONSE ∆ VO – Change in Output Voltage – mV VI – Input Voltage – V ∆ VO – Change in Output Voltage – mV 5.3 0 1.2 Figure 24 LINE TRANSIENT RESPONSE –50 1 t – Time – ms 80 100 120 140 160 180 200 t – Time – µs 3.8 2.8 10 0 IO = 125 mA CO = 33 µF VOUT2 –10 0 20 Figure 25 40 60 80 100 120 140 160 180 200 t – Time – µs Figure 26 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 17 TPS70845, TPS70848, TPS70851, TPS70858, TPS70802 DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS WITH INTEGRATED SVS FOR SPLIT VOLTAGE SYSTEMS SLVS301B – JUNE 2000 – REVISED OCTOBER 2002 TYPICAL CHARACTERISTICS VOUT2 – Output Voltage OUTPUT VOLTAGE vs TIME (START-UP) VO = 3.3 V CO = 33 µF IO = 250 mA VOUT2 = Standby 3 2 1 0 Enable Voltage (EN2) – V Enable Voltage (EN1) – V VOUT1 – Output Voltage OUTPUT VOLTAGE vs TIME (START-UP) 5 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 t – Time – ms 1.6 1.8 2.0 VO = 1.5 V CO = 33 µF IO = 125 mA VOUT1 = Standby 3 2 1 0 5 0 0 0.2 0.4 0.8 1.0 1.2 1.4 t – Time – ms 1.6 1.8 2.0 Figure 28 Figure 27 VI 0.6 To Load IN OUT + CO EN GND RL ESR Figure 29. Test Circuit for Typical Regions of Stability † Equivalent series resistance (ESR) refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance to CO. 18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TPS70845, TPS70848, TPS70851, TPS70858, TPS70802 DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS WITH INTEGRATED SVS FOR SPLIT VOLTAGE SYSTEMS SLVS301B – JUNE 2000 – REVISED OCTOBER 2002 TYPICAL CHARACTERISTICS TYPICAL REGION OF STABILITY TYPICAL REGION OF STABILITY EQUIVALENT SERIES RESISTANCE† vs OUTPUT CURRENT EQUIVALENT SERIES RESISTANCE† vs OUTPUT CURRENT 10 REGION OF INSTABILITY ESR – Equivalent Series Resistance – Ω ESR – Equivalent Series Resistance – Ω 10 VO = 3.3 V CO = 10 µF TJ = 25°C 1 0.1 50 mΩ REGION OF INSTABILITY REGION OF INSTABILITY VO = 3.3 V CO = 6.8 µF TJ = 25°C 1 250 mΩ REGION OF INSTABILITY 0.1 0.01 0 50 100 150 200 IO – Output Current – mA 250 0 50 100 150 200 IO – Output Current – mA Figure 30 TYPICAL REGION OF STABILITY TYPICAL REGION OF STABILITY EQUIVALENT SERIES RESISTANCE† vs OUTPUT CURRENT 10 REGION OF INSTABILITY ESR – Equivalent Series Resistance – Ω ESR – Equivalent Series Resistance – Ω Figure 31 EQUIVALENT SERIES RESISTANCE† vs OUTPUT CURRENT 10 VO = 1.8 V CO = 10 µF TJ = 25°C 1 250 0.1 50 mΩ REGION OF INSTABILITY REGION OF INSTABILITY VO = 1.8 V CO = 6.8 µF TJ = 25°C 1 250 mΩ REGION OF INSTABILITY 0.1 0.01 0 25 50 75 100 IO – Output Current – mA 125 0 Figure 32 25 50 75 100 IO – Output Current – mA 125 Figure 33 † Equivalent series resistance (ESR) refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance to CO. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 19 TPS70845, TPS70848, TPS70851, TPS70858, TPS70802 DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS WITH INTEGRATED SVS FOR SPLIT VOLTAGE SYSTEMS SLVS301B – JUNE 2000 – REVISED OCTOBER 2002 APPLICATION INFORMATION timing diagrams The following figures provide a timing diagram of how this device functions in different configurations. application conditions not shown in block diagram: VIN1 and VIN2 are tied to the same fixed input voltage greater than the VUVLO. PG2 is tied to MR. TPS708xxPWP (Fixed Output Option) VIN VIN1 explanation of timing diagrams: 0.1 µF EN1 and EN2 are initially high; therefore, both regulators are off, and PG1 and PG2 (tied to MR) are at logic low. Since MR is at logic low, RESET is also at logic low. When EN1 is taken to logic low, VOUT1 turns on. Later, when EN2 is taken to logic low, VOUT2 turns on. When VOUT1 reaches 95% of its regulated output voltage, PG1 goes to logic high. When VOUT2 reaches 95% of its regulated output voltage, PG2 (tied to MR) goes to logic high. When VIN1 is greater than VUVLO and MR (tied to PG2) is at logic high, RESET is pulled to logic high after a 120 ms delay. When EN1 and EN2 are returned to logic high, both devices power down and both PG1, PG2 (tied to MR2), and RESET return to logic low. VSENSE1 VIN2 0.1 µF >2 V EN1 RESET EN1 <0.7 V EN2 >2 V MR PG2 EN2 VOUT2 <0.7 V 95% 95% PG2 PG1 MR (PG2 tied to MR) RESET t1 120ms NOTES: A. t1 – Time at which VIN is greater than VUVLO and MR is logic high. B. The timing diagrams are not drawn to scale. Figure 34. Timing When VOUT1 Is Enabled Before VOUT2 20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MR 250 k RESET PG2 VSENSE2 EN1 VOUT1 10 µF 250 k PG1 EN2 VOUT2 VOUT1 VOUT1 VOUT2 10 µF TPS70845, TPS70848, TPS70851, TPS70858, TPS70802 DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS WITH INTEGRATED SVS FOR SPLIT VOLTAGE SYSTEMS SLVS301B – JUNE 2000 – REVISED OCTOBER 2002 APPLICATION INFORMATION application conditions not shown in block diagram: VIN1 and VIN2 are tied to the same fixed input voltage greater than VUVLO. MR is initially logic high but is eventually toggled. TPS708xxPWP (Fixed Output Option) VIN 0.1 µF VSENSE1 explanation of timing diagrams: EN1 and EN2 are initially high; therefore, both regulators are off, and PG1 and PG2 are at logic low. Since VIN1 is greater than VUVLO and MR is at logic high, RESET is also at logic high. When EN2 is taken to logic low, VOUT2 turns on. Later, when EN1 is taken to logic low, VOUT1 turns on. When VOUT2 reaches 95% of its regulated output voltage, PG2 goes to logic high. When VOUT1 reaches 95% of its regulated output voltage, PG1 goes to logic high. When MR is taken to logic low, RESET is taken low. When MR returns to logic high, RESET returns to logic high after a 120 ms delay. VOUT1 VOUT1 VIN1 10 µF 250 k 250 k PG1 VIN2 250 k 0.1 µF RESET PG2 EN1 EN1 MR >2 V >2 V <0.7 V EN2 EN2 VSENSE2 VOUT2 <0.7 V RESET PG2 MR 2V 0.7 V VOUT2 10 µF EN2 EN1 VOUT2 VOUT1 95% 95% PG2 PG1 MR RESET t1 120ms NOTES: A. t1 – Time at which VIN is greater than VUVLO and MR is logic high. B. The timing diagrams are not drawn to scale. Figure 35. Timing When MR Is Toggled POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 21 TPS70845, TPS70848, TPS70851, TPS70858, TPS70802 DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS WITH INTEGRATED SVS FOR SPLIT VOLTAGE SYSTEMS SLVS301B – JUNE 2000 – REVISED OCTOBER 2002 APPLICATION INFORMATION application conditions not shown in block diagram: VIN1 and VIN2 are tied to same fixed input voltage greater than VUVLO. PG1 is tied to MR. TPS708xxPWP (Fixed Output Option) VIN explanation of timing diagrams: 0.1 µF EN1 and EN2 are initially high; therefore, both regulators are off, and PG1 (tied to MR) and PG2 are at logic low. Since MR is at logic low, RESET is also at logic low. When EN2 is taken to logic low, VOUT2 turns on. Later, when EN1 is taken to logic low, VOUT1 turns on. When VOUT2 reaches 95% of its regulated output voltage, PG2 goes to logic high. When VOUT1 reaches 95% of its regulated output voltage, PG1 goes to logic high. When VIN1 is greater than VUVLO and MR (tied to PG2) is at logic high, RESET is pulled to logic high after a 120 ms delay. When a fault on VOUT1 causes it to fall below 95% of its regulated output voltage, PG1 (tied to MR) goes to logic low. Since MR is logic low, RESET goes to logic low. VOUT2 is unaffected. VSENSE1 PG1 MR VIN2 0.1 µF RESET PG2 EN1 EN1 EN2 EN2 >2 V VOUT2 <0.7 V PG2 95% PG2 PG1 MR (PG1 tied to MR) RESET t1 120ms NOTES: A. t1 – Time at which VIN is greater than VUVLO and MR is logic high. B. The timing diagrams are not drawn to scale. Figure 36. Timing When There Is a Fault on VOUT1 • DALLAS, TEXAS 75265 VOUT2 10 µF 95% POST OFFICE BOX 655303 RESET VSENSE2 <0.7 V FAULT ON VOUT1 22 250 k >2 V EN1 VOUT1 10 µF 250 k EN2 VOUT2 VOUT1 VOUT1 VIN1 TPS70845, TPS70848, TPS70851, TPS70858, TPS70802 DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS WITH INTEGRATED SVS FOR SPLIT VOLTAGE SYSTEMS SLVS301B – JUNE 2000 – REVISED OCTOBER 2002 APPLICATION INFORMATION input capacitor For a typical application, an input bypass capacitor (0.1 µF – 1 µF) is recommended. This capacitor will filter any high frequency noise generated in the line. For fast transient condition where droop at the input of the LDO may occur due to high inrush current, it is recommended to place a larger capacitor at the input as well. The size of this capacitor is dependant on the output current and response time of the main power supply, as well as the distance to the VI pins of the LDO. output capacitor As with most LDO regulators, the TPS708xx requires an output capacitor connected between OUT and GND to stabilize the internal control loop. The minimum recommended capacitance values are 10 µF ceramic capacitors with an ESR (equivalent series resistance) between 50-mΩ and 2.5-Ω or 6.8-µF tantalum capacitors with ESR between 250 mΩ and 4 Ω. Solid tantalum electrolytic, aluminum electrolytic, and multilayer ceramic capacitors with capacitance values greater than 10 µF are all suitable, provided they meet the requirements described above. Larger capacitors provide a wider range of stability and better load transient response. Below is a partial listing of surface-mount capacitors usable with the TPS708xx for fast transient response application. This information, along with the ESR graphs, is included to assist in selection of suitable capacitance for the user’s application. When necessary to achieve low height requirements along with high-output current and/or high-load capacitance, several higher ESR capacitors can be used in parallel to meet the guidelines above. VALUE MFR. MAX ESR† PART NO. 22 µF Kermet 345 mΩ 7495C226K0010AS 33 µF Sanyo 100 mΩ 10TPA33M 47 µF Sanyo 100 mΩ 6TPA47M 68 µF Sanyo 45 mΩ 10TPC68M ESR and transient response LDOs typically require an external output capacitor for stability. In fast transient response applications, capacitors are used to support the load current while LDO amplifier is responding. In most applications, one capacitor is used to support both functions. Besides its capacitance, every capacitor also contains parasitic impedances. These parasitic impedances are resistive as well as inductive. The resistive impedance is called equivalent series resistance (ESR), and the inductive impedance is called equivalent series inductance (ESL). The equivalent schematic diagram of any capacitor can therefore be drawn as shown in Figure 37. RESR LESL C Figure 37. ESR and ESL In most cases one can neglect the effect of inductive impedance ESL. Therefore, the following application focuses mainly on the parasitic resistance ESR. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 23 TPS70845, TPS70848, TPS70851, TPS70858, TPS70802 DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS WITH INTEGRATED SVS FOR SPLIT VOLTAGE SYSTEMS SLVS301B – JUNE 2000 – REVISED OCTOBER 2002 APPLICATION INFORMATION Figure 38 shows the output capacitor and its parasitic impedances in a typical LDO output stage. IO LDO – VESR RESR + + VI RLOAD VO – CO Figure 38. LDO Output Stage With Parasitic Resistances ESR In steady state (dc state condition), the load current is supplied by the LDO (solid arrow) and the voltage across the capacitor is the same as the output voltage (V(CO) = VO). This means no current is flowing into the CO branch. If IO suddenly increases (transient condition), the following occurs: D The LDO is not able to supply the sudden current need due to its response time. Therefore, capacitor CO provides the current for the new load condition (dashed arrow). CO now acts like a battery with an internal resistance, ESR. Depending on the current demand at the output, a voltage drop will occur at RESR. This voltage is shown as VESR in Figure 38. D When CO is conducting current to the load, initial voltage at the load will be VO = V(CO) – VESR. Due to the discharge of CO, the output voltage VO will drop continuously until the response time t1 of the LDO is reached and the LDO will resume supplying the load. From this point, the output voltage starts rising again until it reaches the regulated voltage. This period is shown as t2 in Figure 39. The figure also shows the impact of different ESRs on the output voltage. The left brackets show different levels of ESRs where number 1 displays the lowest and number 3 displays the highest ESR. From above, the following conclusions can be drawn: D The higher the ESR, the larger the droop at the beginning of load transient. D The smaller the output capacitor, the faster the discharge time and the bigger the voltage droop during the LDO response period. 24 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TPS70845, TPS70848, TPS70851, TPS70858, TPS70802 DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS WITH INTEGRATED SVS FOR SPLIT VOLTAGE SYSTEMS SLVS301B – JUNE 2000 – REVISED OCTOBER 2002 APPLICATION INFORMATION conclusion To minimize the transient output droop, capacitors must have a low ESR and be large enough to support the minimum output voltage requirement. IO VO 1 2 ESR 1 3 ESR 2 ESR 3 t1 t2 Figure 39. Correlation of Different ESRs and Their Influence to the Regulation of VO at a Load Step From Low-to-High Output Current POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 25 TPS70845, TPS70848, TPS70851, TPS70858, TPS70802 DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS WITH INTEGRATED SVS FOR SPLIT VOLTAGE SYSTEMS SLVS301B – JUNE 2000 – REVISED OCTOBER 2002 APPLICATION INFORMATION programming the TPS70802 adjustable LDO regulator The output voltage of the TPS70802 adjustable regulators is programmed using an external resistor divider as shown in Figure 40. Resistors R1 and R2 should be chosen for approximately 50-µA divider current. Lower value resistors can be used, but offer no inherent advantage and waste more power. Higher values should be avoided as leakage currents at the sense terminal increase the output voltage error. The recommended design procedure is to choose R2 = 30.1 kΩ to set the divider current at approximately 50 µA and then calculate R1 using: R1 + ǒ V V Ǔ O *1 ref R2 where Vref = 1.224 V typ (the internal reference voltage) OUTPUT VOLTAGE PROGRAMMING GUIDE TPS70802 VI OUTPUT VOLTAGE IN 0.1 µF >2.0 V OUT EN VO <0.7V R1 + R1 R2 UNIT 2.5 V 31.6 30.1 kΩ 3.3 V 51.1 30.1 kΩ 3.6 V 59.0 30.1 kΩ FB GND R2 Figure 40. TPS70802 Adjustable LDO Regulator Programming regulator protection Both TPS708xx PMOS-pass transistors have built-in back diodes that conduct reverse currents when the input voltage drops below the output voltage (e.g., during power down). Current is conducted from the output to the input and is not internally limited. When extended reverse voltage is anticipated, external limiting may be appropriate. The TPS708xx also features internal current limiting and thermal protection. During normal operation, the TPS708xx regulator 1 limits output current to approximately 1.6 A (typ) and regulator 2 limits output current to approximately 750 mA (typ). When current limiting engages, the output voltage scales back linearly until the overcurrent condition ends. While current limiting is designed to prevent gross device failure, care should be taken not to exceed the power dissipation ratings of the package. If the temperature of the device exceeds 150°C(typ), thermal-protection circuitry shuts it down. Once the device has cooled below 130°C(typ), regulator operation resumes. 26 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TPS70845, TPS70848, TPS70851, TPS70858, TPS70802 DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS WITH INTEGRATED SVS FOR SPLIT VOLTAGE SYSTEMS SLVS301B – JUNE 2000 – REVISED OCTOBER 2002 APPLICATION INFORMATION power dissipation and junction temperature Specified regulator operation is assured to a junction temperature of 125°C; the maximum junction temperature should be restricted to 125°C under normal operating conditions. This restriction limits the power dissipation the regulator can handle in any given application. To ensure the junction temperature is within acceptable limits, calculate the maximum allowable dissipation, PD(max), and the actual dissipation, PD, which must be less than or equal to PD(max). The maximum-power-dissipation limit is determined using the following equation: P T max * T A + J D(max) R qJA where TJmax is the maximum allowable junction temperature. RθJA is the thermal resistance junction-to-ambient for the package, i.e., 32.6°C/W for the 20-terminal PWP with no airflow. TA is the ambient temperature. The regulator dissipation is calculated using: P D ǒ Ǔ + V *V I O I O Power dissipation resulting from quiescent current is negligible. Excessive power dissipation triggers the thermal protection circuit. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 27 TPS70845, TPS70848, TPS70851, TPS70858, TPS70802 DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS WITH INTEGRATED SVS FOR SPLIT VOLTAGE SYSTEMS SLVS301B – JUNE 2000 – REVISED OCTOBER 2002 MECHANICAL DATA PWP (R-PDSO-G**) PowerPAD PLASTIC SMALL-OUTLINE PACKAGE 20-PIN SHOWN 0,30 0,19 0,65 20 0,10 M 11 Thermal Pad (See Note D) 4,50 4,30 0,15 NOM 6,60 6,20 Gage Plane 1 10 0,25 A 0°–ā8° 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 14 16 20 24 28 A MAX 5,10 5,10 6,60 7,90 9,80 A MIN 4,90 4,90 6,40 7,70 9,60 DIM 4073225/E 03/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusions. The package thermal performance may be enhanced by bonding the thermal pad to an external thermal plane. This pad is electrically and thermally connected to the backside of the die and possibly selected leads. E. Falls within JEDEC MO-153 PowerPAD is a trademark of Texas Instruments. 28 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third–party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Mailing Address: Texas Instruments Post Office Box 655303 Dallas, Texas 75265 Copyright 2002, Texas Instruments Incorporated