PCA9543A TWO-CHANNEL I C-BUS SWITCH WITH INTERRUPT LOGIC AND RESET 2 www.ti.com SCPS169 – SEPTEMBER 2007 FEATURES 1 • • • • • • • • • • • • • • 1-of-2 Bidirectional Translating Switches I2C Bus and SMBus Compatible Two Active-Low Interrupt Inputs Active-Low Interrupt Output Active-Low Reset Input Two Address Pins Allowing up to Four Devices on the I2C Bus Channel Selection Via I2C Bus, in Any Combination Power Up With All Switch Channels Deselected Low ron Switches Allows Voltage-Level Translation Between 1.8-V, 2.5-V, 3.3-V, and 5-V Buses No Glitch on Power Up • • • • Supports Hot Insertion Low Standby Current Operating Power-Supply Voltage Range of 2.3 V to 5.5 V 5-V Tolerant Inputs 0 to 400-kHz Clock Frequency Latch-Up Performance Exceeds 100 mA Per JESD78 ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) D PACKAGE (TOP VIEW) A0 1 14 VCC A1 2 13 SDA RESET 3 12 SCL INT0 4 PW PACKAGE (TOP VIEW) SD0 5 10 SC1 SC0 6 9 SD1 GND 7 8 INT1 13 SDA RESET 3 12 SCL INT0 SD0 SC0 GND 11 INT 14 VCC A0 1 A1 2 4 11 INT 5 10 SC1 6 9 SD1 7 8 INT1 DESCRIPTION/ORDERING INFORMATION The PCA9543A is a bidirectional translating switch controlled by the I2C bus. The SCL/SDA upstream pair fans out to two downstream pairs, or channels. Any individual SCn/SDn channel or combination of channels can be selected, determined by the contents of the programmable control register. Two interrupt inputs (INT0–INT1), one for each of the downstream pairs, are provided. One interrupt output (INT) acts as an AND of the two interrupt inputs. ORDERING INFORMATION PACKAGE (1) (2) TA SOIC – D –40°C to 85°C TSSOP – PW (1) (2) ORDERABLE PART NUMBER Tube of 50 PCA9543AD Reel of 2500 PCA9543ADR Tube of 90 PCA9543APW Reel of 2000 PCA9543APWR TOP-SIDE MARKING PCA9543A PD543A For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2007, Texas Instruments Incorporated PCA9543A TWO-CHANNEL I2C-BUS SWITCH WITH INTERRUPT LOGIC AND RESET www.ti.com SCPS169 – SEPTEMBER 2007 DESCRIPTION/ORDERING INFORMATION (CONTINUED) An active-low reset (RESET) input allows the PCA9543A to recover from a situation where one of the downstream I2C buses is stuck in a low state. Pulling RESET low resets the I2C state machine and causes all the channels to be deselected, as does the internal power-on reset function. The pass gates of the switches are constructed such that the VCC pin can be used to limit the maximum high voltage, which will be passed by the PCA9543A. This allows the use of different bus voltages on each pair, so that 1.8-V, 2.5-V, or 3.3-V parts can communicate with 5-V parts without any additional protection. External pullup resistors pull the bus up to the desired voltage level for each channel. All I/O pins are 5-V tolerant. TERMINAL FUNCTIONS 2 D AND PW PIN NUMBER NAME 1 A0 Address input 0. Connect directly to VCC or ground. 2 A1 Address input 1. Connect directly to VCC or ground. 3 RESET 4 INT0 Active-low interrupt input 0. Connect to VCC through a pullup resistor. 5 SD0 Serial data 0. Connect to VCC through a pullup resistor. 6 SC0 Serial clock 0. Connect to VCC through a pullup resistor. 7 GND Ground 8 INT1 Active-low interrupt input 1. Connect to VCC through a pullup resistor. 9 SD1 Serial data 1. Connect to VCC through a pullup resistor. 10 SC1 Serial clock 1. Connect to VCC through a pullup resistor. 11 INT Active-low interrupt output. Connect to VCC through a pullup resistor. 12 SCL Serial clock line. Connect to VCC through a pullup resistor. 13 SDA Serial data line. Connect to VCC through a pullup resistor. 14 VCC Supply power DESCRIPTION Active-low reset input. Connect to VCC through a pullup resistor, if not used. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): PCA9543A PCA9543A TWO-CHANNEL I C-BUS SWITCH WITH INTERRUPT LOGIC AND RESET 2 www.ti.com SCPS169 – SEPTEMBER 2007 BLOCK DIAGRAM SC0 6 PCA9543A 10 SC1 5 SD0 9 SD1 GND VCC RESET SCL 7 Switch Control Logic 14 3 Power-On Reset 1 12 2 I C Bus Control Input Filter SDA 13 INT0 4 8 INT1 Interrupt Logic 2 Output Filter 11 A0 A1 INT Figure 1. Block Diagram Device Address Following a start condition, the bus master must output the address of the slave it is accessing. The address of the PCA9543A is shown in Figure 2. To conserve power, no internal pullup resistors are incorporated on the hardware-selectable address pins and they must be pulled high or low. 1 1 1 Fixed 0 0 A1 A0 R/W Hardware selectable Figure 2. Slave Address PCA9543A The last bit of the slave address defines the operation to be performed. When set to a logic 1, a read is selected, while a logic 0 selects a write operation. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): PCA9543A 3 PCA9543A TWO-CHANNEL I2C-BUS SWITCH WITH INTERRUPT LOGIC AND RESET www.ti.com SCPS169 – SEPTEMBER 2007 Control Register Following the successful acknowledgement of the slave address, the bus master sends a byte to the PCA9543A, which is stored in the control register (see Figure 3). If multiple bytes are received by the PCA9543A, it saves the last byte received. This register can be written and read via the I2C bus. Channel Selection Bits (Read/Write) Interrupt Bits (Read Only) 7 6 X X 5 4 INT1 INT0 3 2 1 0 X X B1 B0 Channel 0 Channel 1 INT0 INT1 Figure 3. Control Register Control Register Definition One or several SCn/SDn downstream pairs, or channels, are selected by the contents of the control register (see Table 1). After the PCA9543A has been addressed, the control register is written. The two LSBs of the control byte are used to determine which channel or channels are to be selected. When a channel is selected, the channel becomes active after a stop condition has been placed on the I2C bus. This ensures that all SCn/SDn lines are in a high state when the channel is made active, so that no false conditions are generated at the time of connection. A stop condition must occur always right after the acknowledge cycle. Table 1. Control Register Write (Channel Selection), Control Register Read (Channel Status) (1) D7 (1) D6 INT1 INT0 D3 D2 X X X X X X X X X X X X 0 0 0 0 0 0 B1 X 0 1 0 B0 COMMAND 0 Channel 0 disabled 1 Channel 0 enabled Channel 1 disabled X 0 Channel 1 enabled No channel selected; power-up/reset default state Channel 0 and channel 1 can be enabled at the same time. Care should be taken not to exceed the maximum bus capacitance. Interrupt Handling The PCA9543A provides two interrupt inputs (one for each channel) and one open-drain interrupt output (see Table 2). When an interrupt is generated by any device, it is detected by the PCA9543A and the interrupt output is driven low. The channel does not need to be active for detection of the interrupt. A bit also is set in the control register. Bit 4 and Bit 5 of the control register correspond to the INT0 and INT1 inputs of the PCA9543A, respectively. Therefore, if an interrupt is generated by any device connected to channel 1, the state of the interrupt inputs is loaded into the control register when a read is accomplished. Likewise, an interrupt on any device connected to channel 0 would cause bit 4 of the control register to be set on the read. The master then can address the PCA9543A and read the contents of the control register to determine which channel contains the device generating the interrupt. The master then can reconfigure the PCA9543A to select this channel, and locate the device generating the interrupt and clear it. It should be noted that more than one device can provide an interrupt on a channel, so it is up to the master to ensure that all devices on a channel are interrogated for an interrupt. The interrupt inputs may be used as general-purpose inputs if the interrupt function is not required. If unused, interrupt input(s) must be connected to VCC through a pullup resistor. 4 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): PCA9543A PCA9543A TWO-CHANNEL I C-BUS SWITCH WITH INTERRUPT LOGIC AND RESET 2 www.ti.com SCPS169 – SEPTEMBER 2007 Table 2. Control Register Read (Interrupt) (1) (1) D7 D6 INT1 X X X X X 0 0 0 1 0 INT0 0 1 D3 D2 B1 B0 X X X X X X X X X 0 0 0 0 0 COMMAND No interrupt on channel 0 Interrupt on channel 0 No interrupt on channel 1 Interrupt on channel 1 No channel selected; power-up/reset default state Two interrupts can be active at the same time. RESET Input The RESET input can be used to recover the PCA9543A from a bus-fault condition. The registers and the I2C state machine within this device initialize to their default states if this signal is asserted low for a minimum of tWL. All channels also are deselected in this case. RESET must be connected to VCC through a pullup resistor. Power-On Reset When power is applied to VCC, an internal power-on reset holds the PCA9543A in a reset condition until VCC has reached VPOR. At this point, the reset condition is released and the PCA9543A registers and I2C state machine are initialized to their default states, all zeroes, causing all the channels to be deselected. Thereafter, VCC must be lowered below 0.2 V to reset the device. Voltage Translation The pass-gate transistors of the PCA9543A are constructed such that the VCC voltage can be used to limit the maximum voltage that is passed from one I2C bus to another. 5.0 Vpass (V) 4.0 Max Typ 3.0 Min 2.0 1.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC (V) Figure 4. Vpass Voltage vs VCC Figure 4 shows the voltage characteristics of the pass gate transistors (note that the graph was generated using the data specified in Electrical Characteristics section of this data sheet). In order for the PCA9543A to act as a voltage translator, the Vpass voltage should be equal to or lower than the lowest bus voltage. For example, if the main bus is running at 5 V and the downstream buses are 3.3 V and 2.7 V, Vpass must be equal to or below 2.7 V to effectively clamp the downstream bus voltages. As shown in Figure 4, Vpass(max) is at 2.7 V when the PCA9543A supply voltage is 3.5 V or lower, so the PCA9543A supply voltage could be set to 3.3 V. Pullup resistors then can be used to bring the bus voltages to their appropriate levels (see Figure 14). Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): PCA9543A 5 PCA9543A TWO-CHANNEL I2C-BUS SWITCH WITH INTERRUPT LOGIC AND RESET www.ti.com SCPS169 – SEPTEMBER 2007 I2C Interface The I2C bus is for two-way, two-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pullup resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy. One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the high period of the clock pulse as changes in the data line at this time is interpreted as control signals (see Figure 5). SDA SCL Data Line Stable; Data Valid Change of data allowed Figure 5. Bit Transfer Both data and clock lines remain high when the bus is not busy. A high-to-low transition of the data line while the clock is high is defined as the start condition (S). A low-to-high transition of the data line while the clock is high is defined as the stop condition (P) (see Figure 6). SDA SDA SCL SCL S P STOP Condition START Condition Figure 6. Definition of Start and Stop Conditions A device generating a message is a transmitter; a device receiving a message is the receiver. The device that controls the message is the master and the devices that are controlled by the master are the slaves (see Figure 7). SDA SCL Master Transmitter/ Receiver Slave Receiver Slave Transmitter/ Receiver Master Transmitter Master Transmitter/ Receiver 2 I C-Bus Multiplexer Slave Figure 7. System Configuration The number of data bytes transferred between the start and the stop conditions from transmitter to receiver is not limited. Each byte of eight bits is followed by one acknowledge (ACK) bit. The transmitter must release the SDA line before the receiver can send an ACK bit. 6 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): PCA9543A PCA9543A TWO-CHANNEL I C-BUS SWITCH WITH INTERRUPT LOGIC AND RESET 2 www.ti.com SCPS169 – SEPTEMBER 2007 When a slave receiver is addressed, it must generate an ACK after the reception of each byte. Also, a master must generate an ACK after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges must pull down the SDA line during the ACK clock pulse, so that the SDA line is stable low during the high pulse of the ACK-related clock period (see Figure 8). Setup and hold times must be taken into account. A master receiver must signal an end of data to the transmitter by not generating an acknowledge (NACK) after the last byte has been clocked out of the slave. This is done by the master receiver by holding the SDA line high. In this event, the transmitter must release the data line to enable the master to generate a stop condition. Data Output by Transmitter NACK Data Output by Receiver ACK SCL From Master 1 2 8 9 S Clock Pulse for Acknowledgment Start Condition Figure 8. Acknowledgment on I2C Bus Data is transmitted to the PCA9543A control register using the write mode shown in Figure 9. Control Register Slave Address SDA S 1 1 1 0 0 A1 A0 0 A X X X X X X R/W Acknowledge From Slave Start Condition B1 B0 A P Acknowledge From Slave Stop Condition Figure 9. Write Control Register Data is read from the PCA9543A control register using the read mode shown in Figure 10. Last Byte Control Register Slave Address SDA S 1 1 1 Start Condition 0 0 A1 A0 1 A X X INT1 INT0 R/W Acknowledge From Slave X X B1 B0 NA P No Acknowledge From Master Stop Condition Figure 10. Read Control Register Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): PCA9543A 7 PCA9543A TWO-CHANNEL I2C-BUS SWITCH WITH INTERRUPT LOGIC AND RESET www.ti.com SCPS169 – SEPTEMBER 2007 Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN MAX VCC Supply voltage range –0.5 7 V VI Input voltage range (2) –0.5 7 V II Input current ±20 mA IO Output current ±25 mA ±100 mA ±100 mA Continuous current through VCC Continuous current through GND D package 86 UNIT °C/W θJA Package thermal impedance (3) Ptot Total power dissipation 400 mW Tstg Storage temperature range –60 150 °C TA Operating free-air temperature range –40 85 °C (1) (2) (3) PW package 113 Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. The package thermal impedance is calculated in accordance with JESD 51-7. Recommended Operating Conditions (1) VCC Supply voltage High-level input voltage VIL Low-level input voltage TA Operating free-air temperature (1) 8 MAX 2.3 5.5 0.7 × VCC 6 VCC = 2.3 V to 3.6 V 0.7 × VCC VCC + 0.5 A1, A0, INT1, INT0, RESET VCC = 3.6 V to 4.5 V 0.7 × VCC VCC + 0.5 VCC = 4.5 V to 5.5 V 0.7 × VCC VCC + 0.5 SCL, SDA –0.5 0.3 × VCC A1, A0, INT1, INT0, RESET –0.5 0.3 × VCC –40 85 SCL, SDA VIH MIN UNIT V V V °C All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): PCA9543A PCA9543A TWO-CHANNEL I C-BUS SWITCH WITH INTERRUPT LOGIC AND RESET 2 www.ti.com SCPS169 – SEPTEMBER 2007 Electrical Characteristics (1) over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VPOR Power-on reset voltage TEST CONDITIONS No load: VI = VCC or GND (2) TYP MAX VPOR VCC MIN 1.6 2.1 5V 3.6 4.5 V to 5.5 V Vpass Switch output voltage VSWin = VCC, ISWout = –100 μA 2.6 3.3 V 3 V to 3.6 V IOH INT VO = VCC 1.6 II VOL = 0.6 V INT VOL = 0.4 V SCL, SDA VI = VCC or GND SC1–SC0, SD1–SD0 VI = VCC or GND A1, A0 VI = VCC or GND INT1–INT0 VI = VCC or GND RESET VI = VCC or GND Operating mode ICC fSCL = 100 kHz Low inputs VI = VCC or GND, IO = 0 VI = GND, IO = 0 Standby mode High inputs INT1–INT0 ΔICC Supplycurrent change SCL, SDA Ci (1) (2) 2.8 VI = VCC, IO = 0 2.3 V to 5.5 V 2 SCL or SDA input at 0.6 V, Other inputs at VCC or GND VI = VCC or GND INT1–INT0 VI = VCC or GND RESET VI = VCC or GND SCL VI = VCC or GND 3 7 6 10 μA mA 2.3 V to 5.5 V –1 2.3 V to 3.6 V –1 1 4.5 V to 5.5 V –1 100 2.3 V to 3.6 V –1 1 4.5 V to 5.5 V –1 50 2.3 V to 3.6 V –1 1 4.5 V to 5.5 V –1 50 2.3 V to 3.6 V –1 1 4.5 V to 5.5 V –1 50 1 5.5 V 17 50 3.6 V 6 20 2.7 V 3 16 5.5 V 0.3 1 3.6 V 0.1 1 2.7 V 0.1 1 5.5 V 0.3 1 3.6 V 0.1 1 2.7 V 0.1 1 8 20 8 20 8 20 8 20 2.3 V to 3.6 V 4 5 4.5 V to 5.5 V 4 5 2.3 V to 3.6 V 4 6 4.5 V to 5.5 V 4 6 2.3 V to 3.6 V 4 5 4.5 V to 5.5 V 4 5 2.3 V to 5.5 V 9 12 μA μA μA 2.3 V to 5.5 V SCL or SDA input at VCC – 0.6 V, Other inputs at VCC or GND A1, A0 100 3 One INT1–INT0 input at 0.6 V, Other inputs at VCC or GND One INT1–INT0 input at VCC – 0.6 V, Other inputs at VCC or GND V 1.5 1.1 2.3 V to 5.5 V VOL = 0.4 V SDA IOL V 4.5 1.9 2.5 V 2.3 V to 2.7 V UNIT pF For operation between published voltage ranges, refer to the worst-case parameter in both ranges. To reset the part, either RESET must be low or VCC must be lowered to 0.2 V. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): PCA9543A 9 PCA9543A TWO-CHANNEL I2C-BUS SWITCH WITH INTERRUPT LOGIC AND RESET www.ti.com SCPS169 – SEPTEMBER 2007 Electrical Characteristics (continued) over recommended operating free-air temperature range (unless otherwise noted) PARAMETER SDA Cio(OFF) (3) SC1–SC0, SD1–SD0 ron Switch on-state resistance TEST CONDITIONS VCC VI = VCC or GND, Switch OFF 2.3 V to 5.5 V VO = 0.4 V, IO = 15 mA VO = 0.4 V, IO = 10 mA (3) MIN TYP MAX 11 13 6 8 4.5 V to 5.5 V 4 9 20 3 V to 3.6 V 5 11 25 2.3 V to 2.7 V 7 16 50 UNIT pF Ω Cio(ON) depends on the device capacitance and load that is downstream from the device. I2C Interface Timing Requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure 11) STANDARD MODE I2C BUS MIN MAX 100 fscl I2C clock frequency 0 tsch I2C clock high time 4 2 tscl I C clock low time tsp I2C spike time tsds I2C serial-data setup time FAST MODE I2C BUS MAX 0 400 50 250 100 (1) (1) 0 μs 1.3 50 ns ns μs tsdh I C serial-data hold time ticr I2C input rise time 1000 20 + 0.1Cb (2) 300 ns ticf I2C input fall time 300 20 + 0.1Cb (2) 300 ns tocf I2C output fall time 300 20 + 0.1Cb (2) 300 ns 10-pF to 400-pF bus 2 0 kHz μs 0.6 4.7 2 UNIT MIN tbuf I C bus free time between stop and start 4.7 1.3 μs tsts I2C start or repeated start condition setup 4.7 0.6 μs tsth I2C start or repeated start condition hold 4 0.6 μs 2 tsps I C stop condition setup 4 tvdL(Data) Valid-data time (high to low) (3) SCL low to SDA output low valid tvdH(Data) Valid-data time (low to high) (3) SCL low to SDA output high valid tvd(ack) ACK signal from SCL low to SDA output low Cb (1) (2) (3) 10 Valid-data time of ACK condition 2 I C bus capacitive load μs 0.6 1 1 μs 0.6 0.6 μs 1 1 μs 400 400 pF A device internally must provide a hold time of at least 300 ns for the SDA signal (referred to as the VIH min of the SCL signal), in order to bridge the undefined region of the falling edge of SCL. Cb = total bus capacitance of one bus line in pF Data taken using a 1-kΩ pullup resistor and 50-pF load (see Figure 11) Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): PCA9543A PCA9543A TWO-CHANNEL I C-BUS SWITCH WITH INTERRUPT LOGIC AND RESET 2 www.ti.com SCPS169 – SEPTEMBER 2007 Switching Characteristics over recommended operating free-air temperature range, CL ≤ 100 pF (unless otherwise noted) (see Figure 13) PARAMETER RON = 20 Ω, CL = 15 pF FROM (INPUT) TO (OUTPUT) SDA or SCL SDn or SCn MIN MAX UNIT 0.3 tpd (1) Propagation delay time tiv Interrupt valid time (2) INTn INT 4 μs tir Interrupt reset delay time (2) INTn INT 2 μs (1) RON = 20 Ω, CL = 50 pF 1 ns The propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance). Data taken using a 4.7-kΩ pullup resistor and 100-pF load (see Figure 13) (2) Interrupt and Reset Timing Requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure 13) PARAMETER MIN (1) tPWRL Required low-level pulse duration of INTn inputs tPWRH Required high-level pulse duration of INTn inputs (1) tWL Pulse duration, RESET low trst (2) tREC (1) (2) MAX 1 μs 0.5 μs 4 ns RESET time (SDA clear) 500 Recovery time from RESET to start UNIT 0 ns ns The device has interrupt input rejection circuitry for pulses less than the listed minimum. trst is the propagation delay measured from the time the RESET pin is first asserted low to the time the SDA pin is asserted high, signaling a stop condition. It must be a minimum of tWL. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): PCA9543A 11 PCA9543A TWO-CHANNEL I2C-BUS SWITCH WITH INTERRUPT LOGIC AND RESET www.ti.com SCPS169 – SEPTEMBER 2007 PARAMETER MEASUREMENT INFORMATION VCC RL = 1 kΩ SDn, SCn DUT CL = 50 pF (See Note A) I2C PORT LOAD CONFIGURATION Two Bytes for Complete Device Programming Start Address Stop Address Bit 7 Condition Condition Bit 6 (S) (MSB) (P) BYTE Address Bit 1 R/W Bit 0 (LSB) ACK (A) Data Bit 7 (MSB) Data Bit 0 (LSB) ACK (A) Stop Condition (P) DESCRIPTION I2C 1 2 address + R/W Control register data tscl tsch 0.7 × VCC SCL tvd(ACK) or tvdL tvdH ticr ticf tbuf tsp 0.3 × VCC tsts 0.7 × VCC SDA 0.3 × VCC ticr ticf tsth tsdh tsds tsps Repeat Start Condition Start or Repeat Start Condition Stop Condition VOLTAGE WAVEFORMS A. CL includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf = 30 ns. C. The outputs are measured one at a time, with one transition per measurement. Figure 11. I2C Interface Load Circuit, Byte Descriptions, and Voltage Waveforms 12 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): PCA9543A PCA9543A TWO-CHANNEL I C-BUS SWITCH WITH INTERRUPT LOGIC AND RESET 2 www.ti.com SCPS169 – SEPTEMBER 2007 PARAMETER MEASUREMENT INFORMATION (continued) Figure 12. Reset Timing VCC RL = 4.7 kΩ DUT INT CL = 100 pF (See Note A) INTERRUPT LOAD CONFIGURATION INTn (input) 0.5 × VCC INTn (input) 0.5 × VCC tir tiv INT (output) 0.5 × VCC INT (output) VOLTAGE WAVEFORMS (tiv) 0.5 × VCC VOLTAGE WAVEFORMS (tir) A. CL includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf = 30 ns. Figure 13. Interrupt Load Circuit and Voltage Waveforms Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): PCA9543A 13 PCA9543A TWO-CHANNEL I2C-BUS SWITCH WITH INTERRUPT LOGIC AND RESET www.ti.com SCPS169 – SEPTEMBER 2007 APPLICATION INFORMATION Figure 14 shows an application in which the PCA9543A can be used. VCC = 2.7 V to 5.5 V VCC = 3.3 V VCC = 2.7 V to 5.5 V See Note A VCC 12 SCL SDA 13 11 I2C/SMBus Master SCL SD0 SDA SC0 INT0 INT 5 6 Channel 0 4 3 RESET PCA9543A VCC = 2.7 V to 5.5 V See Note A 2 1 7 NOTE: A1 SD1 A0 GND SC1 9 10 8 Channel 1 INT1 A. If the device generating the interrupt has an open-drain output structure or can be 3-stated, a pullup resistor is required. If the device generating the interrupt has a totem-pole output structure and cannot be 3-stated, a pullup resistor is not required. The interrupt inputs should not be left floating. B. Pin numbers shown are for the D and PW packages. Figure 14. Typical Application 14 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): PCA9543A PACKAGE OPTION ADDENDUM www.ti.com 22-Oct-2007 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty PCA9543AD ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PCA9543ADG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PCA9543ADR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PCA9543ADRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PCA9543APW ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PCA9543APWG4 ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PCA9543APWR ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PCA9543APWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 15-Oct-2007 TAPE AND REEL BOX INFORMATION Device Package Pins Site Reel Diameter (mm) Reel Width (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant PCA9543ADR D 14 SITE 41 330 16 6.5 9.0 2.1 8 16 Q1 PCA9543APWR PW 14 SITE 41 330 12 7.0 5.6 1.6 8 12 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com Device 15-Oct-2007 Package Pins Site Length (mm) Width (mm) Height (mm) PCA9543ADR D 14 SITE 41 346.0 346.0 33.0 PCA9543APWR PW 14 SITE 41 346.0 346.0 29.0 Pack Materials-Page 2 MECHANICAL DATA MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. 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