SN65LVCP408 www.ti.com....................................................................................................................................................................................................... SLLS842 – JUNE 2009 Gigabit 8 x 8 CROSSPOINT SWITCH • Up to 4.25 Gbps Operation • Non-Blocking Architecture Allows Each Output to be Connected to Any Input • 30 ps of Deterministic Jitter • Selectable Transmit Pre-Emphasis Per Lane • Selectable Receive Equalization • Available Packaging 64 Pin QFP • Propagation Delay Times: 500 ps Typical • Inputs Electrically Compatible With CML Signal Levels • Operates From a Single 3.3-V Supply • Ability to 3-STATE Outputs • Integrated Termination Resistors • I2C™ Control Interface 23 DESCRIPTION The SN65LVCP408 is a 8 × 8 non-blocking crosspoint switch in a flow-through pin-out allowing for ease in PCB layout. VML signaling is used to achieve a high-speed data throughput while using low power. Each of the output drivers includes a 8:1 multiplexer to allow any input to be routed to any output. Internal signal paths are fully differential to achieve the high signaling speeds while maintaining low signal skews. The SN65LVCP408 incorporates 100-Ω termination resistors for those applications where board space is a premium. Built-in transmit pre-emphasis and receive equalization for superior signal integrity performance. The SN65LVCP408 is characterized for operation from –40°C to 85°C. (See operating free air condition requirements) VCC I2C_EN SWT GND 0Y 0Z VCC 1Y 1Z GND 2Y 2Z VCC 3Y 3Z GND FEATURES 1 APPLICATIONS • • • • • Clock Buffering/Clock MUXing Wireless Base Stations High-Speed Network Routing Telecom/Datacom XAUI 802.3ae Protocol Backplane Redundancy 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 GND VCC RESN GND 0A 0B VCC 1A 1B GND 2A 2B VCC 3A 3B VBB 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 ADDR2 ADDR1 SDA SCL GND 4Y 4Z VCC 5Y 5Z GND 6Y 6Z VCC 7Y 7Z GND 4A 4B VCC 5A 5B GND 6A 6B VCC 7A 7B GND VCC EQ PRE 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 2 3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments. I2C is a trademark of Philips Electronics. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2009, Texas Instruments Incorporated SN65LVCP408 SLLS842 – JUNE 2009....................................................................................................................................................................................................... www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ADDR1 ADDR2 SCL SDA RESN I2C_EN I 2C IF Registers LOGIC DIAGRAM SWT 24 2x 1 MUX 24 24 VBB RT EQ 0A 0B RT 3 EQ PRE 2 0Y 0Z 8x1 MUX 3-State_0 3 VBB PRE 2 RT EQ 7A 7B 7Y 8x1 MUX RT 7Z EQ 3-State_7 8x 8 MUX 2 A. VBB: Receiver input internal biasing voltage (allows ac coupling) B. RT: Internal 50-Ω receiver termination (100-Ω differential) Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): SN65LVCP408 SN65LVCP408 www.ti.com....................................................................................................................................................................................................... SLLS842 – JUNE 2009 PIN FUNCTIONS Pin NAME NO. TYPE DESCRIPTION Differential Inputs (with 50-Ω termination to Vbb) xA=P; xB=N Line Side Differential Inputs CML compatible Differential Output xY=P; xZ=N Switch Side Differential Outputs. VML Inputs I2C Control Interface (SCL: Clock, SDA: Data, ADDR: Address) High Speed I/O xA 5, 8, 11, 14, 18, 21, 24 ,27 xB 6, 9, 12, 15, 19, 22, 25, 28 xY 34, 37, 40 43, 51, 54, 57, 60 xZ 33, 36, 39, 42, 50, 53, 56, 59 Control Signals SCL 45 SDA 46 ADDR1 47 ADDR2 48 EQ 31 Input Equalization setting when I2C is not enabled. EQ=0 for 13dB and setting EQ=1 for 9dB. PRE 32 Input Pre-Emphasis setting when I2C is not enabled. PRE=0 for 0 dB and PRE=1 for 6 dB I2C_EN 63 Input Enables I2C control interface I2C_EN=1 for enable; When EN=0 then the PRE and EQ pins are used to set the Pre-Emphasis and Equalization settings rather than the I2C register map. When EN=0 the I2C register map is still open for read and write operations. SWT 62 Input Enable switch event when toggled RESN 3 Input (Active Low) Configuration Reset. Resets I2C register space (Active Low). Note upon device startup the RESN pin must be driven low to reset the device registers. Power Supply 3.3v±5% Power Supply VCC 2, 7, 13, 20, 26, 30, 35, 41, 52, 58, 64 Power GND 1,4, 10, 17, 23, 29 , 38, 44, 49, 55, 61 Ground VBB 16 PowerPAD™ Input Receiver input biasing voltage Ground The ground center pad of the package must be connected to GND plane. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): SN65LVCP408 3 SN65LVCP408 SLLS842 – JUNE 2009....................................................................................................................................................................................................... www.ti.com EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS VCC IN+ RT(SE) = 50 W Gain Stage + EQ VCC RBBDC RT(SE) = 50 W IN− VBB ESD LineEndTermination Self−Biasing Network Figure 1. Equivalent Input Circuit Design OUT+ 49.9 W OUT− 49.9 W VOCM 1 pF Figure 2. Common-Mode Output Voltage Test Circuit AVAILABLE OPTIONS (1) (1) (2) TA DESCRIPTION –40°C to 85°C Serial multiplexer PACKAGED DEVICE (2) PAP (64 pin) SN65LVCP408 For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. The package is available taped and reeled. Add an R suffix to device types (e.g., SN65LVCP408PAP). Temperature range assumes 1 m/s airflow. PACKAGE THERMAL CHARACTERISTICS PACKAGE THERMAL CHARACTERISTICS (1) θJA (junction-to-ambient) (1) 4 NOM 100LFM airflow is required otherwise a 4x4 thermal via array must be implemented with 6 layer or greater PCB. 21.2 UNIT °C/W See application note SPRA953 for a detailed explanation of thermal parameters (http://www-s.ti.com/sc/psheets/spra953/spra953.pdf). Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): SN65LVCP408 SN65LVCP408 www.ti.com....................................................................................................................................................................................................... SLLS842 – JUNE 2009 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) UNIT Supply voltage range (2) VCC –0.5 V to 6 V Control inputs, all outputs Voltage range ESD TJ –0.5 V to (VCC + 0.5 V) Receiver inputs –0.5 V to 4 V Human Body Model (3) All pins 6 kV Charged-Device Model (4) All pins 500 V Maximum junction temperature See Package Thermal Characteristics Table Moisture sensitivity level 2 Reflow temperature package soldering, 4 seconds (1) (2) (3) (4) 260°C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values, except differential I/O bus voltages, are with respect to network ground terminal. Tested in accordance with JEDEC Standard 22, Test Method A114-A. Tested in accordance with JEDEC Standard 22, Test Method C101. RECOMMENDED OPERATING CONDITIONS dR Operating data rate VCC Supply voltage VCC(N) Supply voltage noise amplitude TJ Junction temperature TA Operating free-air temperature (1) MIN NOM MAX UNIT 4.25 Gbps 3.135 3.3 3.465 10 Hz to 2.125 GHz Assumes 4x4 thermal via array is implemented with 6 layer or greater PCB otherwise 100LFM airflow is required. V 20 mV 125 °C -40 85 °C 100 1750 mVPP 100 1560 mVPP 100 1000 mVPP DIFFERENTIAL INPUTS dR(in) ≤ 4.25 Gbps Receiver peak-to-peak differential input 1.25 Gbps < dR(in) ≤ 4.25 Gbps (2) voltage dR(in) > 4.25 Gbps VID VICM Receiver common-mode input voltage Note: for best jitter performance ac coupling is recommended. |V 1.5 1.6 VCC * | ID 2 V CONTROL INPUTS VIH High-level input voltage 2 VCC + 0.3 V VIL Low-level input voltage –0.3 0.8 V 120 Ω DIFFERENTIAL OUTPUTS RL (1) (2) Differential load resistance 80 100 Maximum free-air temperature operation is allowed as long as the device maximum junction temperature is not exceeded. Differential input voltage VID is defined as | IN+ – IN– |. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): SN65LVCP408 5 SN65LVCP408 SLLS842 – JUNE 2009....................................................................................................................................................................................................... www.ti.com ELECTRICAL CHARACTERISTICS over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT DIFFERENTIAL INPUTS VIT+ Positive going differential input high threshold VIT– Negative going differential input low threshold A(EQ) Equalizer gain RT(D) Termination resistance, differential VBB Open-circuit Input voltage (input self-bias voltage) R(BBDC) Biasing network dc impedance R(BBAC) Biasing network ac impedance 50 mV –50 at 1.875 GHz (EQ=1) mV 9 80 AC-coupled inputs 100 dB Ω 120 1.6 V 30 kΩ 375 MHz 42 2.125 GHz 8.4 Ω DIFFERENTIAL OUTPUTS VODH High-level output voltage VODL Low-level output voltage VODB Output differential voltage without preemphasis (2) VOCM Output common mode voltage ΔVOC(SS) Change in steady-state common-mode output voltage between logic states RL = 100 Ω ±1%, Pre-Emph=0 dB 1000 V ODB(PP) mVPP –650 mVPP 1300 1500 mVPP 1.8 See Figure 2 V 1 Output preemphasis voltage ratio, V(PE) 650 mV 0 3 RL = 100 Ω±1%; x = L or S; See Figure 3 dB 6 VODPE(PP) 10 t(PRE) Preemphasis duration measurement Output preemphasis is set to 10 dB during test Measured with a 100-MHz clock signal; RL = 100 Ω ±1%, See Figure 4 175 ps ro Output resistance Differential on-chip termination between OUT+ and OUT– 100 Ω CONTROL INPUTS IIH High-level Input current VIN = VCC IIL Low-level Input current VIN = GND R(PU) Pullup resistance 5 -125 µA -90 µA 35 kΩ POWER CONSUMPTION PD Device power dissipation All outputs terminated 100 Ω PZ Device power dissipation in 3-State All outputs in 3-state ICC Device current consumption All outputs terminated 100 Ω (1) (2) 6 PRBS 27-1 pattern at 4.25 Gbps 1.52 W 864 mW 440 mA All typical values are at TA = 25°C and VCC = 3.3 V supply unless otherwise noted. They are for reference purposes and are not production tested. Differential output voltage V(ODB) is defined as | OUT+ – OUT– |. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): SN65LVCP408 SN65LVCP408 www.ti.com....................................................................................................................................................................................................... SLLS842 – JUNE 2009 SWITCHING CHARACTERISTICS over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT MULTIPLEXER t(SM) Multiplexer switch time Multiplexer to valid output 15 ns 0.5 0.7 ns 0.5 0.7 ns DIFFERENTIAL OUTPUTS Low-to-high propagation delay tPLH tPHL High-to-low propagation delay tr Rise time tf Fall time tsk(p) Pulse skew, | tPHL – tPLH | tsk(o) Output skew (3) tsk(pp) Part-to-part skew (4) tzd 3-State switch time to Disable tze RJ Propagation delay input to output, See Figure 6 20% to 80% of VO(DB); Test Pattern: 100-MHz clock signal; See Figure 5 and Figure 8 90 ps 90 ps All outputs terminated with 100 Ω 25 (2) 20 ps 75 ps 150 ps Assumes 50 Ω to Vcm and 150 pF load on each output; Tested using I2C 30 ns 3-State switch time to Enable Assumes 50 Ω to Vcm and 150 pF load on each output; Tested using I2C 20 ns Device random jitter, rms See Figure 8 for test circuit. BERT setting 10–15 Alternating 10-pattern. 0 dB preemphasis Intrinsic deterministic device See Figure 8 for the test (5) jitter , peak-to-peak circuit. DJ (1) (2) (3) (4) (5) (6) 0 dB preemphasis Absolute deterministic See Figure 8 for the test (6) output jitter , peak-to-peak circuit. PRBS 27-1 pattern PRBS 27-1 pattern 0.8 4.25 Gbps 1.25Gbps; EQ=13dB Over 25-inch FR4 trace 4.25 Gbps; EQ=13dB Over FR4 trace 2-inch to 43 inches long 2 ps-rms 30 ps 15 ps 40 All typical values are at 25°C and with 3.3 V supply unless otherwise noted. tsk(p) is the magnitude of the time difference between the tPLH and tPHL of any output of a single device. tsk(o) is the magnitude of the time difference between the tPLH and tPHL of any two outputs of a single device. tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits. The SN65LVCP408 built-in passive input equalizer compensates for ISI. For a 25-inch FR4 transmission line with 8-mil trace width, the LVCP408 typically reduces jitter by 29 ps from the device input to the device output. Absolute deterministic output jitter reflects the deterministic jitter measured at the SN65LVCP408 output. The value is a real measured value with a Bit error tester as described in Figure 8. The absolute DJ reflects the sum of all deterministic jitter components accumulated over the link: DJ(absolute) = DJ(Signal generator) + DJ(transmission line) + DJ(intrinsic(LVCP408)). Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): SN65LVCP408 7 SN65LVCP408 SLLS842 – JUNE 2009....................................................................................................................................................................................................... www.ti.com PARAMETER MEASUREMENT INFORMATION 1−bit 1 to N bit 3−dB Preemphasis VODPE3(pp) 10−dB Preemphasis VOCM VODB(PP) VODPE2(pp) 6−dB Preemphasis VODPE1(pp) 0−dB Preemphasis VOH VOL Figure 3. Preemphasis and Output Voltage Waveforms and Definitions 1−bit VODPE3(pp) 10−dB Preemphasis 1 to N bit VODB(PP) 80% 20% tPRE Figure 4. t(PRE) Preemphasis Duration Measurement 80% 80% VODB 20% 20% tr tf Figure 5. Driver Output Transition Time 8 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): SN65LVCP408 SN65LVCP408 www.ti.com....................................................................................................................................................................................................... SLLS842 – JUNE 2009 PARAMETER MEASUREMENT INFORMATION (continued) VID = 0 V IN t PHLD t PLHD VOD = 0 V OUT Figure 6. Propagation Delay Input to Output VA Clock Input VID = 0 V VOD = 0 V Ideal Output VB VY − VZ 1/fo Period Jitter 1/fo Cycle-to-Cycle Jitter Actual Output Actual Output VOD = 0 V VOD = 0 V VY − VZ VY − VZ tc(n) tc(n) tc(n +1) tjit(cc) = | tc(n) − tc(n + 1) | tjit(pp) = | tc(n) − 1/fo | Peak-to-Peak Jitter VA PRBS Input VY PRBS Output VID = 0 V VOD = 0 V VZ VB tjit(pp) A. All input pulses are supplied by an Agilent 81250 Stimulus System. B. The measurement is made with the AgilentParBert measurement software. Figure 7. Driver Jitter Measurement Waveforms Pattern Generator DC Block Coax DC Block Coax DC Block Pre-amp SMA SMA 400 mVPP 25-inch FR4 (63,5 cm) Coupled Transmission Line RX + EQ <3-inch 50 W TL (7,62 cm) SMA <3-inch 50 W TL (7,62 cm) SMA Coax DC Block Coax SN65LVCP408 Differential Jitter Test Instruments Characterization Test Board For the rise/fall time measurements, the 25-inch FR4 transmission line is removed. Figure 8. AC Test Circuit — Jitter and Output Rise Time Test Circuit The SN65LVCP408 input equalizer provides frequency gain to compensate for frequency loss of a shorter backplane transmission line. For characterization purposes, a 25-inch (63,5 cm) FR-4 coupled transmission line is used in place of the backplane trace. The 25-inch trace provides roughly 5 dB of attenuation between 375 MHz and 2.125 GHz, representing closely the characteristics of a short backplane trace. The loss tangent of the FR4 in the test board is 0.018 with an effective ε(r) of 4.1. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): SN65LVCP408 9 SN65LVCP408 SLLS842 – JUNE 2009....................................................................................................................................................................................................... www.ti.com TYPICAL DEVICE BEHAVIOR Eye After 43-inch FR-4 Trace, Input 400 mVPP Eye After 43-inch FR-4 Trace, Input 400 mVPP, Through the 408 With Pre-emphasis at 3 dB 0 0 0 1 0dB 3dB 1 1 0 1 6dB 10dB 100 ps/div Pre-emphasis Levels Figure 10. Preemphasis Signal Shape 50 ps/div Figure 9. Data Input and Output Pattern 4.25-Gbps Signal Generator PRBS 27 - 1 400 mVPP Input 43-inch, 129,54 cm FR4 LVCP408 Output with 10-dB Preamp 35-inch, 88,9 cm FR4 Output with 0-dB Preamp 35-inch, 88,9 cm FR4 Figure 11. Data Output Pattern 10 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): SN65LVCP408 SN65LVCP408 www.ti.com....................................................................................................................................................................................................... SLLS842 – JUNE 2009 TYPICAL CHARACTERISTICS DETERMINISTIC OUTPUT JITTER vs DIFFERENTIAL INPUT AMPLITUDE 1400 50 27-1 PRBS pattern, The DJ is Measured on the Output of the LVCP408 60 4.25 Gbps 45 Deterministic Output jitter - ps Deterministic Output Jitter - ps 70 50 40 30 20 10 1200 2.5 Gbps 40 1000 3.125 Gbps 35 30 3.75 Gbps 25 1.25 Gbps 20 15 10 5 0 0 1 2 3 4 5 6 DR - Data Rate - Gbps 7 0 8 800 600 400 200 0 0 0 400 800 1200 1600 2000 VID - Differential Input Amplitude - mVPP Figure 12. 1 2 3 4 5 6 DR - Data Rate - Gbps Figure 13. SUPPLY NOISE vs DETERMINISTIC JITTER vs DATA RATE 7 8 Figure 14. DETERMINISTIC OUTPUT JITTER vs COMMON-MODE INPUT VOLTAGE 16 50 Noise = 650 mVPP 40 35 30 25 20 Noise = 300 mVPP 15 Noise = 200 mVPP Noise = 100 mVPP 10 Noise = 50 mVPP Deterministic Output Jitter - ps Noise = 400 mVPP 45 Deterministic Output Jitter - ps DIFFERENTIAL OUTPUT VOLTAGE vs DATA RATE VOD - Differential Output Voltage - VPP DETERMINISTIC OUTPUT JITTER vs DATA RATE 14 12 10 8 6 4 2 5 0 0 0 0.5 1 1.5 2 2.5 3 3.5 DR - Data Rate - Gbps 4 4.5 0 0.5 1 1.5 2 2.5 3 VIC - Common Mode Input Voltage - V Figure 15. Figure 16. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): SN65LVCP408 11 SN65LVCP408 SLLS842 – JUNE 2009....................................................................................................................................................................................................... www.ti.com I2C CONTROL INTERFACE I2C Interface Notes The I2C interface is used to access the internal registers of the SN65LVCP408. I2C is a two-wire serial interface developed by Philips Semiconductor (see I2C-Bus Specification, Version 2.1, January 2000). The bus consists of a data line (SDA) and a clock line (SCL) with pull-up structures. When the bus is idle, both SDA and SCL lines are pulled high. All the I2C compatible devices connect to the I2C bus through open drain I/O pins, SDA and SCL. A master device, usually a microcontroller or a digital signal processor, controls the bus. The master is responsible for generating the SCL signal and device addresses. The master also generates specific conditions that indicate the START and STOP of data transfer. A slave device receives and/or transmits data on the bus under control of the master device. The SN65LVCP408 works as a slave and supports the standard mode transfer (100 kbps) . The basic I2C start and stop access cycles are shown in Figure 17. The basic access cycle consists of the following: • A start condition • A slave address cycle • Any number of data cycles • A stop condition SDA SCL S P Start Condition Stop Condition Figure 17. I2C Start and Stop Conditions General I2C Protocol • • • • • 12 The master initiates data transfer by generating a start condition. The start condition is when a high-to-low transition occurs on the SDA line while SCL is high, as shown in Figure 17. All I2C-compatible devices should recognize a start condition. The master then generates the SCL pulses and transmits the 7-bit address and the read/write direction bit R/W on the SDA line. During all transmissions, the master ensures that data is valid. A valid data condition requires the SDA line to be stable during the entire high period of the clock pulse (see Figure 18). All devices recognize the address sent by the master and compare it to their internal fixed addresses. Only the slave device with a matching address generates an acknowledge (see Figure 19) by pulling the SDA line low during the entire high period of the ninth SCL cycle. On detecting this acknowledge, the master knows that a communication link with a slave has been established. The master generates further SCL cycles to either transmit data to the slave (R/W bit 0) or receive data from the slave (R/W bit 1). In either case, the receiver needs to acknowledge the data sent by the transmitter. So an acknowledge signal can either be generated by the master or by the slave, depending on which one is the receiver. The 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long as necessary (see Figure 20). To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line from low to high while the SCL line is high (see Figure 17). This releases the bus and stops the communication link with the addressed slave. All I2C compatible devices must recognize the stop condition. Upon the receipt of a stop condition, all devices know that the bus is released, and they wait for a start condition followed by a matching address. All bytes are transmitted most significant bit first. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): SN65LVCP408 SN65LVCP408 www.ti.com....................................................................................................................................................................................................... SLLS842 – JUNE 2009 Table 1. I2C Timing PARAMETER TEST CONDITIONS MIN TYP 2 MAX UNIT 100 kHz fSCL SCL clock frequency for internal register Local I C tW(L) Clock LOW period for I2C register Local I2C 4.7 µs tW(H) Clock HIGH period for internal register Local I2C 4 µs tSU1 Internal register setup time, SDA to SCL Local I2C 250 µs 2 0 µs 2 th(1) Internal register hold time, SCL to SDA t(buf) Internal register bus free time between STOP and START Local I C Local I C 4.7 µs tsu(2) Internal register setup time, SCL to START Local I2C 4.7 µs th(2) Internal register hold time, START to SCL Local I2C 4 µs tsu(3) Internal register hold time, SCL to STOP Local I2C 4 µs SDA SCL Data Line Stable; Data Valid Change of Data Allowed 2 Figure 18. I C Bit Transfer Data Output by Transmitter Not Acknowledge Data Output by Receiver Acknowledge SCL From Master 1 2 S 8 9 Clock Pulse for Acknowledgement Start Condition Figure 19. I2C Acknowledge Note: Following power up, this device must be reset. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): SN65LVCP408 13 SN65LVCP408 SLLS842 – JUNE 2009....................................................................................................................................................................................................... www.ti.com handbook, full pagewidth SDA SCL 1–7 8 9 1–7 8 9 1–7 8 9 P S START ADDRESS condition R/W ACK DATA ACK DATA ACK STOP condition Figure 20. I2C Address and Data Cycles During a write cycle, the slave sends an acknowledge (A) after every byte that follows the device address. The first byte following the device address is the register address, which maps to the register addresses specific to the device. The second byte following the device address is the data byte to be written at the register address (see Figure 21). If only the register address is to be written for a subsequent read sequence, the data byte is omitted and the sequence ends with a Stop (see Figure 22) or a repeated Start after the register address byte (see Figure 24). If multiple data bytes are to be written at subsequent register addresses, the master may continue to send data bytes after each slave acknowledge, and the slave device automatically increments the register address. Note that the master must not drive the SDA signal line during the slave acknowledge since the slave is in control of the SDA bus and may be holding it low. During a read cycle, the slave acknowledges the initial address byte if it decodes the device address as its own device address. Following this initial acknowledge by the slave, the master device becomes a receiver and acknowledges data bytes sent by the slave. The first byte received by the master is the data stored at the register address, while subsequent bytes are data stored at incrementing register addresses. When the master has received all of the requested data bytes from the slave, the not acknowledge (A) condition is initiated by the master by keeping the SDA signal high just before it asserts the Stop (P) condition. This sequence terminates a read cycle as shown in Figure 23. A combined format is when the read cycle is preceded by a write cycle for setting the register address, and is shown in Figure 24. Repeat n Times S Slave Address W A Register Address A A = Not Acknowledge (SDA High) A = Acknowledge (SDA Low) S = Start Condition P = Stop Condition W = Write (SDA Low) R = Read (SDA High) Register Data A P From Master From Slave Figure 21. I2C Write Cycle with Register Address and Data S Slave Address W A Register Address A = Not Acknowledge (SDA High) A = Acknowledge (SDA Low) S = Start Condition P = Stop Condition W = Write (SDA Low) R = Read (SDA High) A P From Master From Slave Figure 22. I2C Write Cycle with Register Address Only 14 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): SN65LVCP408 SN65LVCP408 www.ti.com....................................................................................................................................................................................................... SLLS842 – JUNE 2009 Repeat n Times S Slave Address R Register Data A A/A A = Not Acknowledge (SDA High) A = Acknowledge (SDA Low) S = Start Condition P = Stop Condition W = Write (SDA Low) R = Read (SDA High) P From Master From Slave Figure 23. I2C Read Cycle Repeat n Times S Slave Address W A Register Address A S Slave Address R A Register Data A/A P From Master A = Not Acknowledge (SDA High) A = Acknowledge (SDA Low) S = Start Condition P = Stop Condition W = Write (SDA Low) R = Read (SDA High) From Slave Figure 24. I2C Combined Format Write/Read Cycle Slave Address Both SDA and SCL must be connected to a positive supply voltage via a pull-up resistor. These resistors should comply with the I2C specification that ranges from 2 kΩ to 19 kΩ. When the bus is free, both lines are high. The slave address is the first 7 bits received following the START condition from the master device. The first 5 Bits (MSBs) of the address are factory preset to 01011. The next two bits of the SN65LVCP408 address are controlled by the logic levels appearing on the ADDR2 and ADDR1 pins. The ADDR2 and ADDR1 address inputs can be connected to VCC for logic 1, GND for logic 0, or can be actively driven by TTL/CMOS logic levels. The device addresses are set by the state of these pins and are not latched. Thus a dynamic address control system could be utilized to incorporate several devices on the same system. Up to four SN65LVCP408 devices can be connected to the same I2C-Bus without requiring additional glue logic. Table 2 lists the possible addresses for the SN65LVCP408. Table 2. Slave Addresses Fixed Address Selectable with Address Pins Bit 6 (MSB) Bit 5 Bit 4 Bit 3 Bit 2 Bit 1(addr2) Bit 0 (addr1) 0 1 0 1 1 0 0 0 1 0 1 1 0 1 0 1 0 1 1 1 0 0 1 0 1 1 1 1 Note: Following power up, this device must be reset. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): SN65LVCP408 15 SN65LVCP408 SLLS842 – JUNE 2009....................................................................................................................................................................................................... www.ti.com Table 3. Port Register Addresses Register Name Register Address Output Port 0 0000 0000 Output Port 1 0000 0001 Output Port 2 0000 0010 Output Port 3 0000 0011 Output Port 4 0000 0100 Output Port 5 0000 0101 Output Port 6 0000 0110 Output Port 7 0000 0111 Input Port 0 0000 1000 Input Port 1 0000 1001 Input Port 2 0000 1010 Input Port 3 0000 1011 Input Port 4 0000 1100 Input Port 5 0000 1101 Input Port 6 0000 1110 Input Port 7 0000 1111 Switch Control 0001 0000 Reserved for TI use 0001 0001 to 0001 1010 Table 4. Output Port Control Registers Bit Function 7 6 Default 0 Input Port Select No.1 5 0 0 4 Note Access Selects the desired input port to be used by the output port. Defaults to same port number as the ouput port. Valid values are : 000 for port 1, 001 for port 1...etc Pre-Emphasis 00 Pre-Emphasis setting. Valid Values are: 00 = 0 dB; 01 = 3 dB; 10 = 6dB, and 11= 10dB; Note When EN=0 then the PRE pin is used to set the Pre-Emphasis setting rather than the I2C register map. 2 Port 3-State 0 3-State Off = 0; 3-State On=1 1 RSVD 0 Reserved 0 RSVD 0 Reserved 3 R/W R Table 5. Input Port Control Registers Bit Function 7 Rx Equalization Select 6 5 Default 0 0 Input Port Select No.2 4 0 0 Note Access Rx Equalization Setting; 0 = 13dB ; 1 = 9dB; Note When EN=0 then the EQ pin is used to set the Equalization setting rather than the I2C register map. Selects the desired input port to be used by the ouput port when the switch event is triggered. Defaults to same port number as the ouput port. Valid values are : 000 for port 0, 001 for port 1...etc 3 RSVD 0 Reserved 2 RSVD 0 Reserved 1 RSVD 0 Reserved 0 RSVD 0 Reserved R/W R Note: Following power up, this device must be reset. 16 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): SN65LVCP408 SN65LVCP408 www.ti.com....................................................................................................................................................................................................... SLLS842 – JUNE 2009 Table 6. Switch Control Bit Function Default Note Access 2 7 Enable Switch Via Pin 0 0= Switch Via I C bit is used to enable the switch event; 1 = Switch via SWT pin; When SWT is logic 0, Port Select No. 1 settings will be used. When SWT is logic 1, the Port Select No. 2 settings will be used. The Switch Via i2C setting will be ignored. 6 Switch Via I2C 0 Selects between Port Select No. 1 and No. 2 when enable Switch Via Pin is 0. 0= Port Select No. 1, 1=Port Select No. 2 5 RSVD 0 Reserved 4 RSVD 0 Reserved 3 RSVD 0 Reserved 2 RSVD 0 Reserved 1 RSVD 0 Reserved 0 RSVD 0 Reserved R/W R Table 7. Reserved for TI Use Bit Function Default 7:0 RSVD - Note Read only value is indeterministic Access R Switching Options For each output port, users can select two possible input port selection profiles (i.e. sources that indicate which input port to use for the ouput). Input port select No. 1 I2C™ register bits are used to select the configuration of each output port that is used for default operation. (Note: on power up and after resetting the I2C register space with the RESN pin, each output port is mapped to its matching input port. For example, output port 0 is mapped to input port 0, and output port 1 is mapped to input port 1, etc.). Input Port Select No. 2 registers are used to select the secondary output port configuration that is used when the switch event is triggered. Triggering Switch Event Switching between the active output port configuration and the secondary output port configuration (configuration selected with Input Port Select No 2 registers) is accomplished in two ways: 1. The switch event can be triggered using the I2C register bit Switch Via I2C and setting it to 1 (high). 2. If the switch event needs to occur faster than the I2C access allows, then users have the option to use the SWT pin (pin #62) to trigger the switch from port configuration No. 1 to port configuration No. 2. For this option, users should set the Enable Switch Via I2C register bit to 1 upon initial start up. The SWT pin should be logic high state to initiate the switch. Changing the logic states of the SWT pin causes the port configurations to move between the two port configuration options. APPLICATION INFORMATION BANDWIDTH REQUIREMENTS Error free transmission of data over a transmission line has specific bandwidth demands. It is helpful to analyze the frequency spectrum of the transmit data first. For an 8B10B coded data stream at 3.75 Gbps of random data, the highest bit transition density occurs with a 1010 pattern (1.875 GHz). The least transition density in 8B10B allows for five consecutive ones or zeros. Hence, the lowest frequency of interest is 1.875 GHz/5 = 375 MHz. Real data signals consist of higher frequency components than sine waves due to the fast rise time. The faster the rise time, the more bandwidth becomes required. For 80-ps rise time, the highest important frequency component is at least 0.6/(π × 80 ps) = 2.4 GHz. Figure 25 shows the Fourier transformation of the 375-MHz and 1.875-GHz trapezoidal signal. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): SN65LVCP408 17 SN65LVCP408 SLLS842 – JUNE 2009....................................................................................................................................................................................................... www.ti.com Signal Amplitude − dB 0 20 dB/dec 1875 MHz With 80 ps Rise Time −5 20 dB/dec 375 MHz With 80 ps Rise Time −10 40 dB/dec −15 80% 20% tr −20 −25 40 dB/dec tPeriod = 1/f 100 1000 f − Frequency − MHz 1/(pi x 100/60 tr) = 2.4 GHz 10000 Figure 25. Approximate Frequency Spectrum of the Transmit Output Signal With 80 ps Rise Time The spectrum analysis of the data signal suggests building a backplane with little frequency attenuation up to 2 GHz. This is achievable only with expensive, specialized PCB material. To support material like FR4, a compensation technique is necessary to compensate for backplane imperfections. EXPLANATION OF EQUALIZATION Backplane designs differ widely in size, layer stack-up, and connector placement. In addition, the performance is impacted by trace architecture (trace width, coupling method) and isolation from adjacent signals. Common to most commercial backplanes is the use of FR4 as board material and its related high-frequency signal attenuation. Within a backplane, the shortest to longest trace lengths differ substantially – often ranging from 8 inches up to 40 inches. Increased loss is associated with longer signal traces. In addition, the backplane connector often contributes a good amount of signal attenuation. As a result, the frequency signal attenuation for a 300-MHz signal might range from 1 dB to 4 dB while the corresponding attenuation for a 2-GHz signal might span 6 dB to 24 dB. This frequency dependent loss causes distortion jitter on the transmitted signal. Each LVCP408 receiver input incorporates an equalizer and compensates for such frequency loss. The SN65LVCP408 equalizer provides 5 dB of frequency gain between 375 MHz and 1.875 GHz, compensating roughly for 20 inches of FR4 material with 8-mil trace width. Distortion jitter improvement is substantial, often providing more than 30-ps jitter reduction. The 5-dB compensation is sufficient for most short backplane traces. For longer trace lengths, it is recommended to enable transmit preemphasis in addition. SETTING THE PREEMPHASIS LEVEL The receive equalization compensates for ISI. This reduces jitter and opens the data eye. In order to find the best preemphasis setting for each link, calibration of every link is recommended. Assuming each link consists of a transmitter (with adjustable pre-emphasis such as LVCP408) and the LVCP408 receiver, the following steps are necessary: 1. Set the transmitter and receiver to 0-dB preemphasis; record the data eye on the LVCP408 receiver output. 2. Increase the transmitter preemphasis until the data eye on the LVCP408 receiver output looks the cleanest. 18 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): SN65LVCP408 PACKAGE OPTION ADDENDUM www.ti.com 17-Jun-2009 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty SN65LVCP408PAPR ACTIVE HTQFP PAP 64 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR SN65LVCP408PAPT ACTIVE HTQFP PAP 64 250 CU NIPDAU Level-3-260C-168 HR Green (RoHS & no Sb/Br) Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 15-Jun-2009 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel Diameter Width (mm) W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN65LVCP408PAPR HTQFP PAP 64 1000 330.0 24.4 13.0 13.0 1.4 16.0 24.0 Q2 SN65LVCP408PAPT HTQFP PAP 64 250 330.0 24.4 13.0 13.0 1.4 16.0 24.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 15-Jun-2009 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN65LVCP408PAPR HTQFP PAP 64 1000 346.0 346.0 41.0 SN65LVCP408PAPT HTQFP PAP 64 250 346.0 346.0 41.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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