SN74ALVC164245 16-BIT 2.5-V TO 3.3-V/3.3-V TO 5-V LEVEL-SHIFTING TRANSCEIVER WITH 3-STATE OUTPUTS www.ti.com SCAS416P – MARCH 1994 – REVISED NOVEMBER 2005 FEATURES • • • • • Member of the Texas Instruments Widebus™ Family Max tpd of 5.8 ns at 3.3 V ±24-mA Output Drive at 3.3 V Control Inputs VIH/VIL Levels Are Referenced to VCCA Voltage Latch-Up Performance Exceeds 250 mA Per JESD 17 NOTE: New and improved versions of the SN74ALVC164245 are available. The new part numbers are SN74LVC16T245 and SN74LVCH16T245 and should be considered for new designs. DESCRIPTION/ORDERING INFORMATION This 16-bit (dual-octal) noninverting bus transceiver contains two separate supply rails. B port has VCCB, which is set to operate at 3.3 V and 5 V. A port has VCCA, which is set to operate at 2.5 V and 3.3 V. This allows for translation from a 2.5-V to a 3.3-V environment, and vice versa, or from a 3.3-V to a 5-V environment, and vice versa. The SN74ALVC164245 is designed for asynchronous communication between data buses. The control circuitry (1DIR, 2DIR, 1OE, and 2OE) is powered by VCCA. To ensure the high-impedance state during power up or power down, the output-enable (OE) input should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. DGG OR DL PACKAGE (TOP VIEW) 1DIR 1B1 1B2 GND 1B3 1B4 (3.3 V, 5 V) VCCB 1B5 1B6 GND 1B7 1B8 2B1 2B2 GND 2B3 2B4 (3.3 V, 5 V) VCCB 2B5 2B6 GND 2B7 2B8 2DIR 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 17 32 18 31 19 30 20 29 21 28 22 27 23 26 24 25 1OE 1A1 1A2 GND 1A3 1A4 VCCA (2.5 V, 3.3 V) 1A5 1A6 GND 1A7 1A8 2A1 2A2 GND 2A3 2A4 VCCA (2.5 V, 3.3 V) 2A5 2A6 GND 2A7 2A8 2OE ORDERING INFORMATION PACKAGE (1) TA FBGA – GRD FBGA – ZRD (Pb-free) Tape and reel Tube of 25 SSOP – DL –40°C to 85°C Reel of 1000 Reel of 2000 TSSOP – DGG Reel of 250 VFBGA – GQL VFBGA – ZQL (Pb-free) (1) Reel of 1000 ORDERABLE PART NUMBER 74ALVC164245GRDR 74ALVC164245ZRDR TOP-SIDE MARKING VC4245 SN74ALVC164245DL SN74ALVC164245DLR ALVC164245 74ALVC164245DLRG4 SN74ALVC164245DGGR 74ALVC164245DGGRG4 SN74ALVC164245DGGT ALVC164245 74ALVC164245DGGTE4 SN74ALVC164245KR 74ALVC164245ZQLR VC4245 Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 1994–2005, Texas Instruments Incorporated SN74ALVC164245 16-BIT 2.5-V TO 3.3-V/3.3-V TO 5-V LEVEL-SHIFTING TRANSCEIVER WITH 3-STATE OUTPUTS www.ti.com SCAS416P – MARCH 1994 – REVISED NOVEMBER 2005 DESCRIPTION/ORDERING INFORMATION (CONTINUED) The logic levels of the direction-control (DIR) input and the output-enable (OE) input activate either the B-port outputs or the A-port outputs or place both output ports into the high-impedance mode. The device transmits data from the A bus to the B bus when the B-port outputs are activated, and from the B bus to the A bus when the A-port outputs are activated. The input circuitry on both A and B ports always is active and must have a logic HIGH or LOW level applied to prevent excess ICC and ICCZ. TERMINAL ASSIGNMENTS (1) GQL OR ZQL PACKAGE (56-Ball GQL/ZQL Package) (TOP VIEW) 1 2 3 4 5 6 A B C D E F G H J K 1 2 3 4 5 6 A 1DIR NC NC NC NC 1OE B 1B2 1B1 GND GND 1A1 1A2 C 1B4 1B3 VCCB VCCA 1A3 1A4 D 1B6 1B5 GND GND 1A5 1A6 E 1B8 1B7 1A7 1A8 F 2B1 2B2 2A2 2A1 G 2B3 2B4 GND GND 2A4 2A3 H 2B5 2B6 VCCB VCCA 2A6 2A5 J 2B7 2B8 GND GND 2A8 2A7 K 2DIR NC NC NC NC 2OE abc (1) abc NC – No internal connection GRD OR ZRD PACKAGE (TOP VIEW) 1 2 3 4 5 6 TERMINAL ASSIGNMENTS (1) (54-Ball GRD/ZRD Package) 1 2 3 4 5 6 A 1B1 NC 1DIR 1OE NC 1A1 B 1B3 1B2 NC NC 1A2 1A3 C 1B5 1B4 VCCB VCCA 1A4 1A5 D 1B7 1B6 GND GND 1A6 1A7 D E 2B1 1B8 GND GND 1A8 2A1 E F 2B3 2B2 GND GND 2A2 2A3 G 2B5 2B4 VCCB VCCA 2A4 2A5 H 2B7 2B6 NC NC 2A6 2A7 J 2B8 NC 2DIR 2OE NC 2A8 A B C F G H (1) NC – No internal connection xxxxx J xxxxx xxxxx xxxxx FUNCTION TABLE (1) (EACH 8-BIT SECTION) CONTROL INPUTS (1) 2 OUTPUT CIRCUITS OPERATION OE DIR A PORT B PORT L L Enabled Hi-Z B data to A bus L H Hi-Z Enabled A data to B bus H X Hi-Z Hi-Z Isolation Input circuits of the data I/Os always are active. SN74ALVC164245 16-BIT 2.5-V TO 3.3-V/3.3-V TO 5-V LEVEL-SHIFTING TRANSCEIVER WITH 3-STATE OUTPUTS www.ti.com SCAS416P – MARCH 1994 – REVISED NOVEMBER 2005 LOGIC DIAGRAM (POSITIVE LOGIC) 1DIR 1 2DIR 48 1A1 25 1OE 47 2A1 2 24 2OE 36 13 1B1 2B1 To Seven Other Channels To Seven Other Channels Absolute Maximum Ratings (1) over operating free-air temperature range for VCCB at 5 V and VCCA at 3.3 V (unless otherwise noted) VCC VI Supply voltage range Input voltage range MIN MAX VCCA –0.5 4.6 VCCB –0.5 6 Except I/O ports (2) –0.5 6 I/O port A (3) –0.5 VCCA + 0.5 B (2) –0.5 VCCB + 0.5 I/O port UNIT V V IIK Input clamp current VI < 0 –50 mA IOK Output clamp current VO < 0 –50 mA IO Continuous output current ±50 mA ±100 mA Continuous current through each VCC or GND θJA Package thermal impedance (4) Tstg Storage temperature range DGG package 70 DL package 63 GQL/ZQL package 42 GRD/ZRD package (1) (2) (3) (4) °C/W 36 –65 150 °C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. This value is limited to 6 V maximum. This value is limited to 4.6 V maximum. The package thermal impedance is calculated in accordance with JESD 51-7. 3 SN74ALVC164245 16-BIT 2.5-V TO 3.3-V/3.3-V TO 5-V LEVEL-SHIFTING TRANSCEIVER WITH 3-STATE OUTPUTS www.ti.com SCAS416P – MARCH 1994 – REVISED NOVEMBER 2005 Recommended Operating Conditions (1) for VCCB at 3.3 V and 5 V MIN MAX VCCB Supply voltage 3 5.5 VIH High-level input voltage 2 VIL Low-level input voltage VIB Input voltage 0 VCCB VOB Output voltage 0 VCCB V IOH High-level output current –24 mA IOL Low-level output current 24 mA ∆t/∆v Input transition rise or fall rate 10 ns/V TA Operating free-air temperature 85 °C (1) V V VCCB = 3 V to 3.6 V 0.7 VCCB = 4.5 V to 5.5 V 0.8 –40 UNIT V V All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. Recommended Operating Conditions (1) for VCCA at 2.5 V and 3.3 V VCCA Supply voltage VCCA = 2.3 V to 2.7 V MIN MAX 2.3 3.6 UNIT V 1.7 VIH High-level input voltage VIL Low-level input voltage VIA Input voltage 0 VCCA V VOA Output voltage 0 VCCA V IOH High-level output current IOL Low-level output current ∆t/∆v Input transition rise or fall rate TA Operating free-air temperature (1) 4 VCCA = 3 V to 3.6 V V 2 VCCA = 2.3 V to 2.7 V 0.7 VCCA = 3 V to 3.6 V 0.8 VCCA = 2.3 V –18 VCCA = 3 V –24 VCCA = 2.3 V 18 VCCA = 3 V 24 –40 V mA mA 10 ns/V 85 °C All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. SN74ALVC164245 16-BIT 2.5-V TO 3.3-V/3.3-V TO 5-V LEVEL-SHIFTING TRANSCEIVER WITH 3-STATE OUTPUTS www.ti.com SCAS416P – MARCH 1994 – REVISED NOVEMBER 2005 Electrical Characteristics over recommended operating free-air temperature range for VCCA = 2.7 V to 3.6 V and VCCB = 4.5 V to 5.5 V (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = –100 µA B to A IOH = –12 mA IOH = –24 mA VOH VCCA VCCB 2.7 V to 3.6 V 2.7 V 2.2 3V 2.4 3V IOH = –24 mA A to B MAX 2 IOH = –100 µA B to A TYP (1) UNIT VCC – 0.2 A to B VOL MIN 4.5 V 4.3 5.5 V 5.3 4.5 V 3.7 5.5 V 4.7 V IOL = 100 µA 2.7 V to 3.6 V IOL = 12 mA 2.7 V 0.4 IOL = 24 mA 3V 0.55 0.2 IOL = 100 µA 4.5 V to 5.5 V 0.2 IOL = 24 mA 4.5 V to 5.5 V 0.55 V VI = VCCA/VCCB or GND 3.6 V 5.5 V ±5 µA IOZ (2) A or B port VO = VCCA/VCCB or GND 3.6 V 5.5 V ±10 µA ICC VI = VCCA/VCCB or GND, IO = 0 3.6 V 5.5 V 40 µA ∆ICC (3) One input at VCCA/VCCB – 0.6 V, Other inputs at VCCA/VCCB or GND 3 V to 3.6 V 4.5 V to 5.5 V 750 µA II Control inputs Ci Control inputs VI = VCCA/VCCB or GND 3.3 V 5V 6.5 pF Cio A or B port VO = VCCA/VCCB or GND 3.3 V 3.3 V 8.5 pF (1) (2) (3) Typical values are measured at VCCA = 3.3 V and VCCB = 5 V, TA = 25°C. For I/O ports, the parameter IOZ includes the input leakage current. This is the increase in supply current for each input that is at one of the specified TTL voltage levels, rather than at 0 or the associated VCC. Electrical Characteristics over recommended operating free-air temperature range for VCCA = 2.3 V to 2.7 V and VCCB = 3 V to 3.6 V (unless otherwise noted) PARAMETER TEST CONDITIONS VCCA VCCB 2.3 V to 2.7 V 3 V to 3.6 V VCCA – 0.2 IOH = –8 mA 2.3 V 3 V to 3.6 V 1.7 IOH = –12 mA 2.7 V 3 V to 3.6 V 1.8 IOH = –100 µA 2.3 V to 2.7 V 3 V to 3.6 V VCCB – 0.2 IOH = –18 mA 2.3 V to 2.7 V 3V IOL = 100 µA 2.3 V to 2.7 V 3 V to 3.6 V 0.2 IOL = 12 mA 2.3 V 3 V to 3.6 V 0.6 IOL = 100 µA 2.3 V to 2.7 V 3 V to 3.6 V 0.2 0.55 IOH = –100 µA B to A VOH A to B B to A VOL A to B MAX UNIT V 2.2 V 2.3 V 3V VI = VCCA/VCCB or GND 2.3 V to 2.7 V 3 V to 3.6 V ±5 µA IOZ (1) A or B port VO = VCCA/VCCB or GND 2.3 V to 2.7 V 3 V to 3.6 V ±10 µA ICC VI = VCCA/VCCB or GND, IO = 0 2.3 V to 2.7 V 3 V to 3.6 V 20 µA ∆ICC (2) One input at VCCA/VCCB – 0.6 V, Other inputs at VCCA/VCCB or GND 2.3 V to 2.7 V 3 V to 3.6 V 750 µA II (1) (2) Control inputs IOL = 18 mA MIN For I/O ports, the parameter IOZ includes the input leakage current. This is the increase in supply current for each input that is at one of the specified TTL voltage levels, rather than at 0 or the associated VCC. 5 SN74ALVC164245 16-BIT 2.5-V TO 3.3-V/3.3-V TO 5-V LEVEL-SHIFTING TRANSCEIVER WITH 3-STATE OUTPUTS www.ti.com SCAS416P – MARCH 1994 – REVISED NOVEMBER 2005 Switching Characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1 through Figure 4) VCCB = 3.3 V ± 0.3 V PARAMETER TO (OUTPUT) MAX MIN MAX A B 7.6 5.9 1 5.8 B A 7.6 6.7 1.2 5.8 VCCA = 2.5 V ± 0.2 V MIN tpd VCCB = 5 V ± 0.5 V FROM (INPUT) MAX VCCA = 3.3 V ± 0.3 V VCCA = 2.7 V MIN UNIT ns ten OE B 11.5 9.3 1 8.9 ns tdis OE B 10.5 9.2 2.1 9.5 ns ten OE A 12.3 10.2 2 9.1 ns tdis OE A 9.3 9 2.9 8.6 ns Operating Characteristics TA = 25°C PARAMETER TEST CONDITIONS Outputs enabled (B) Cpd Power dissipation capacitance Outputs disabled (B) Outputs enabled (A) Outputs disabled (A) 6 CL = 50 pF, f = 10 MHz CL = 50 pF, f = 10 MHz VCCB = 3.3 V VCCB = 5 V VCCA = 2.5 V VCCA = 3.3 V TYP TYP 55 56 27 6 118 56 58 6 UNIT pF www.ti.com SN74ALVC164245 16-BIT 2.5-V TO 3.3-V/3.3-V TO 5-V LEVEL-SHIFTING TRANSCEIVER WITH 3-STATE OUTPUTS SCAS416P – MARCH 1994 – REVISED NOVEMBER 2005 POWER-UP CONSIDERATIONS (1) TI level-translation devices offer an opportunity for successful mixed-voltage signal design. A proper power-up sequence always should be followed to avoid excessive supply current, bus contention, oscillations, or other anomalies caused by improperly biased device pins. Take these precautions to guard against such power-up problems: 1. Connect ground before any supply voltage is applied. 2. Power up the control side of the device (VCCA for all four of these devices). 3. Tie OE to VCCA with a pullup resistor so that it ramps with VCCA. 4. Depending on the direction of the data path, DIR can be high or low. If DIR high is needed (A data to B bus), ramp it with VCCA. Otherwise, keep DIR low. (1) Refer to the TI application report, Texas Instruments Voltage-Level-Translation Devices, literature number SCEA021. 7 SN74ALVC164245 16-BIT 2.5-V TO 3.3-V/3.3-V TO 5-V LEVEL-SHIFTING TRANSCEIVER WITH 3-STATE OUTPUTS www.ti.com SCAS416P – MARCH 1994 – REVISED NOVEMBER 2005 PARAMETER MEASUREMENT INFORMATION VCCA = 2.5 V ± 0.2 V to VCCB = 3.3 V ± 0.3 V VCCB = 6 V 500 Ω From Output Under Test S1 Open GND CL = 30 pF (see Note A) 500 Ω TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open VCCB = 6 V GND LOAD CIRCUIT VCCA Output Control (low-level enabling) VCCA/2 0V tPZL VCCA Input VCCA/2 VCCA/2 0V tPLH tPHL VOHB Output 1.5 V 1.5 V VOLB VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES tPLZ VCCB Output Waveform 1 S1 at 6 V (see Note B) Output Waveform 2 S1 at GND (see Note B) VCCA/2 1.5 V VOL + 0.3 V VOLB tPZH tPHZ 1.5 V VOH − 0.3 V VOHB 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR≤ 10 MHz, ZO = 50 Ω, tr≤ 2 ns, tf≤ 2 ns. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms 8 SN74ALVC164245 16-BIT 2.5-V TO 3.3-V/3.3-V TO 5-V LEVEL-SHIFTING TRANSCEIVER WITH 3-STATE OUTPUTS www.ti.com SCAS416P – MARCH 1994 – REVISED NOVEMBER 2005 PARAMETER MEASUREMENT INFORMATION VCCB = 3.3 V ± 0.3 V to VCCA = 2.5 V ± 0.2 V 2 × VCCA 500 Ω From Output Under Test S1 Open TEST tpd tPLZ/tPZL tPHZ/tPZH GND CL = 30 pF (see Note A) 500 Ω S1 Open 2 × VCCA GND LOAD CIRCUIT Output Control (low-level enabling) 2.7 V 1.5 V 0V tPZL 2.7 V Input 1.5 V 1.5 V 0V tPLH VCCA/2 VCCA/2 VOLA VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES tPLZ VCCA VCCA/2 tPZH VOHA Output Output Waveform 1 S1 at 2 × VCCA (see Note B) tPHL 1.5 V Output Waveform 2 S1 at GND (see Note B) VOL + 0.15 V VOLA tPHZ VCCA/2 VOHA VOH − 0.15 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 2. Load Circuit and Voltage Waveforms 9 SN74ALVC164245 16-BIT 2.5-V TO 3.3-V/3.3-V TO 5-V LEVEL-SHIFTING TRANSCEIVER WITH 3-STATE OUTPUTS www.ti.com SCAS416P – MARCH 1994 – REVISED NOVEMBER 2005 PARAMETER MEASUREMENT INFORMATION VCCA = 3.3 V ± 0.3 V to VCCB = 5 V ± 0.5 V S1 500 Ω From Output Under Test 2 VCCB TEST S1 Open tpd tPLZ/tPZL tPHZ/tPZH Open 2 VCCB GND GND CL = 50 pF (see Note A) 500 Ω 2.7 V Output Control (low-level enabling) LOAD CIRCUIT 1.5 V 0V tPZL 2.7 V Input 1.5 V 1.5 V 0V tPLH 50% VCCB VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES tPLZ ≈VCCB 50% VCCB 50% VCCB VOL 20% VCCB VOL tPZH VOH Output Output Waveform 1 S1 at 2 VCCB (see Note B) tPHL 1.5 V Output Waveform 2 S1 at GND (see Note B) tPHZ 50% VCCB 80% VCCB VOH 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 3. Load Circuit and Voltage Waveforms 10 SN74ALVC164245 16-BIT 2.5-V TO 3.3-V/3.3-V TO 5-V LEVEL-SHIFTING TRANSCEIVER WITH 3-STATE OUTPUTS www.ti.com SCAS416P – MARCH 1994 – REVISED NOVEMBER 2005 PARAMETER MEASUREMENT INFORMATION VCCB = 5 V ± 0.5 V to VCCA = 2.7 V and 3.3 V ± 0.3 V S1 500 Ω From Output Under Test VCCA = 6 V TEST S1 Open tpd tPLZ/tPZL tPHZ/tPZH Open VCCA = 6 V GND GND CL = 50 pF (see Note A) 500 Ω 3V Output Control (low-level enabling) LOAD CIRCUIT 1.5 V 0V tPZL 3V Input 1.5 V 1.5 V 0V tPLH 1.5 V 1.5 V VOLA VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES tPLZ ≈3 V 1.5 V VOL + 0.3 V VOLA tPZH VOHA Output Output Waveform 1 S1 at 6 V (see Note B) tPHL 1.5 V Output Waveform 2 S1 at GND (see Note B) tPHZ 1.5 V VOH − 0.3 V VOHA 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 4. Load Circuit and Voltage Waveforms 11 PACKAGE OPTION ADDENDUM www.ti.com 6-Dec-2006 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing 74ALVC164245DGGRE4 ACTIVE TSSOP DGG 48 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 74ALVC164245DGGRG4 ACTIVE TSSOP DGG 48 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 74ALVC164245DGGTE4 ACTIVE TSSOP DGG 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 74ALVC164245DLG4 ACTIVE SSOP DL 48 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 74ALVC164245DLRG4 ACTIVE SSOP DL 48 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 74ALVC164245GRDR ACTIVE BGA MI CROSTA R JUNI OR GRD 54 1000 SNPB Level-1-240C-UNLIM 74ALVC164245ZQLR ACTIVE BGA MI CROSTA R JUNI OR ZQL 56 1000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM 74ALVC164245ZRDR ACTIVE BGA MI CROSTA R JUNI OR ZRD 54 1000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM SN74ALVC164245DGGR ACTIVE TSSOP DGG 48 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ALVC164245DGGT ACTIVE TSSOP DGG 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ALVC164245DL ACTIVE SSOP DL 48 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ALVC164245DLR ACTIVE SSOP DL 48 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ALVC164245KR ACTIVE GQL 56 1000 SNPB Level-1-240C-UNLIM BGA MI CROSTA R JUNI OR Pins Package Eco Plan (2) Qty TBD TBD Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 6-Dec-2006 (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 2 MECHANICAL DATA MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001 DL (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0.025 (0,635) 0.0135 (0,343) 0.008 (0,203) 48 0.005 (0,13) M 25 0.010 (0,25) 0.005 (0,13) 0.299 (7,59) 0.291 (7,39) 0.420 (10,67) 0.395 (10,03) Gage Plane 0.010 (0,25) 1 0°–ā8° 24 0.040 (1,02) A 0.020 (0,51) Seating Plane 0.110 (2,79) MAX 0.004 (0,10) 0.008 (0,20) MIN PINS ** 28 48 56 A MAX 0.380 (9,65) 0.630 (16,00) 0.730 (18,54) A MIN 0.370 (9,40) 0.620 (15,75) 0.720 (18,29) DIM 4040048 / E 12/01 NOTES: A. B. C. D. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15). Falls within JEDEC MO-118 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MTSS003D – JANUARY 1995 – REVISED JANUARY 1998 DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0,27 0,17 0,50 48 0,08 M 25 6,20 6,00 8,30 7,90 0,15 NOM Gage Plane 1 0,25 24 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 48 56 64 A MAX 12,60 14,10 17,10 A MIN 12,40 13,90 16,90 DIM 4040078 / F 12/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold protrusion not to exceed 0,15. Falls within JEDEC MO-153 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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