SLES149 − OCTOBER 2005
D VCO (Voltage-Controlled Oscillator):
D
D
D
D
− Complete Oscillator Using Only One
External Bias Resistor (RBIAS)
− Lock Frequency:
30 MHz to 55 MHz (VDD = 3 V +5%,
TA = –205C to 755C, x1 Output)
30 MHz to 60 MHz (VDD = 3.3 V +5%,
TA = –205C to 755C, x1 Output)
43 MHz to 110 MHz (VDD = 5 V +5%,
TA = –205C to 755C, x1 Output)
− Selectable Output Frequency
D PFD (Phase Frequency Detector):
High Speed, Edge-Triggered Detector
with Internal Charge Pump
Independent VCO, PFD Power-Down Mode
Thin Small-Outline Package (14 Terminal)
CMOS Technology
Pin Compatible TLC2933IPW
14-PIN TSOP (PW PACKAGE)
(TOP VIEW)
LOGIC VDD
SELECT
VCO OUT
FIN −A
FIN −B
PFD OUT
LOGIC GND
1
2
3
4
5
6
7
14
13
12
11
10
9
8
VCO VDD
RBIAS
VCO IN
VCO GND
VCO INHIBIT
PFD INHIBIT
TEST
description
The TLC2933A is designed for phase-locked loop (PLL) systems and is composed of a voltage-controlled
oscillator (VCO) and an edge-triggered type phase frequency detector (PFD). The oscillation frequency range
of the VCO is set by an external bias resistor (RBIAS). The VCO has a 1/2 frequency divider at the output stage.
The high speed PFD with internal charge pump detects the phase difference between the reference frequency
input and signal frequency input from the external counter. Both the VCO and the PFD have inhibit functions,
which can be used as power-down mode. Due to the TLC2933A high speed and stable oscillation capability,
the TLC2933A is suitable for use as a high-performance PLL.
AVAILABLE OPTIONS
PACKAGE
TA
SMALL OUTLINE (PW)
–20°C to 75°C
TLC2933AIPW
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2005, Texas Instruments Incorporated
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TI.COM
1
SLES149 − OCTOBER 2005
functional block diagram
FIN−A
FIN−B
PFD INHIBIT
VCO IN
4
Phase
Frequency
Detector
5
9
6
BIAS
PFD OUT
VCO INHIBIT
SELECT
12
13
10
Voltage
Controlled
Oscillator
3
VCO OUT
2
Terminal Functions
TERMINAL
2
I/O
DESCRIPTION
NAME
NO.
LOGIC VDD
1
SELECT
2
I
VCO output frequency select. When SELECT is high, the VCO output frequency is ×1/2 and when
low. The output frequency is ×1.
VCO OUT
3
O
VCO output. When the VCO INHIBIT is high, VCO output is low.
FIN−A
4
I
Input reference frequency f(REF IN) is applied to FIN−A.
FIN−B
5
I
Input for VCO external counter output frequency f(FIN−B). FIN−B is nominally provided from the
external counter.
PFD OUT
6
O
PFD output. When the PFD INHIBIT is high, PFD output is in the high-impedance state.
LOGIC GND
7
TEST
8
PFD INHIBIT
9
I
PFD inhibit control. When PFD INHIBIT is high, PFD output is in the high-impedance state.
VCO INHIBIT
10
I
VCO inhibit control. When VCO INHIBIT is high, VCO output is low.
Power supply for the internal logic. This power supply should be separated from VCO VDD to reduce
cross-coupling between supplies.
GND for the internal logic.
Connect to GND.
VCO GND
11
VCO IN
12
I
GND for VCO.
VCO control voltage input. Nominally the external loop filter output connects to VCO IN to control
VCO oscillation frequency.
RBIAS
13
I
Bias supply. An external resistor (RBIAS) between VCO VDD and RBIAS supplies bias for adjusting the
oscillation frequency range.
VCO VDD
14
Power supply for VCO. This power supply should be separated from LOGIC VDD to reduce
cross-coupling between supplies.
TI.COM
SLES149 − OCTOBER 2005
detailed description
VCO oscillation frequency
The VCO oscillation frequency is determined by an external register (RBIAS) connected between the VCO VDD
and the BIAS terminals. The oscillation frequency and range depends on this Resistor value. For the lock
frequency range, refer to the recommended operating conditions. Figure 1 shows the typical frequency
variation and VCO control voltage.
VCO Oscillation Frequency − fOSC
VCO Oscillation Frequency Range
Bias Resistor (RBIAS)
1/2 VDD
VCO Control Voltage (VCO IN)
Figure 1. Oscillation Frequency
VCO output frequency 1/2 divider
The TLC2933A SELECT terminal sets the fOSC VCO output frequency as shown in Table 1. The 1/2 fOSC output
should be used for minimum VCO output jitter.
Table 1. VCO Output 1/2 Divider Function
SELLECT
VCO OUTPUT
Low
fOSC
1/2 fOSC
High
VCO inhibit function
The VCO has an externally controlled inhibit function which inhibit the VCO output. A high level on the VCO
INHIBIT terminal stops the VCO oscillation and powers down the VCO. The output maintains a low level during
the power−down mode as shown in Table 2.
Table 2. VCO Inhibit Function
VCO INHIBIT
VCO OSCILLATOR
VCO OUT
Low
Active
Active
IDD(VCO)
Normal
High
Stopped
Low level
Power Down
PFD operation
The PFD is a high-speed, edge-triggered detector with an internal charge pump. The PFD detects the phase
difference between two frequency inputs supplied to FIN−A and FIN−B as shown in Figure 2. Normally the
reference is supplied to FIN−A and the frequency from the external counter output is fed to FIN−B. For clock
recovery PLL system, other types of phase detectors should be used.
TI.COM
3
SLES149 − OCTOBER 2005
FIN−A
FIN−B
VOH
PFD OUT
HI-Z
VOL
Figure 2. PFD Function Timing Chart
PFD inhibit control
A high level on the PFD INHIBIT terminal places PFD OUT in the high-impedance state and the PFD stops
phase detection as shown in Table 3. A high level on the PFD INHIBIT terminal can also be used as the
power-down mode for the PFD.
Table 3. VCO Output Control Function
PFD INHIBIT
DETECTION
PFD OUT
Low
Active
Active
IDD(PFD)
Normal
High
Stopped
Hi−Z
Power Down
VCO block schematic
PFD block schematic
Charge Pump
VDD
FIN−A
PFD OUT
Detector
FIN−B
PFD INHIBIT
4
TI.COM
SLES149 − OCTOBER 2005
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage (each supply), VDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Input voltage range (each input), VIN (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VDD + 0.5 V
Input current (each input), IIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output current (each output), IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –20°C to 75°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltages are with respect to GND.
2. For operation above 25_C free-air temperature, derate linearly at the rate of 5.6 mW/°C.
recommended operating conditions
PARAMETERS
VDD = 3 V
Supply voltage (each supply, see Note 3)
VDD = 3.3 V
VDD = 5 V
Input voltage, (inputs except VCO IN)
Output current, (each output)
VCO control voltage at VCO IN
Lock frequency
MIN
2.85
TYP
3
MAX
3.15
UNIT
3.135
3.3
3.465
V
4.75
5
5.25
0
0
0.9
30
VDD = 3 V
VDD = 3.3 V
VDD = 5 V
VDD = 3 V
VDD
±2
VDD
55
V
mA
V
30
60
MHz
43
110
2.2
5.1
VDD = 3.3 V
2.2
5.1
kΩ
VDD = 5 V
2.2
5.1
NOTE 3: It is recommended that the logic supply terminal (LOGIC VDD) and the VCO supply terminal (VCO VDD) should be at the same voltage
and separated from each other.
Bias resisitor
electrical characteristics, VDD = 3 V, TA = 25°C (unless otherwise noted)
VCO section
PARAMETER
TEST CONDITIONS
VOH
VOL
High level output voltage
VTH
II
Input threshold voltage at select, VCO inhibit
ZI(VCOIN)
IDD(INH)
VCO IN input impedance
VI = VDD or GND
VCO IN = 1/2 VDD
VCO supply current (inhibit)
See Note 4
Low level output voltage
Input current at Select, VCO inhibit
IOH = –2 mA
IOL = 2 mA
MIN
TYP
MAX
2.4
V
0.3
0.9
1.5
V
±1
µA
10
0.41
V
2.1
MΩ
1
IDD(VCO) VCO supply current
See Note 5
11.7
23
NOTES: 4. Current into VCO VDD, when VCO INHIBIT = high, PFD is inhibited.
5. Current into VCO VDD, when VCO IN = 1/2 VDD, RBIAS = 3.3 kΩ, VCOOUT = 15-pF Load, VCO INHIBIT = GND, and
PFD INHIBIT = GND.
TI.COM
UNIT
µA
mA
5
SLES149 − OCTOBER 2005
electrical characteristics, VDD = 3 V, TA = 25°C (unless otherwise noted) (continued)
PFD section
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VOH
VOL
High level output voltage
Low level output voltage
IOH = –2 mA
IOL = 2 mA
2.4
IOZ
VIH
High impedance state output current
PFD inhibit = high, VO = VDD or GND
VIL
VTH
Low level input voltage at Fin−A, Fin−B
CIN
Input capacitance at Fin−A, Fin−B
5.6
pF
ZIN
IDD(Z)
Input impedance at Fin−A, Fin−B
10
MΩ
High level input voltage at Fin−A, Fin−B
V
±1
µA
2.1
V
0.5
Input threshold voltage at PFD inhibit
High impedance state PFD supply current
V
0.3
0.9
1.5
V
2.1
See Note 6
µA
1
IDD(PFD) PFD supply current
See Note 7
3
mA
NOTES: 6. The current into LOGIC VDD when FIN−A and FIN−B = ground, PFD INHIBIT = VDD, PFD OUT open, and VCO OUT is inhibited.
7. The current into LOGIC VDD when FIN−A = 1 MHz and FIN−B = 1 MHz (VI(PP) = 3 V, rectangular wave), PFD INHIBIT = GND, PFD
OUT open, and VCO OUT is inhibited.
operation characteristics, VDD = 3 V, TA = 25°C (unless otherwise noted)
VCO section
Parameter
TEST CONDITIONS
fOSC
fSTB
Operation oscillation frequency
RBIAS = 3.3 kΩ, VCO IN = 1/2 VDD
tr
tf
Rise time
CL = 15 pF
Fall time
CL = 15 pF
MIN
TYP
MAX
UNIT
32
47
63
MHz
10
µs
8.6
14
ns
7.1
12
ns
50%
55%
Time to stable oscillation (see Note 8)
Duty cycle at VCO OUT
RBIAS = 3.3 kΩ, VCO IN = 1/2 VDD
α (fOSC)
Temperature coefficient of oscillation
frequency
VCO IN = 1/2 VDD,
TA = –20°C to 75°C
45%
–0.21
%/°C
kSVS
(fosc)
Supply voltage coefficient of oscillation
frequency
VCO IN = 1/2 VDD,
VDD = 4.75 V to 5.25 V
0.002
%/mV
Jitter absolute (see Note 9)
PLL jitter, N = 128
262
ps
NOTES: 8. The time period to the stable VCO oscillation frequency after the VCO INHIBIT terminal is changed to a low level.
9. Jitter performance is highly dependent on circuit layout and external device characteristics. The jitter specification was made with
a carefully deigned PCB with no device socket.
PFD section
PARAMETER
6
TEST CONDITIONS
MIN
TYP
MAX
32
UNIT
fmax
tPLZ
Maximum operation frequency
PFD output disable time from low level
22
50
ns
tPHZ
tPZL
PFD output disable time from high level
21
50
ns
PFD output enable time to low level
6.5
30
ns
tPZH
tr
PFD output enable time to high level
7
30
ns
Rise time
CL = 15 pF
3.4
10
ns
tf
Fall time
CL = 15 pF
1.9
10
ns
TI.COM
MH
SLES149 − OCTOBER 2005
electrical characteristics, VDD = 3.3 V, TA = 25°C (unless otherwise noted)
VCO section
PARAMETER
TEST CONDITIONS
VOH
VOL
High level output voltage
VTH
II
Input threshold voltage at select, VCO inhibit
ZI(VCOIN)
IDD(INH)
VCO IN input impedance
VI = VDD or GND
VCO IN = 1/2 VDD
VCO supply current (inhibit)
See Note 10
Low level output voltage
Input current at Select, VCO inhibit
IOH = –2 mA
IOL = 2 mA
MIN
TYP
MAX
UNIT
2.64
V
0.33
1.05
1.65
V
2.25
V
±1
µA
10
MΩ
0.44
µA
1
IDD(VCO) VCO supply current
See Note 11
14.7
28
mA
NOTES: 10. Current into VCO VDD, when VCO INHIBIT = high, PFD is inhibited.
11. Current into VCO VDD, when VCO IN = 1/2 VDD, RBIAS = 3.3 kΩ, VCOOUT = 15-pF Load, VCO INHIBIT = GND, and
PFD INHIBIT = GND.
PFD section
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
VOH
VOL
High level output voltage
Low level output voltage
IOH = –2 mA
IOL = 2 mA
IOZ
VIH
High impedance state output current
PFD inhibit = high, VO = VDD or GND
VIL
VTH
Low level input voltage at Fin−A, Fin−B
CIN
Input capacitance at Fin−A, Fin−B
5.6
pF
ZIN
IDD(Z)
Input impedance at Fin−A, Fin−B
10
MΩ
High level input voltage at Fin−A, Fin−B
V
0.2
V
±1
µA
2.1
V
0.5
Input threshold voltage at PFD inhibit
High impedance state PFD supply current
2.97
UNIT
1.05
1.65
See Note 12
V
2.25
1
µA
IDD(PFD) PFD supply current
See Note 13
3
mA
NOTES: 12. The current into LOGIC VDD when FIN−A and FIN−B = ground, PFD INHIBIT = VDD, PFD OUT open, and VCO OUT is inhibited.
13. The current into LOGIC VDD when FIN−A = 1 MHz and FIN−B = 1 MHz (VI(PP) = 3.3 V, rectangular wave), PFD INHIBIT = GND,
PFD OUT open, and VCO OUT is inhibited.
operation characteristics, VDD = 3.3 V, TA = 25°C (unless otherwise noted)
VCO section
PARAMETER
TEST CONDITIONS
RBIAS = 3.3 kΩ, VCO IN = 1/2 VDD
MIN
TYP
MAX
UNIT
35
55
80
MHz
10
µs
14
ns
6.7
12
ns
50%
55%
fOSC
fstb
Operation oscillation frequency
tr
Rise time
CL = 15 pF
8.3
tf
fDUTY
Fall time
CL = 15 pF
Duty cycle at VCO OUT
RBIAS = 3.3 kΩ, VCO IN = 1/2 VDD
α (fOSC)
Temperature coefficient of oscillation
frequency
VCO IN = 1/2 VDD, TA = –20°C to 75°C
kSVS(fOSC)
Supply voltage coefficient of oscillation
frequency
VCO IN = 1/2 VDD, VDD = 4.75 V to 5.25 V
Time to stable oscillation (see Note 14)
45%
–0.232
%/°C
0.002
%/m
V
Jitter absolute (see Note 15)
PLL jitter, N = 128
211
ps
NOTES: 14. The time period to the stable VCO oscillation frequency after the VCO INHIBIT terminal is changed to a low level.
15. Jitter performance is highly dependent on circuit layout and external device characteristics. The jitter specification was made with
a carefully deigned PCB with no device socket.
TI.COM
7
SLES149 − OCTOBER 2005
operation characteristics, VDD = 3.3 V, TA = 25°C (unless otherwise noted) (continued)
PFD section
PARAMETER
TEST CONDITIONS
TYP
MAX
21
50
ns
PFD output disable time from high level
21
50
ns
PFD output enable time to low level
5.8
30
ns
6.2
30
ns
3
10
ns
1.7
10
ns
fmax
tPLZ
Maximum operation frequency
tPHZ
tPZL
tPZH
tr
PFD output enable time to high level
Rise time
CL = 15 pF
tf
Fall time
CL = 15 pF
MIN
40
PFD output disable time from low level
UNIT
MHz
electrical characteristics, VDD = 5 V, TA = 25°C (unless otherwise noted)
VCO section
PARAMETER
TEST CONDITIONS
VOH
VOL
High level output voltage
VTH
Input threshold voltage at select, VCO
inhibit
II
ZI(VCOIN)
Input current at select, VCO inhibit
VCO IN input impedance
VI = VDD or GND
VCO IN = 1/2 VDD
IDD(inh)
VCO supply current (inhibit)
See Note 16
Low level output voltage
IOH = –2 mA
IOL = 2 mA
MIN
TYP
MAX
4
1.5
UNIT
V
2.5
0.5
V
3.5
V
±1
µA
1
µA
10
0.61
M(
IDD(vco)
VCO supply current
See Note 17
35.5
55
mA
NOTES: 16. Current into VCO VDD, when VCO INHIBIT = high, PFD is inhibited.
17. Current into VCO VDD, when VCO IN = 1/2 VDD, RBIAS = 3.3 kΩ, VCOOUT = 15-pF Load, VCO INHIBIT = GND, and
PFD INHIBIT = GND.
PFD section
PARAMETER
TEST CONDITIONS
VOH
VOL
High level output voltage
IOH = –2 mA
IOL = 2 mA
IOZ
High impedance state output current
VIH
VIL
High level input voltage at Fin−A, Fin−B
VTH
CIN
Input threshold voltage at PFD inhibit
Input capacitance at Fin−A, Fin−B
5.6
pF
ZIN
IDD(Z)
Input impedance at Fin−A, Fin−B
10
MΩ
Low level output voltage
MIN
TYP
PFD inhibit = high, Vo = VDD or
GND
0.2
V
±1
µA
4.5
V
1
1.5
See Note 18
UNIT
V
Low level input voltage at Fin−A, Fin−B
High impedance state PFD supply current
MAX
4.5
2.5
V
3.5
1
µA
IDD(PFD) PFD supply current
See Note 19
0.48
3
mA
NOTES: 18. The current into LOGIC VDD when FIN−A and FIN−B = ground, PFD INHIBIT = VDD, PFD OUT open, and VCO OUT is inhibited.
19. The current into LOGIC VDD when FIN−A = 1 MHz and FIN−B = 1 MHz (VI(PP) = 5 V, rectangular wave), PFD INHIBIT = GND, PFD
OUT open, and VCO OUT is inhibited
8
TI.COM
SLES149 − OCTOBER 2005
operation characteristics, VDD = 5 V, TA = 25°C (unless otherwise noted)
VCO section
PARAMETER
TEST CONDITIONS
RBIAS = 3.3 kΩ, VCO IN = 1/2 VDD
MIN
TYP
MAX
UNIT
70
99
130
MHz
10
us
10
ns
5
10
ns
50%
55%
fOSC
fSTB
Operation oscillation frequency
tr
tf
Rise time
CL = 15 pF
Fall time
CL = 15 pF
fDUTY
α (fOSC)
Duty cycle at VCO OUT
RBIAS = 3.3 kΩ, VCO IN = 1/2 VDD
Temperature coefficient of oscillation
frequency
VCO IN = 1/2 VDD, TA = –20°C to
75°C
–0.309
%/°C
kSVS(fOS
C)
Supply voltage coefficient of oscillation
frequency
VCO IN = 1/2 VDD, VDD = 4.75 V
to 5.25 V
0.001
%/mV
Time to stable oscillation (see Note 20)
5.4
45%
Jitter absolute (see Note 21)
PLL jitter, N = 128
140
ps
NOTES: 20. The time period to the stable VCO oscillation frequency after the VCO INHIBIT terminal is changed to a low level.
21. Jitter performance is highly dependent on circuit layout and external device characteristics. The jitter specification was made with
a carefully deigned PCB with no device socket.
PFD section
PARAMETER
TYP
MAX
PFD output disable time from low level
20
40
ns
tPHZ
tPZL
PFD output disable time from high level
20
40
ns
4
20
ns
tPZH
tr
PFD output enable time to high level
4.3
20
ns
Rise time
CL = 15 pF
2.1
10
ns
tf
Fall time
CL = 15 pF
1.3
10
ns
fmax
tPLZ
Maximum operation frequency
TEST CONDITIONS
MIN
65
PFD output enable time to low level
TI.COM
UNIT
MHz
9
SLES149 − OCTOBER 2005
PARAMETER MEASUREMENT INFORMATION
90%
VCO OUT
90%
10%
10%
tr
tf
Figure 3. VCO Output Voltage Waveform
FIN−A
VDD
50%
GND
FIN−B
VDD
50%
GND
VDD
PFD INHIBIT
50%
50%
GND
VDD
90%
PFD OUT
90%
50%
GND
50%
50%
50%
10%
10%
tPZH
tPHZ
tPZL
tr
tPLZ
tf
Figure 4. PFD Output Voltage Waveform
Table 4. PFD Output Test Conditions
PARAMETER
RL
CL
1 kΩ
15 pF
tPZH
tPHZ
tr
tPZL
tPLZ
tf
10
TI.COM
S1
S2
OPEN
CLOSE
CLOSE
OPEN
SLES149 − OCTOBER 2005
PARAMETER MEASUREMENT INFORMATION
Measurement
Point
S1
DUT
RL
CL
S2
Figure 5. PFD Output Test Conditions
TYPICAL CHARACTERISTICS
VCO OSCILATION FREQUENCY
VS
VCO CONTROL VOLTAGE
Vdd=3.0V Rbias=3.3kohm
VCO OSCILATION FREQUENCY
VS
VCO CONTROL VOLTAGE
Vdd=3.0V Rbias=2.2kohm
140
140
−25°C
fosc − VCO Oscilation Frequency NHz
fosc − VCO Oscilation Frequency NHz
−25°C
120
120
25°C
100
85°C
80
60
40
20
25°C
100
85°C
80
60
40
20
0
0
0
1
2
3
0
4
1
2
3
4
VCOIN − VCO Control Voltage − V
VCOIN − VCO Control Voltage − V
Figure 7.
Figure 6.
TI.COM
11
SLES149 − OCTOBER 2005
TYPICAL CHARACTERISTICS
VCO OSCILATION FREQUENCY
VS
VCO CONTROL VOLTAGE
Vdd=3.3V Rbias=2.2kohm
VCO OSCILATION FREQUENCY
VS
VCO CONTROL VOLTAGE
Vdd=3.0V Rbias=5.1kohm
160
140
fosc − VCO Oscilation Frequency NHz
fosc − VCO Oscilation Frequency NHz
−25°C
140
120
−25°C
100
25°C
85°C
80
60
40
20
25°C
120
85°C
100
80
60
40
20
0
0
0
1
2
3
0
4
1
4
VCO OSCILATION FREQUENCY
VS
VCO CONTROL VOLTAGE
Vdd=3.3V Rbias=5.1kohm
VCO OSCILATION FREQUENCY
VS
VCO CONTROL VOLTAGE
Vdd=3.3V Rbias=3.3kohm
160
160
140
140
−25°C
fosc − VCO Oscilation Frequency NHz
fosc − VCO Oscilation Frequency NHz
3
Figure 9.
Figure 8.
120
25°C
100
85°C
80
60
40
120
−25°C
100
25°C
85°C
80
60
40
20
20
0
0
0
1
2
3
0
4
1
2
VCOIN − VCO Control Voltage − V
VCOIN − VCO Control Voltage − V
Figure 11.
Figure 10.
12
2
VCOIN − VCO Control Voltage − V
VCOIN − VCO Control Voltage − V
TI.COM
3
4
SLES149 − OCTOBER 2005
TYPICAL CHARACTERISTICS
VCO OSCILATION FREQUENCY
VS
VCO CONTROL VOLTAGE
Vdd=5.0V Rbias=3.3kohm
VCO OSCILATION FREQUENCY
VS
VCO CONTROL VOLTAGE
Vdd=5.0V Rbias=2.2kohm
200
200
−25°C
180
25°C
−25°C
160
fosc − VCO Oscilation Frequency NHz
fosc − VCO Oscilation Frequency NHz
180
85°C
140
120
100
80
60
40
160
25°C
140
85°C
120
100
80
60
40
20
20
0
0
0
1
2
3
4
5
0
6
1
3
4
5
6
Figure 13.
Figure 12.
VCO OSCILATION FREQUENCY
VS
VCO CONTROL VOLTAGE
Vdd=5.0V Rbias=5.1kohm
VCO Oscilation frequency
Vs
Bias resister
Vdd=3V, VCOIN=1.5V, Ta=25’C
200
180
55
VCO Oscilationfrequency MHz
fosc − VCO Oscilation Frequency NHz
2
VCOIN − VCO Control Voltage − V
VCOIN − VCO Control Voltage − V
160
−25°C
140
25°C
120
85°C
100
80
60
40
20
0
0
1
2
3
4
5
53
51
49
47
45
43
41
39
37
35
1
6
VCOIN − VCO Control Voltage − V
2
3
4
5
6
Rbias(kohm)
Figure 15.
Figure 14.
TI.COM
13
SLES149 − OCTOBER 2005
TYPICAL CHARACTERISTICS
VCO Oscilation Frequency
VCO Oscilation Frequency
Vs
Bias resistor
Bias resistor
Vs
Vdd=5V, VCOIN=2.5V, Ta=25’C
Vdd=3.3V, VCOIN=1.6V, Ta=25’C
105
VCO Oscilationfrequency MHz
VCO Oscilationfrequency MHz
65
63
61
59
57
55
53
51
49
47
45
1
2
3
4
5
103
101
99
97
95
93
91
89
87
85
1
6
2
3
Temperature Coefficient of Oscilation frequency %/’C
Temperature Coefficient of Oscilationfrequency %/’C
Temperature Coefficient Oscilation Frequency
Vs
Bias resistor
Vdd=3V, VCOIN=1.5V, Ta=−20’C to 75’C
0
−0.05
−0.1
−0.15
−0.2
−0.25
−0.3
−0.35
−0.4
−0.45
−0.5
3
4
Rbias(kohm)
5
6
Temperature Coefficient Oscilation Frequency
Vs
Bias resistor
Vdd=3.3V, VCOIN=1.6V, Ta=−20’C to 75’C
0
−0.05
−0.1
−0.15
−0.2
−0.25
−0.3
−0.35
−0.4
−0.45
−0.5
1
2
3
4
Rbias(kohm)
Figure 19.
Figure 18.
14
6
Figure 17.
Figure 16.
2
5
Rbias(kohm)
Rbias(kohm)
1
4
TI.COM
5
6
SLES149 − OCTOBER 2005
Temperature Coefficient Oscilation Frequency
Vs
Bias resistor
Vdd=5.0V, VCOIN=2.5V, Ta=−20’C to 75’C
VCO Oscilation frequency
Vs
VCO Supply Voltage
VCOIN=1.5V, Ta=25’C
0
55
−0.05
53
VCO Oscilation frequency MHz
Temperature Coefficient of Oscilation frequency %/’C
TYPICAL CHARACTERISTICS
−0.1
−0.15
−0.
−0.2
−0.25
−0.3
−0.35
−0.4
−0.45
−0.5
1
2
3
4
Rbias(kohm)
5
51
49
47
45
43
41
39
37
35
6
2.5
105
63
103
VCO Oscilation frequency MHz
VCO Oscilation frequency MHz
65
61
59
57
55
53
51
49
47
101
99
97
95
93
91
89
87
85
3.2
3.4
3.5
VCO Oscilation frequency
Vs
VCO Supply Voltage
VCOIN=2.5V, Ta=25’C
VCO Oscilation frequency
Vs
VCO Supply Voltage
VCOIN=1.6V, Ta=25’C
3
2.9
3.1
3.3
VCO Supply Voltage (V)
Figure 21.
Figure 20.
45
2.8
2.7
3.6
3.8
VCO Supply Voltage (V)
4
4.5
5.5
5
VCO Supply Voltage (V)
6
Figure 23.
Figure 22.
TI.COM
15
SLES149 − OCTOBER 2005
Supply Voltage Coefficient of Oscilation frequency
Vs
Bias resistor
Vdd=2.7V to 3.3V,VCOIN=1.5V, Ta=25’C
0.1
0.08
0.06
0.04
0.02
0
−0.02
−0.04
−0.06
−0.08
−0.1
1
2
3
4
5
6
Rbias (kohm)
Supply Voltage Coefficient of Oscilation frequency %/mV
Supply Voltage Coefficient of Oscilation frequency %/mV
TYPICAL CHARACTERISTICS
Supply Voltage Coefficient of Oscilation frequency
Vs
Bias resistor
Vdd=3.0V to 3.6V,VCOIN=1.6V, Ta=25’C
0.1
0.08
0.06
0.04
0.02
0
−0.02
−0.04
−0.06
−0.08
−0.1 1
2
0.1
0.08
0.06
0.04
0.02
0
−0.02
−0.04
−0.06
−0.08
2
3
4
Rbias (kohm)
5
6
6
Recommended Lock frequency
Vs
Bias resistor
Vdd=2.85V to 3.15V, Ta=−20’C to 75’C
120
100
80
60
40
20
0 1
2
3
4
Rbias (kohm)
Figure 27.
Figure 26.
16
RECOMMENDED LOCK FREQUENCY MHz
Supply Voltage Coefficient of Oscilation frequency %/mV
Supply Voltage Coefficient of Oscilation frequency
Vs
Bias resistor
Vdd=4.5V to 5.5V,VCOIN=2.5V, Ta=25’C
1
5
Figure 25.
Figure 24.
−0.1
3
4
Rbias (kohm)
TI.COM
5
6
SLES149 − OCTOBER 2005
Recommended Lock frequency
Vs
Bias resistor
Vdd=3.135V to 3.465V, Ta=−20’C to 75’C
RECOMMENDED LOCK FREQUENCY MHz
RECOMMENDED LOCK FREQUENCY MHz
TYPICAL CHARACTERISTICS
120
100
80
60
40
20
0
1
2
3
4
Rbias (kohm)
5
6
Recommended Lock frequency
Vs
Bias resistor
Vdd=4.75V to 5.25V, Ta=−20’C to 75’C
120
100
80
60
40
20
0
1
2
3
4
5
6
Rbias (kohm)
Figure 29.
Figure 28.
TI.COM
17
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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