ETC SA4871

SA4871
3W Mono Low-Voltage Audio Power Amplifier
Features
• Operating Voltage : 2.5V-5.5V
• Bridge-Tied Load (BTL) Mode Operation
• Supply Current – IDD=7mA at VDD=5V
• Low Shutdown Current – IDD=0.1µA
• Low Distortion
•
•
•
•
•
•
General Description
The SA4871 is a bridged-tied load (BTL) audio power
amplifier developed especially for low-voltage
applications where internal speakers. Operating with
a 5V supply,
the SA4871 can deliver 3.3W of
continuous power into a BTL 3Ω load at 10% THD+N
–2.5W, at VDD=5V, BTL, RL=3Ω
THD+N=0.1%
–2.1W, at VDD=5V, BTL, RL=4Ω
THD+N=0.1%
Output Power
at 1% THD+N
–2.6W, at VDD=5V, BTL, RL=3Ω
–2.3W, at VDD=5V, BTL, RL=4Ω
at 10% THD+N
–3.3W at VDD=5V, BTL, RL=3Ω
–2.7W at VDD=5V, BTL, RL=4Ω
Depop Circuitry Integrated
Thermal shutdown protection and over current
protection circuitry
High supply voltage ripple rejection
Surface-Mount Packaging
–MSOP-8-P (with enhanced thermal pad)
–SOP-8-P (with enhanced thermal pad)
Lead Free Available (RoHS Compliant)
throughout voice band frequencies. Although this
device is characterized out to 20kHz, its operation is
optimized for narrow band applications such as
wireless communications. The BTL configuration
eliminates the need for external coupling capacitors
on the output in most applications, which is particularly
important for small battery-powered equipment. This
device features a shutdown mode for power sensitive
applications with special depop circuitry to eliminate
speaker noise when exiting shutdown mode. The
SA4871 is available in a SOP-8-P or MSOP-8-P.
Applications
• Mobil Phones
• PDAs
• Portable Electronic Devices
• Desktop Computers
Ordering and Marking Information
SA4871
Lead Free Code
H a n d lin g C o d e
Tem p. Range
Package Code
Package Code
K A : S O P -8-P
X A : M S O P -8-P
O p e r a t i n g A m b ie n t T e m p . R a n g e
I : - 4 0 t o 8 5 °C
H a n d lin g C o d e
TR : Tape & Reel
Lead Free Code
L : L e a d F r e e D e v ic e B la n k : O r i g in a l D e v ic e
SA4871 KA :
SA4871
XXXXX
X X X X X - D a te C o d e
SA4871 XA :
SA4871
XXX
XX
X X X X X - D a te C o d e
Note: SUPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate
termination finish; which are fully compliant with RoHS and compatible with both SnPb and lead-free soldiering
operations. SUPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J STD-020C
for MSL classification at lead-free peak reflow temperature.
SUPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise
customers to obtain the latest version of relevant information to verify before placing orders.
Copyright © SUPEC Electronics Corp.
Rev. A.1 - Nov., 2006
1
www.supec.com.cn
SA4871
Block Diagram
4
IN-
3
IN+
2
B ypass
1
VO+
5
VO-
8
Vbias
Shutdown
Shutdown
C kt
Power an d
D epop Ckt
V DD
6
GND
7
Absolute Maximum Ratings
(Over operating free-air temperature range unless otherwise noted.)
Symbol
VDD
VIN, VO
Supply Voltage
Parameter
TA
TJ
TSTG
TS
Input Voltage Range, Shutdown, Bypass, VO
Operating Junction Temperature Range
Maximum Junction Temperature
Storage Temperature Range
Soldering Temperature Range
VESD
Electrostatic Discharge
PD
Power Dissipation
Rating
-0.3 to 6
Unit
V
-0.3 to VDD+0.3
V
-40 to 85
Internally Limited
-65 to +150
260
-2000 to 2000 (Note1)
-200 to 200 (Note2)
Internally Limited
°C
°C
°C
°C
V
W
Notes:
1.Human body model: C=100pF, R=1500Ω, 3 positives pulses plus 3 negative pulses
2.Machine model: C=200pF, L=0.5µF, 3 positive pulses plus 3 negative pulses
Copyright © SUPEC Electronics Corp.
Rev. A.1 - Nov., 2006
2
www.supec.com.cn
SA4871
Recommended Operating Conditions
Symbol
Parameter
Test Conditions
VDD
Supply Voltage
VIH
High-Level Voltage
Shutdown
VIL
Low-Level Voltage
Shutdown
Min.
Max.
Unit
2.5
5.5
V
V
2.2
V
0.4
Thermal Characteristics
Symbol
Parameter
Value
Unit
50
°C/W
Thermal Resistance - Junction to Ambient
RTHJA
MSOP-8-P*
SOP-8-P*
56
* Please refer to “Thermal Pad Consideration”. 2 layered 5 in printed circuit board with 2oz trace and copper through several
2
thermal vias. The thermal pad is solder on the PCB.
Electrical Characteristics
Unless otherwise noted these specifications apply over full temperature VDD= 5V, TA= 25°C (unless other-
wise noted)
Symbol
VOO
Parameter
Test Conditions
SA4871
Min.
Typ.
Max.
20
14
Unit
Output Offset Voltage
RL=8Ω, Ri=RF=20kΩ
Supply Current
Supply Current
IO=0mA
Shutdown Mode
7
0.1
|IH|
Shutdown, VI=VDD
0.1
µA
|IL|
Shutdown, VI=0V
0.1
µA
IDD
IDD(SD)
Operating characteristic, VDD=5V,TA=25°C
THD=1%, f=1kHz,
RL=3Ω
RL=4Ω
RL=8Ω
Po
Output Power
THD=10%, f=1kHz,
RL=3Ω
RL=4Ω
RL=8Ω
Copyright © SUPEC Electronics Corp.
Rev. A.1 - Nov., 2006
3
2.6
2.3
1.3
mV
mA
µA
W
3.3
2.7
1.7
www.supec.com.cn
SA4871
Electrical Characteristics (Cont.)
Unless otherwise noted these specifications apply over full temperature VDD= 5V, TA= 25°C (unless other-
wise noted)
Symbol
Parameter
Test Conditions
f=1kHz,
Total Harmonic Distortion Plus Po=2W, RL=3Ω
THD+N
Noise
Po=1.6W, RL=4Ω
Po=1W, RL=8Ω
Unity-Gain Bandwidth
Open Loop
B1
PSRR Power Supply Rejection Ratio CB=1µF, RL=8Ω, f=120kHz
Vn
Noise Output Voltage
Gain=2, CB=1µF, RL=8Ω
Twu
Wake-Up Time
CB=1µF
Min.
SA4871
Typ. Max.
0.06
0.04
0.03
2
60
28
380
Unit
%
MHz
dB
µV(rms)
ms
Pin Assignment
SA4871
Shutdown
1
8
VO-
Bypass
2
7
GND
IN+
3
6
VDD
IN-
4
5
VO+
= Thermal Pad
(connected to GND plane for better heat dissipation)
Pin Function Description
Pin
Name
I/O
No
Shutdown (SA4871)
1
Description
I
Bypass
2
I
IN+
3
I
IN-
4
I
VO+
VDD
GND
5
O
VO-
8
6
7
Shutdown mode control signal input, place entire IC in shutdown
mode when held high in SA4871.
Bypass pin
IN+ is the non-inverting input. IN+ is typically tied to the Bypass
terminal.
IN- is the inverting input. IN- is typically used as the audio input
terminal.
VO+ is the positive BTL output.
Supply voltage input pin.
Ground connection for circuitry.
O
Copyright © SUPEC Electronics Corp.
Rev. A.1 - Nov., 2006
VO- is the negative BTL output.
4
www.supec.com.cn
SA4871
Typical Application Circuit
RF
20K Ω
For SE input signal
Audio
IN
CI
0.47 µ F
RI
20K Ω
CB
1µ F
Shutdown
Signal
4
IN-
3
IN+
2
Bypass
1
Shutdown
VO+
5
VO-
8
Vbias
Shutdown
Ckt
4 Ω
Power and Depop
Ckt
VDD
6
GND
7
0.1µ F
CS
10µ F
RF
For Differential input signal
Audio
CI
RI
0.47 µ F
20K Ω
CI
RI
0.47 µ F
20K Ω
20K Ω
IN
Audio
4
IN-
3
IN+
2
Bypass
VO+
5
VO-
8
IN
RF
20K Ω
CB
Vbias
4 Ω
1µ F
Shutdown
Signal
Copyright © SUPEC Electronics Corp.
Rev. A.1 - Nov., 2006
1
Shutdown
Shutdown
Ckt
5
Power and Depop
Ckt
V DD
6
GND
7
0.1µ F
CS
10µ F
www.supec.com.cn
SA4871
Typical Characteristics
THD+N vs. Output Power
10
VDD=5V
Av=6dB
F=1KHz
1
RL=8Ω
RL=4Ω
THD+N (%)
THD+N (%)
10
THD+N vs. Output Power
RL=3Ω
0.1
VDD=5V
Av=6dB
RL=3Ω
1
F=20KHz
F=20Hz
0.1
F=1KHz
0.01
0.5
1
1.5
2
2.5
3
0.01
3.5
10m
100m
1
Output Power (W)
Output Power (W)
THD+N vs. Frequency
THD+N vs. Frequency
10
V DD=5V
Av=6dB
RL=3Ω
2
5
V DD=5V
Po=2W
RL=3Ω
1
1
THD+N (%)
THD+N (%)
10
0
0.1
Av=20dB
0.1
P o=1W
Av=6dB
P o=2W
0.01
20
100
1k
0.01
20
10k 20k
Frequency (Hz)
Copyright © SUPEC Electronics Corp.
Rev. A.1 - Nov., 2006
100
1k
10k
20k
Frequency (Hz)
6
www.supec.com.cn
SA4871
Typical Characteristics (Cont.)
THD+N vs. Output Power
10
10
V DD=5V
Av=6dB
RL=4Ω
1
THD+N (%)
THD+N (%)
THD+N vs. Frequency
F = 20KHz
F = 20Hz
0.1
VDD=5V
Av=6dB
RL=4Ω
1
0.1
Po=0.8W
F = 1KHz
0.01
10m
1
2
Po=1.6W
0.01
20
5
100
10k 20k
Frequency (Hz)
THD+N vs. Frequency
THD+N vs. Output Power
10
VDD=5V
Po=1.6W
RL=4Ω
1
VDD=5V
Av=6dB
RL=8Ω
1
0.1
Av=20dB
F = 20KHz
0.1
Av=6dB
0.01
20
1k
Output Power (W)
THD+N (%)
THD+N (%)
10
100m
100
1k
F = 1KHz
10k
0.01
10m
20k
Frequency (Hz)
Copyright © SUPEC Electronics Corp.
Rev. A.1 - Nov., 2006
F = 20Hz
100m
1
2
5
Output Power (W)
7
www.supec.com.cn
SA4871
Typical Characteristics (Cont.)
THD+N vs. Frequency
10
THD+N vs. Frequency
10
VDD=5V
Av=6dB
RL=8Ω
1
THD+N (%)
1
THD+N (%)
VDD=5V
Po=1W
RL=8Ω
0.1
0.1
Av=20dB
Po=0.5W
Po=1W
0.01
0.005
20
100
1k
Av=6dB
0.01
10k
0.005
20
20k
100
Frequency (Hz)
10k
Frequency Response
+6
+220
+220
Amplitude
Amplitude
+190
+4
Phase
Amplitude(dB)
+200
+5
+200
+190
+4
Phase
+180
VDD=5V
RL=3Ω
Po=1W
100
1k
10k
+3
10
Frequency (Hz)
Copyright © SUPEC Electronics Corp.
Rev. A.1 - Nov., 2006
+180
VDD=5V
RL=4Ω
Po=0.8W
+170
100k200k
Phase(Degress)
+5
+210
Phase(Degress)
Amplitude(dB)
+210
+3
10
20k
Frequency (Hz)
Frequency Response
+6
1k
100
1k
+170
100k 200k
10k
Frequency (Hz)
8
www.supec.com.cn
SA4871
Typical Characteristics (Cont.)
Frequency Response
Input Capacitor vs.
Frequency Response
+6
+10
+220
Amplitude
Rin=Rf=20k Ω
+5
+200
+190
+4
Phase
100
1k
10k
+0
Cin=2.2µf
Cin=1µf
Cin=0.47µf
Cin=0.1µf
-5
VDD=5V
RL=8Ω
Av=6dB
Po=0.5W
-10
+180
VDD=5V
RL=8Ω
Po=0.5W
+3
10
Amplitude(dB)
+5
Phase(Degress)
Amplitude(dB)
+210
-15
10
+170
100k 200k
100
Frequency (Hz)
1k
10k 20k
Frequency (Hz)
Shutdown Attenuation
PSRR vs. Frequency
vs. Frequency
+0
+0
Shutdown Attenuation(dB)
V DD=5V
-10 RL=8Ω
Cb=1µf
-20
PSRR(dB)
-30
-40
-50
-60
-70
-80
V DD=5V
Av=6dB
-20 RL=8Ω
-40
-60
-80
-100
-90
-100
20
100
1k
10k
-120
20k
Frequency (Hz)
Copyright © SUPEC Electronics Corp.
Rev. A.1 - Nov., 2006
20
100
1k
10k
20k
Frequency (Hz)
9
www.supec.com.cn
SA4871
Typical Characteristics (Cont.)
Output Noise Voltage vs.Frequency
Power Dissipation vs. Output Power
1.8
100u
20u
A-Weight
10u
5u
2u
RL=3Ω
1.4
RL=4Ω
1.2
1.0
0.8
RL=8Ω
0.6
0.4
0.2
20
8.0
Supply Current(mA)
Power Dissipation(W)
Filter BW<22KHz
100
1k
0
10k 20k
0
0.25 0.50
0.75
1.00
1.25
1.50 1.75
2.00 2.25 2.50
Frequency (Hz)
Output Power(W)
Supply Current vs. Supply Voltage
Supply Voltage vs. Output Power
4.0
Av=6dB
NoLoad
3.5
7.0
3.0
Output Power(W)
Output Noise Voltage(V)
50u
1u
VDD=5V
THD<1%
1.6
6.0
5.0
VDD=5V
Av=6dB
RL=3Ω
F=1KHz
BW<80KHz
2.5
THD=10%
2.0
THD=1%
1.5
1.0
0.5
4.0
2.5
3.0
3.5
4.0
4.5
5.0
0.0
2.5
5.5
3.5
4.0
4.5
5.0
5.5
Supply Voltage(V)
Supply Voltage(V)
Copyright © SUPEC Electronics Corp.
Rev. A.1 - Nov., 2006
3.0
10
www.supec.com.cn
SA4871
Typical Characteristics (Cont.)
Power Dissipation vs. Output Power
Output Power(W)
3.0
2.5
2.5
VDD=5V
Av=6dB
RL=4Ω
F=1KHz
BW<80KHz
2.0
Output Power(W)
3.5
Supply Current vs. Supply Voltage
THD=10%
2.0
1.5
THD=1%
1.0
VDD=5V
Av=6dB
RL=8Ω
F=1KHz
BW<80KHz
1.5
THD=10%
1.0
THD=1%
0.5
0.5
0.0
2.5
3.0
3.5
4.0
4.5
5.0
0.0
2.5
5.5
Supply Voltage(V)
3.0
3.5
4.0
4.5
5.0
5.5
Supply Voltage(V)
Application Descriptions
BTL Operation
amplifiers with identical in magnitude, but out of phase
The SA4871 output stage (power amplifier) has two
180°. Consequently, the differential gain for each
pairs of operational amplifiers internally, allowed for
channel is 2 x (Gain of SE mode).
different amplifier configurations.
By driving the load differentially through outputs OUT+
and OUT-, an amplifier configuration commonly referred
OUT+
to as bridged mode is established. BTL mode operation
is different from the classical single-ended SE
OP1
amplifier configuration where one side of its load is
OUTVbias
Circuit
connected to ground.
RL
A BTL amplifier design has a few distinct advantages
OP2
over the SE configuration, as it provides differential
drive to the load, thus doubling the output swing for a
Figure 1: SA4871 internal configuration
specified supply voltage.
Four times the output power is possible as compared
The power amplifier’s OP1 gain is setting by Ri and
toa SE amplifier under the same conditions. A BTL
Rf, while the second amplifier OP2 is internally fixed
configuration, such as the one used in SA4871 ,
in a unity-gain, inverting configuration. Figure 1 shows
also creates a second advantage over SE amplifiers.
that the output of OP1 is connected to the input to
Since the differential outputs, OUT+ and OUT- are biased
OP2, which results in the output signals of with both
Copyright © SUPEC Electronics Corp.
Rev. A.1 - Nov., 2006
11
www.supec.com.cn
SA4871
Application Descriptions (Cont.)
BTL Operation (Cont.)
a DC offset voltage at the input to the amplifier that
at half-supply, no need DC voltage exists across the
reduces useful headroom, especially in high gain
load. This eliminates the need for an output coupling
capacitor which is required in a single supply, SE
configuration.
applications. For this reason a low-leakage tantalum
or ceramic capacitor is the best choice. When polarized capacitors are used, the positive side of the capacitor should face the amplifier input in most
Input Resistance, Ri
appli-
cations as the DC level there is held at VDD/2, which is
The gain for audio input of the SA4871 is set by
likely higher that the source DC level. Please note that
the external resistors (Ri and Rf).
RF
BTL Gain = -2 x
Ri
it is important to confirm the capacitor polarity in the
(1)
BTL mode operation brings the factor of 2 in the gain
application.
Effective Bypass Capacitor, Cbypass
equation due to the inverting amplifier mirroring the
As other power amplifiers, proper supply bypassing is
voltage swing across the load. The input resistance
critical for low noise performance and high power supply
will affect the low frequency performance of audio
rejection.
signal.
The capacitors located on both the bypass and power
Input Capacitor, Ci
supply pins should be as close to the device as
In the typical application an input capacitor, Ci, is
required to allow the amplifier to bias the input signal
to the proper DC level for optimum operation. In this
case, Ci and the input impedance Ri (20kΩ) form a
high-pass filter with the corner frequency determined
in the follow equation :
FC(highpass)=
1
2πx20kΩxCi
(2)
The value of Ci is important to consider as it directly
affects the low frequency performance of the circuit.
Consider the example where Ri is 10kΩ and the
specification calls for a flat bass response down to
possible. The effect of a larger bypass capacitor will
improve PSRR due to increased supply stability. Typical
applications employ a 5V regulator with 1.0µF and a
0.1µF bypass capacitor as supply filtering. This does
not eliminate the need for bypassing the supply nodes
of the SA4871. The selection of bypass capacitors,
especially Cbypass, is thus dependent upon desired
PSRR requirements, click and pop performance.
To avoid start-up pop noise occurred, the bypass voltage should rise slower than the input bias voltage and
the relationship shown in equation (4) should be
maintained.
1
1
<<
Cbypass x 125kΩ
40kΩ x Ci
50Hz. Equation is reconfigured as follow :
1
Ci=
(3)
2πx20kΩxfC
The bypass capacitor is fed thru from a 125kΩ resistor
Ci is 0.16µF so one would likely choose a value in
inside the amplifier and the 40kΩ is maximum input
the range of 0.22µF to 1.0µF.
resistance of (Ri+ Rf). Bypass capacitor, Cb, values
A further consideration for this capacitor is the leakage
path from the input source through the input network
(Ri+Rf, Ci) to the load. This leakage current creates
Copyright © SUPEC Electronics Corp.
Rev. A.1 - Nov., 2006
(4)
of 3.3µF to 10µF ceramic or tantalum low-ESR capacitors
are recommended for the best THD and noise
performance.
12
www.supec.com.cn
SA4871
Application Descriptions (Cont.)
Effective Bypass Capacitor, Cbypass (Cont.)
The bypass capacitance also effects to the start up
time. It is determined in the following equation :
Tstart up = 5 x (Cbypass x 125KΩ)
(5)
Power Supply Decoupling, Cs
The
SA4871 is a high-performance CMOS audio
amplifier that requires adequate power supply
decoupling to ensure the output total harmonic
turn-on time and the amount of clicks and pops. By
increasing the value of Cbypass, turn-on pop can be
reduced. However, the tradeoff for using a larger
bypass capacitor is to increase the turn-on time for
this device. There is a linear relationship between the
size of Cbypass and the turn-on time.
A high gain amplifier intensifies the problem as the
small delta in voltage is multiplied by the gain. So it is
advantageous to use low-gain configurations.
distortion (THD) is as low as possible. Power supply
Shutdown Function
decoupling also prevents the oscillations causing by
In order to reduce power consumption while not in use,
long lead length between the amplifier and the speaker.
The optimum decoupling is achieved by using two
different type capacitors that target on different type of
noise on the power supply leads.
For higher frequency transients, spikes, or digital hash
the SA4871
contains a shutdown pin to externally
turn off the amplifier bias circuitry. This shutdown feature
turns the amplifier off when a logic high is placed on the
SHUTDOWN pin. The trigger point between a logic
high and logic low level is typically 2.0V. It is best
on the line, a good low equivalent-series-resistance
to switch between ground and the supply VDD to
(ESR) ceramic capacitor, typically 0.1µF placed as
provide maximum device performance.
close as possible to the device VDD lead works best.
For filtering lower-frequency noise signals, a large
aluminum electrolytic capacitor of 10µF or greater
placed near the audio power amplifier is recommended.
Optimizing Depop Circuitry
Circuitry has been included in the SA4871 to minimize
By switching the SHUTDOWN pin to high, the amplifier
enters a low-current state, IDD< 0.1µA. SA4871 is in
shutdown mode. On normal operating, SHUTDOWN
pin pull to low level to keeping the IC out of the shutdown
mode. The SHUTDOWN pin should be tied to a definite
voltage to avoid unwanted state changes.
the amount of popping noise at power-up and when
BTL Amplifier Efficiency
coming out of shutdown mode. Popping occurs whenever
An easy-to-use equation to calculate efficiency starts
a voltage step is applied to the speaker. In order to
out as being equal to the ratio of power from the power
eliminate clicks and pops, all capacitors must be fully
supply to the power delivered to the load.
discharged before turn-on. Rapid on/off switching of
The following equations are the basis for calculating
the device or the shutdown function will cause the click
amplifier efficiency.
PO
Efficiency =
PSUP
Where :
V ORMS × V ORMS
PO =
RL
VP
VORMS =
√2
and pop circuitry.
The value of Ci will also affect turn-on pops. (Refer to
Effective Bypass Capacitance) The bypass voltage ramp
up should be slower than input bias voltage. Although
the bypass pin current source cannot be modified, the
size of Cbypass can be changed to alter the device
Copyright © SUPEC Electronics Corp.
Rev. A.1 - Nov., 2006
PSUP = VDD x IDDAVG = VDD x
13
(6)
VP × VP
2RL
=
(7)
2VP
πRL
(8)
www.supec.com.cn
SA4871
Application Descriptions (Cont.)
BTL Amplifier Efficiency (Cont.)
Power Dissipation
Efficiency of a BTL configuration :
In BTL mode operation, the output voltage swing is
PO
VPxVP ) / (VDD x2VP ) = πV P
=(
4VDD
PSUP
πRL
2RL
(9)
Table 1 calculates efficiencies for four different output
power levels.
Note that the efficiency of the amplifier is quite low for
lower power levels and rises sharply as power to the
load is increased resulting in a nearly flat internal power
dissipation over the normal operating range.
doubled as in SE mode. Thus the maximum power
dissipation point for a BTL mode operating at the same
given conditions is 4 times as in SE mode.
4VDD2
BTL mode : PD,MAX=
2π2RL
(10)
Even with this substantial increase in power dissipation,
the SA4871 does not require extra heatsink. The
power dissipation from equation11, assuming a 5Vpower supply and an 8Ω load, must not be greater
than the power dissipation that results from the
Note that the internal dissipation at full output power
equation11 :
is less than in the half power range. Calculating the
efficiency for a specific system is the key to proper
power supply design.
A final point to remember about linear amplifiers (either
SE or BTL) is how to manipulate the terms in the
efficiency equation to utmost advantage when possible.
Note that in equation, VDD is in the denominator. This
indicates that as VDD goes down, efficiency goes up.
PD,MAX=
TJ,MAX - TA
θJA
(11)
For MSOP8-P package with thermal pad, the thermal
resistance (θJA) is equal to 48οC/W.
Since the maximum junction temperature (TJ,MAX) of
SA4871 is 150οC and the ambient temperature (TA)
is defined by the power system design, the maximum
power dissipation which the IC package is able to
In other words, use the efficiency analysis to choose
handle can be obtained from equation11.
the correct supply voltage and speaker impedance for
Once the power dissipation is greater than the maximum
the application.
limit (PD,MAX), either the supply voltage (VDD) must be
decreased, the load impedance (RL) must be increased
Po (W) Efficiency (%) IDD(A) VPP(V) PD (W)
0.25
31.25
0.16
2.00
0.55
0.50
47.62
0.21
2.83
0.55
1.00
66.67
0.30
4.00
0.5
1.25
78.13
0.32
4.47
0.35
** High peak voltages cause the THD to increase.
Table 1. Efficiency Vs Output Power in 5-V/8Ω BTL
Systems.
or the ambient temperature should be reduced.
Thermal Pad Considerations
The thermal pad must be connected to ground. The
package with thermal pad of the SA4871 requires
special attention on thermal design. If the thermal
design issues are not properly addressed, the
SA4871 4Ω will go into thermal shutdown when
driving a 4Ω load.
The thermal pad must be connected to ground. The
package with thermal pad of the SA4871 requires
special attention on thermal design. If the thermal
Copyright © SUPEC Electronics Corp.
Rev. A.1 - Nov., 2006
14
www.supec.com.cn
SA4871
Application Descriptions (Cont.)
Thermal Pad Considerations (Cont.)
0.087
design issues are not properly addressed, the
Via diameter
=25mil X4
0.090
Via diameter
=15mil X12
SA4871 4Ω will go into thermal shutdown when
driving a 4Ω load.
0.024
The thermal pad on the bottom of the SA4871
should be soldered down to a copper pad on the circuit
board. Heat can be conducted away from the thermal
0.050
pad through the copper plane to ambient. If the copper
plane is not on the top surface of the circuit board, 8 to
12 vias of 15 mil or smaller in diameter should be used
to thermally couple the thermal pad to the bottom
plane.
0.020
0.205
For good thermal conduction, the vias must be plated
Ground
plane for
ThermalPAD
through and solder filled. The copper plane used to
conduct heat away from the thermal pad should be as
large as practical.
SOP-8-P Layout Recommendation
Thermal Considerations
If the ambient temperature is higher than 25°C, a larger
Linear power amplifiers dissipate a significant amount
copper plane or forced-air cooling will be required to
of heat in the package under normal operating
keep the SA4871 junction temperature below the
thermal shutdown temperature (150°C). In higher ambient
conditions.
temperature, higher airflow rate and/or larger copper
To calculate maximum ambient temperatures, refer the
area will be required to keep the IC out of thermal
“Power Dissipation vs. Output Power” graphs.
shutdown.
Given θJA, the maximum allowable junction tempera-
0.040
0.032
ture (TJMAX), and the total internal dissipation (PD), the
0.120
maximum ambient temperature can be calculated with
Via diameter
=15mil X12
the following equation. The maximum recommended
junction temperature for the SA4871 is 150°C. The
0.016
internal dissipation figures are taken from the Power
Dissipation vs. Output Power graphs.
TAMax = TJMax -θJAPD
0.0256
(12)
150 - 50(1.3) = 85°C
The SA4871 is designed with a thermal shutdown
protection that turns the device off when the junction
Ground
plane for
ThermalPAD
temperature surpasses 150°C to prevent damaging the
0.189
IC.
MSOP-8-P Layout Recommendation
Copyright © SUPEC Electronics Corp.
Rev. A.1 - Nov., 2006
4
www.supec.com.cn
SA4871
Packaging Information
E
E1
0.015X45
SOP-8-P pin ( Reference JEDEC Registration MS-012)
H
D1
e1
e2
D
A1
A
L
0.004max.
Dim
1
Millimeters
Inches
Min.
Max.
Min.
Max.
A
1.35
1.75
0.053
0.069
A1
0
0 .1 5
0
0.00 6
D
D1
4.80
5.00
0.189
E
3.80
3 . 0 0R E F
0.197
0.118REF
4.00
0.150
2 . 6 0R E F
0.157
E1
H
5.80
6.20
0.228
0.244
L
0.40
1.27
0.016
0.050
e1
e2
0.33
0.51
0.013
0.02 0
φ 1
Copyright © SUPEC Electronics Corp.
Rev. A.1 - Nov., 2006
0.102REF
1.27BSC
0.50BSC
8°
8°
16
1www.supec.com.cn
SA4871
Packaging Information
MSOP-8-P
e1
E
E1
H1
GAUGE
PLANE
D1
L
C
e1
0.25
L1
A2
A1
A3
Dim
A1
A2
A3
C
e
e1
E
E1
D1
H1
L
L1
φ
Min.
0.06
0.25
0.13
2.90
4.8
2.90
0.9
0.45
Millimeters
0.86 TYP
0.65 TYP
2.146 REF
1.740 REF
Copyright © SUPEC Electronics Corp.
Rev. A.1 - Nov., 2006
6°
Max.
0.15
Min.
0.002
0.4
0.23
0.01
0.005
3.1
5.0
3.1
0.114
0.189
0.114
1.0
0.65
0.036
0.018
17
Inches
Max.
0.006
0.34 TYP
0.0256 TYP
0.0845 REF
0.0685 REF
6°
0.0126
0.009
0.122
0.197
0.122
0.039
0.026
www.supec.com.cn
SA4871
Physical Specifications
Terminal Material
Lead Solderability
Solder-Plated Copper (Solder Material : 90/10 or 63/37 SnPb), 100%Sn
Meets EIA Specification RSI86-91, ANSI/J-STD-002 Category 3.
Reflow Condition
(IR/Convection or VPR Reflow)
tp
TP
Critical Zone
T L to T P
Temperature
Ramp-up
TL
tL
Tsmax
Tsmin
Ramp-down
ts
Preheat
25
t 25 °C to Peak
Tim e
Classificatin Reflow Profiles
Profile Feature
Average ramp-up rate
(TL to TP)
Preheat
- Temperature Min (Tsmin)
- Temperature Max (Tsmax)
- Time (min to max) (ts)
Time maintained above:
- Temperature (TL)
- Time (tL)
Peak/Classificatioon Temperature (Tp)
Time within 5°C of actual
Peak Temperature (tp)
Ramp-down Rate
Sn-Pb Eutectic Assembly
Pb-Free Assembly
3°C/second max.
3°C/second max.
100°C
150°C
60-120 seconds
150°C
200°C
60-180 seconds
183°C
60-150 seconds
217°C
60-150 seconds
See table 1
See table 2
10-30 seconds
20-40 seconds
6°C/second max.
6°C/second max.
6 minutes max.
8 minutes max.
Time 25°C to Peak Temperature
Notes: All temperatures refer to topside of the package .Measured on the body surface.
Copyright © SUPEC Electronics Corp.
Rev. A.1 - Nov., 2006
18
www.supec.com.cn
SA4871
Classification Reflow Profiles(Cont.)
Table 1. SnPb Entectic Process – Package Peak Reflow Temperatures
Package Thickness
Volum e m m 3
Volum e m m 3
<350
≥350
<2.5 m m
240 +0/-5°C
225 +0/-5°C
≥2.5 m m
225 +0/-5°C
225 +0/-5°C
Table 2. Pb-free Process – Package Classification Reflow Temperatures
3
3
3
Package Thickness
Volum e m m
Volum e m m
Volum e m m
<350
350-2000
>2000
<1.6 m m
260 +0°C*
260 +0°C*
260 +0°C *
1.6 m m – 2.5 m m
260 +0°C*
250 +0°C*
245 +0°C *
250 +0°C*
245 +0°C*
245 +0°C *
≥2.5 m m
*Tolerance: The device manufacturer/supplier shall assure process compatibility up to and
including the stated classification temperature (this means Peak reflow temperature +0°C .
For exam p le 260°C+0 °C) at the rated M S L level.
Reliability Test Program
Test item
SOLDERABILITY
HOLT
PCT
TST
ESD
Latch-Up
Method
MIL-STD-883D-2003
MIL-STD-883D-1005.7
JESD-22-B,A102
MIL-STD-883D-1011.9
MIL-STD-883D-3015.7
JESD 78
Description
245°C, 5 SEC
1000 Hrs Bias @125°C
168 Hrs, 100%RH, 121°C
-65°C~150°C, 200 Cycles
VHBM > 2KV, VMM > 200V
10ms, 1 tr > 100mA
Carrier Tape & Reel Dimensions
t
E
D
P
Po
P1
Bo
F
W
Ao
Copyright © SUPEC Electronics Corp.
Rev. A.1 - Nov., 2006
D1
19
Ko
www.supec.com.cn
SA4871
Carrier Tape & Reel Dimensions (Cont.)
T2
J
C
A
B
T1
Carrier Tape & Reel Dimensions
Application
M/SOP-8-P
A
B
330±1
62 ± 1.5
F
D
5.5 ± 0.1
C
12.75 +
0.1 5
D1
J
T1
T2
2 + 0.5
12.4 +0.2
2± 0.2
Po
P1
Ao
W
12 + 0.3
- 0.1
Bo
2.0 ± 0.1
6.4 ± 0.1
5.2± 0.1
1.55±0.1 1.55+ 0.25 4.0 ± 0.1
P
E
8± 0.1
1.75± 0.1
Ko
t
2.1± 0.1 0.3±0.013
(mm)
Cover Tape Dimensions
Application
SOP- 8-P
M/SOP- 8-P
Carrier Width
12
12
Cover Tape Width
9.3
9.3
Devices Per Reel
2500
3000
Customer Service
Supec Electronics Corp.
Head Office :
A411, 328 Airport Road,Suzhou Industrial Park,
Suzhou,P.R.China
Tel : +86-512-6252 2212
Fax : +86-512-6252 2126
Shenzhen Branch :
A-507,Hi-Tech Venture Park,Tian'an Cyber Park,
Shenzhen,P.R.China.
Tel : +86-755-8204 9356
Fax : +86-755-8204 9359
Copyright © SUPEC Electronics Corp.
Rev. A.1 - Nov., 2006
20
www.supec.com.cn