APA3002 12W Stereo Class-D Audio Power Amplifier Features • • • General Description Class-D Operation with High Efficiency. 32-Step DC Volume Control With Hysteresis The APA3002 is a monolithic integrated circuit, which provides precise DC volume control, and a stereo Class-D 9W Per Channel Output Power into 8Ω Load at 12V, Class-D Output audio power amplifiers capable of producing 9W into 8Ω (12V) with less than 10% THD+N. The attenuator range 12W Per Channel Output into 6Ω Load at 12V, Class-D Output of the volume control in the APA3002 is from 36dB (VVOLUME=5V) to -40dB (VVOLUME=0V) with 32 steps. The ad- 5V LDO Output for Powering APA4801 Headphone Driver vantage of internal gain setting can be less components and PCB area. The circuitries of both thermal and the Line Output for APA4801 Headphone Driver with DC Volume Control over-current protections are integrated in the APA3002. It protects the chip from being destroyed by over tempera- Low Current Consumption in Shutdown Mode (10µA, Typical) ture and over current failure. To simplify the audio system design, the APA3002 com- APA3002 will Auto-Recovery after Over-Current Protection bines a line output for external headphone driver with volume control and a 5V regulator for external headphone • • Thermal and Over-Current Protections TQFN7x7-48 with Thermal Pad Package drive, where the speaker output can be switched off by the headphone jack’s switch pin that connects to the APA3002’s mode pin as shown in the application circuit. • TQFP7x7-48P with Thermal Pad Package Lead Free and Green Devices Available • • • • • Applications (RoHS Compliant) • • LCD TV Active Speaker Ordering and Marking Information APA3002 Assembly Material Handling Code Temperature Range Package Code Package Code QB: TQFN7x7-48 QCA: TQFP7x7-48P Operating Ambient Temperature Range I : -40 to 85 oC Handling Code TR: Tape & Reel Assembly Material G : Halogen and Lead Free Device APA3002 QB: APA3002 XXXXX XXXXX - Date Code APA3002 QCA: APA3002 XXXXX XXXXX - Date Code Note : ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by weight). ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright ANPEC Electronics Corp. Rev. A.6 - Sep., 2009 1 www.anpec.com.tw APA3002 48 47 46 45 44 43 42 41 40 39 38 37 48 47 46 45 44 43 42 41 40 39 38 37 RBSRPVDD RPVDD ROUTROUTRPGND RPGND ROUT+ ROUT+ RPVDD RPVDD RBS+ RBSRPVDD RPVDD ROUTROUTRPGND RPGND ROUT+ ROUT+ RPVDD RPVDD RBS+ Pin Configurations SD 1 RIN- 2 RIN+ 3 2.5VREF 4 LIN+ 5 LIN- 6 LDOREF 7 VREF 8 VARDIFF 9 VARMAX 10 VOLUME 11 REFGND 12 APA3002 RCLAMP SD 1 MODEOUT RIN- 2 MODE RIN+ 3 AVDD 2.5VREF 4 RVAROUT LIN+ 5 LVAROUT LIN- 6 AGND LDOREF 7 VREF 8 5VLDO VARDIFF 9 COSC VARMAX 10 ROSC VOLUME 11 AGND LCLAMP REFGND 12 36 35 34 33 32 31 30 29 28 27 26 25 APA3002 RCLAMP MODEOUT MODE AVDD RVAROUT LVAROUT AGND 5VLDO COSC ROSC AGND LCLAMP LBSLPVDD LPVDD LOUTLOUTLPGND LPGND LOUT+ LOUT+ LPVDD LPVDD LBS+ 13 14 15 16 17 18 19 20 21 22 23 24 LBSLPVDD LPVDD LOUTLOUTLPGND LPGND LOUT+ LOUT+ LPVDD LPVDD LBS+ 13 14 15 16 17 18 19 20 21 22 23 24 (APA3002D) 36 35 34 33 32 31 30 29 28 27 26 25 TQFN7x7-48 (TOP VIEW) TQFP7x7-48P (TOP VIEW) Absolute Maximum Ratings (Note 1) (Over operating free-air temperature range unless otherwise noted.) Symbol VDD VMODE, VVREF, VVOLUME, VVARDIFF, VVARMAX VSD VRIN+, VRIN-,VLIN+,VLIN- Parameter Rating Unit Supply Voltage (AVDD to AGND, LPVDD to LPGND, and RPVDD to RPGND) -0.3 to 15 V Input Voltage (MODE to AGND, VREF, VOLUME, VARDIFF, and VARMAX to REFGND) -0.3 to 5.5 Input Voltage (SD to AGND) -0.3 to VDD+0.3 Input Voltage (RIN+, RIN-, LIN+, and LIN- to AGND) Input Voltage (RPGND and LPGND to AGND) V -0.3 to 7 -0.3 to +0.3 I5VLDO Output Current (5VLDO) 120 ILDOREF Output Current (LDOREF) 20 Maximum Junction Temperature 150 ο -65 to +150 ο 260 ο TJ TSTG TSDR Storage Temperature Range Maximum Lead Soldering Temperature, 10 Seconds PD Power Dissipation RL Class-D Power Amplifier Minimum Load Resistance mA C C C Internally Limited W 4 Ω Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Copyright ANPEC Electronics Corp. Rev. A.6 - Sep., 2009 2 www.anpec.com.tw APA3002 Thermal Characteristics Symbol θJA Parameter Thermal Resistance -Junction to Ambient Typical Value Unit (Note 2) TQFN7x7-48 TQFP7x7-48P ο 21 25 C/W Note 2: Please refer to “Thermal Pad Consideration”. The Thermal Pad on the bottom of the IC should be soldered directly to the PCB’s Thermal Pad area connected to the ground plan by several thermal vias, and the PCB is a 2-layer, 5-inch square area with 2oz copper thickness. Recommended Operating Conditions Symbol VDD Range Parameter Min. Supply Voltage 14 V 3.0 5.5 V VOLUME, VARMAX, VARDIFF - 5.5 V SD 2 - V 3.5 - V - 0.8 V VREF Volume Control Pin, Input Voltage High-level Input Voltage VIL Low-level Input Voltage Unit 8.5 Volume Reference Voltage VIH Max. MODE SD MODE - 2 V V5VLDO -100m - V - +100m V VOH High-level Output Voltage MODEOUT sources 1mA VOL Low-level Output Voltage MODEOUT sinks 1mA fOSC Oscillator Frequency 225 275 kHz TA Operating Free-Air Temperature -40 85 ° C RL Class-D Power Amplifier Minimum Load Resistance 6 - Ω Electrical Characteristics VDD =12V, DGND=AGND=0V, TA= 25οC (unless otherwise noted) Symbol VDD IDD ISD Parameter Test Condition Supply Voltage VDD Supply Current VDD Shutdown Current Class-D mode, VMODE=0V, VSD =5V, no load VAROUT mode, VMODE=5V, VSD =5V, no load VSD = 0V APA3002 Unit Min. Typ. Max. 8.5 - 14 V - 20 40 mA - 3 6 mA - 10 100 µA CLASS-D MODE, AV=15.7dB (VOLTAGE GAIN=RATIO OF THE FILTERED OUTPUT VOLTAGE TO INPUT VOLTAGE) PO Output Power Crosstalk Total Harmonic Distortion Plus Noise Channel Separation PSRR Power Supply Rejection Ratio THD+N Copyright ANPEC Electronics Corp. Rev. A.6 - Sep., 2009 THD+N = 1%, fin = 1kHz, RL = 6Ω - 10 THD+N = 1%, fin = 1kHz, RL = 8Ω 6 7.5 - THD+N = 10%, fin = 1kHz, RL = 6Ω - 12 - THD+N = 10%, fin = 1kHz, RL = 8Ω - 9 - PO= 5W, fin= 1kHz, RL = 8Ω - 0.2 - % PO= 5W, fin=1kHz, CB=1µF - 90 - dB RL = 8Ω, fin = 120Hz - 85 - dB 3 W www.anpec.com.tw APA3002 Electrical Characteristics (Cont.) VDD =12V, DGND=AGND=0V, TA= 25οC (unless otherwise noted) Symbol APA3002 Unit Min. Typ. Max. CLASS-D MODE, AV=15.7dB (VOLTAGE GAIN=RATIO OF THE FILTERED OUTPUT VOLTAGE TO INPUT VOLTAGE) (CONT.) With A-Weighting Filter S/N 85 dB PO = 5W, RL = 8Ω VOS Output Offset Voltage 20 mV RL = 8Ω Vn Parameter Test Condition Noise Output Voltage High side Rds(on) Power MOSFET Drain-Source On-State Resistance - 250 - - 300 - µV (rms) Low side - 250 - Total - 550 650 THD+N = 1%, fin = 1kHz, RL = 32Ω - 20 - THD+N = 10%, fin = 1kHz, RL = 32Ω - 25 - fin= 1kHz, RL = 32Ω, PO = 14mW, - 0.05 - VO= 1Vrms, RL=47kΩ, fin=1kHz - 0.005 - - 63 - dB - 85 - dB - - 20 mV - 80 - dB - 30 - µV (rms) IO=1A mΩ VAROUT OUTPUT, AV=10dB PO THD+N Crosstalk PSRR Vos Output Power Total Harmonic Distortion Plus Noise Channel Separation Power Supply Rejection Ratio Output Offset Voltage S/N Vn Noise Output Voltage PO=14mW, RL = 32Ω, fin=1kHz, CB=1µF CB = 1µF, RL = 32Ω, fin =120Hz, VRR=0.2Vrms RL = 32Ω With A-Weighting Filter PO= 20mW, RL = 32Ω, CB = 1µF mW % LINEAR REGULATORS (LDO) V5VLDO 5V LDO Regulator Output I5VLDO =0-100mA, VSD =5V V2.5VREF 2.5V Reference Voltage No load PSRR Power Supply Rejection Ratio CB = 1µF, fin= 120Hz Copyright ANPEC Electronics Corp. Rev. A.6 - Sep., 2009 4 4.5 5 5.5 V 0.45X V5VLDO 0.50X V5VLDO 0.55X V5VLDO V - 73 - dB www.anpec.com.tw APA3002 Typical Operating Characteristics Efficiency vs. Output Power 100 100 90 90 80 80 70 70 Efficiency (%) Efficiency (%) Efficiency vs. Output Power 60 50 VDD =12V RL=8Ω AV=36dB Bead filter AUX-0025 AES-17(20kHz) Class-D 40 30 20 10 0 0 2 4 6 8 Output Power (W) 10 60 50 VDD =12V RL=8Ω+33µH AV=36dB Bead filter AUX-0025 AES-17(20kHz) Class-D 40 30 20 10 0 12 0 Output Power vs. Load Resistance 16 VDD=14V THD+N=10% Output Power (W) 14 12 10 6 VDD=8.5V THD+N=10% 4 0 6 8 Ci=1µF RL=8Ω 12 AV=36dB fin=1kHz AUX-0025 10 AES-17 (20kHz) Class-D 10 12 14 Load Resistance (Ω) 14 12 THD+N=1% 6 2 8.5 9 16 12 10 11 Supply Voltage (V) 13 14 THD+N vs. Output Power 10 fin=1kHz THD+N=10% 1 THD+N (%) Output Power (W) 16 Ci=1µF RL=6Ω Av=36dB fin=1kHz AUX-0025 AES-17 (20kHz) Class-D THD+N=10% 8 Output Power vs. Supply Voltage 18 12 4 VDD=8.5V THD+N=1% 2 10 14 Ci=1µF Av=36dB fin=1kHz AUX-0025 AES-17 (20kHz) Class-D VDD=14V THD+N=1% 8 4 6 8 Output Power (W) Output Power vs. Supply Voltage Output Power (W) 18 2 10 0.1 VDD=12V Ci=1µF RL=6Ω Av=15.7dB AUX-0025 AES-17 (20kHz) Class-D fin=50Hz 8 THD+N=1% fin=15kHz 6 4 8.5 9 10 11 12 Supply Voltage (V) Copyright ANPEC Electronics Corp. Rev. A.6 - Sep., 2009 13 0.01 0.005 10m 14 5 100m 1 Output Power (W) 10 20 www.anpec.com.tw APA3002 Typical Operating Characteristics (Cont.) THD+N vs. Output Power 10 10 VDD =14V Ci=1µF RL=8Ω AV=15.7dB AUX-0025 AES-17 (20kHz) Class-D fin=1kHz 1 THD+N (%) 1 THD+N (%) THD+N vs. Frequency 0.1 fin=50Hz R VDD =14V Ci=1µF RL=8Ω AV=15.7dB AUX-0025 AES-17 (20kHz) Class-D PO=7W 0.1 PO=3.5W 0.01 0.005 10m fin=15kHz 100m PO=0.5W 1 0.01 20 10 20 100 Output Power (W) THD+N vs. Frequency THD+N (%) 1 VDD =14V Ci=1µF RL=8Ω PO=7W AUX-0025 AES-17 (20kHz) Class-D VDD =14V Ci=1µF RL=8Ω PO=3.5W AV=15.7dB AUX-0025 AES-17 (20kHz) Class-D -10 -20 -30 AV=36dB 0.1 AV=20.8dB 10K 20K Crosstalk vs. Frequency +0 Crosstalk (dB) 10 1K Frequency (Hz) -40 -50 -60 -70 -80 AV=10.7dB Left channel to Right channel -90 0.01 Right channel to Left channel 20 100 1k Frequency (Hz) -100 20 10k 20k Noise vs. Frequency 10 Left Channel 1 THD+N (%) Output Noise Voltage (µV) Right Channel 100µ VDD =14V Ci=1µF RL=8Ω AV=15.6dB AUX-0025 LPF=22~22kHz A-Weighting Class-D 20 100 1k Frequency (Hz) Copyright ANPEC Electronics Corp. Rev. A.6 - Sep., 2009 1k Frequency (Hz) 10k 20k THD+N vs. Output Power 500µ 10µ 100 VDD =12V Ci=1µF RL=8Ω Av=15.7dB AUX-0025 fin=1kHz 0.1 fin=50Hz 0.01 fin=20kHz AES-17(20kHz) Class-D 0.001 10m 10k 20k 6 100m 1 Output Power (W) 5 10 www.anpec.com.tw APA3002 Typical Operating Characteristics (Cont.) THD+N vs. Frequency 10 VDD =12V Ci=1µF RL=8Ω AV=15.7dB AUX-0025 AES-17(20kHz) Class-D 1 THD+N (%) 1 THD+N (%) THD+N vs. Frequency 10 PO=0.5W PO=5W 0.1 VDD =12V Ci=1µF RL=8Ω PO=5W AUX-0025 AES-17 (20kHz) Class-D AV=36dB 0.1 PO=2.5W 0.01 20 100 1k Frequency (Hz) 10k 20k 100 Crosstalk vs. Frequency Output Noise Voltage (µV) Crosstalk (dB) Right Channel -60 Left channel to Right channel -100 Right channel to Left channel 100 500 Frequency (Hz) Left Channel 100µ 10µ 10k 20k VDD =12V Ci=1µF RL=8Ω AV=15.6dB AUX-0025 LPF=22~22kHz A-Weighting Class-D 20 THD+N vs. Output Power 10 0.1 10 VDD =8.5V Ci=1µF RL=8Ω AV=15.7dB AUX-0025 AES-17 (20kHz) Class-D fin=1kHz 1 fin=50Hz 100m 1 Output Power (W) Copyright ANPEC Electronics Corp. Rev. A.6 - Sep., 2009 1k Frequency (Hz) 10k 20k 0.1 VDD =8.5V Ci=1µF RL=8Ω AV=15.7dB AUX-0025 AES-17(20kHz) Class-D PO=2.5W PO=0.5W PO=1.25W fin=15kHz 0.01 10m 100 THD+N vs. Frequency THD+N (%) THD+N (%) 1 10k 20k 500µ VDD =12V Ci=1µF -20 RL=8Ω PO=2.5W AV=15.7dB -40 AUX-0025 AES-17 (20kHz) Class-D -120 20 1k Frequency (Hz) Noise vs. Frequency +0 -80 AV=10.7dB AV=20.8dB 0.01 20 0.01 20 5 7 100 1k Frequency (Hz) 10k 20k www.anpec.com.tw APA3002 Typical Operating Characteristics (Cont.) THD+N vs. Frequency 10 500µ VDD =8.5V Ci=1µF RL=8Ω PO=2.5W AUX-0025 AES-17 (20kHz) Class-D Right Channel Output Noise Voltage (µV) 1 THD+N (%) Noise vs. Frequency AV=36dB 0.1 AV=20.8dB AV=10.7dB 0.01 20 100 1k Left Channel 100µ 10µ 20 10k 20k VDD =8.5V Ci=1µF RL=8Ω AV=15.6dB AUX-0025 LPF=22~22kHz A-Weighting Class-D 100 Frequency (Hz) Input Resistance vs. Gain Common-Mode Rejection Ratio (dB) Class-D Input Resistance (kΩ) 140 120 100 80 60 40 20 -30 -10 10 Gain (dB) 30 Gain (36dB) +25 +20 +15 Phase (36dB) Phase (15.7dB) Gain (15.7dB) +10 +50 +0 -50 -100 +5 +010 +100 Phase (degree) Gain (dB) +30 +150 VDD =12V Ci=1µF RL=8Ω PO=0.75W AUX-0025 Class-D -150 100 1k 10k Frequency (Hz) Copyright ANPEC Electronics Corp. Rev. A.6 - Sep., 2009 -30 -40 -50 -60 -70 100 1k Frequency (Hz) 10k 20k Shutdown Attenuation vs. Frequency Shutdown Attenuation (dB) +35 VDD =12V Ci=1µF RL=8Ω VO=1V AV=15.7dB AUX-0025 Class-D -20 20 50 Frequency Response +40 10k 20k CMRR vs. Frequency 160 0 -50 1k Frequency (Hz) 100k 8 +0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 20 VDD =12V Ci=1µF RL=8Ω PO=1W AV=36dB VSD=0V AUX-0025 AES-17(20kHz) Class-D 100 1k Frequency (Hz) 10k 20k www.anpec.com.tw APA3002 Typical Operating Characteristics (Cont.) Mode Attenuation vs. Frequency Mute Attenuation vs. Frequency +0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 VDD =12V -10 Ci=1µF RL=8Ω PO=1W -20 Volume=0V AUX-0025 -30 AES-17(20kHz) Class-D -40 -50 -60 -70 -80 20 100 VDD =12V Ci=1µF RL=8Ω PO=1W AV=36dB Mode=5V AUX-0025 AES-17(20kHz) Class-D Mode Attenuation (dB) Mute Attenuation (dB) +0 1k Frequency (Hz) 20 10k 20k 100 PSRR vs. Frequency Inter-modulation Performance +0 -60 VDD =12V RL=8Ω VRR=0.5Vrms AV=36dB AUX-0025 AES-17(20kHz) Class-D -10 -20 -30 PSRR (dB) -40 FFT (dB) +0 VDD =12V Ci=1µF fin=19kHz&20kHz RL=8Ω PO=1W AV=36dB AUX-0025 Class-D -20 10k 20k 1k Frequency (Hz) -80 -40 -50 -60 -70 -100 -80 -120 -90 -140 50 100 1k Frequency (Hz) -100 10k 20k VRR: Ripple Voltage on VDD 20 PSRR vs. Frequency +0 -10 -20 +0 TTVTDD TTT=12V TTTTT -10 RL=10kΩ VRR=0.5Vrms AV=20dB VAROUT -60 -40 -50 -60 -70 -70 -80 -80 20 -90 VRR: Ripple Voltage on VDD 100 No load VRR=0.5Vrms LDO -30 -50 -90 10k 20k TTVTDD TTT=12V TTT -20 -40 -100 1k Frequency (Hz) PSRR vs. Frequency PSRR (dB) PSRR (dB) -30 100 1k Frequency (Hz) Copyright ANPEC Electronics Corp. Rev. A.6 - Sep., 2009 -100 20 10k 20k 9 VRR: Ripple Voltage on VDD 100 1k Frequency (Hz) 10k 20k www.anpec.com.tw APA3002 Typical Operating Characteristics (Cont.) THD+N vs. Output Power 10 10 VDD =12V Ci=1µF COUT=150µF RL=32Ω AV=10dB LPF=80kHz VAROUT 1 THD+N (%) 1 THD+N (%) THD+N vs. Frequency fin=20kHz fin=50Hz 0.1 VDD =12V Ci=1µF COUT=150µF RL=32Ω AV=10dB PO=14mW LPF=80kHz VAROUT 0.1 fin=1kHz 0.01 0 5m 10m 15m 20m 0.01 20 25m 30m 100 1k Frequency (Hz) Output Power (W) Crosstalk vs. Frequency 100µ RRV RDD =12V -10 -20 Crosstalk (dB) Noise vs. Frequency -30 -40 Ci=1µF COUT=150µF RL=32Ω AV=10dB PO=14mW LPF=80kHz VAROUT Output Noise Voltage (V) +0 -50 -60 Left channel to Right channel -70 Right channel to Left channel 10µ VDD =12V Ci=1µF COUT=150µF RL=32Ω AV=10dB A-weighting VAROUT -80 -90 20 100 1k Frequency (Hz) 1µ 20 10k 20k Frequency Response Gain +6 +5 +4 +260 +240 +220 +200 +180 +3 Phase +2 +160 +1 +140 +0 20 100 1k 10k Frequency (Hz) Copyright ANPEC Electronics Corp. Rev. A.6 - Sep., 2009 1 Phase (Degree) Gain (dB) +280 VDD =12V Ci=1µF COUT=150µF RL=32Ω AV=10dB PO=2mW VAROUT +7 10 THD+N (%) +8 100 1k Frequency (Hz) 10k 20k THD+N vs. Output Voltage +300 +10 +9 10k 20k 0.1 VDD =12V Ci=1µF COUT=150µF RL=10kΩ AV=10dB LPF=80kHz VAROUT fin=20kHz fin=50Hz 0.01 fin=1kHz 0.001 0 +120 200k 500m 1 1.5 2 2.5 Output Voltage (V) 10 www.anpec.com.tw APA3002 Typical Operating Characteristics (Cont.) THD+N vs. Frequency Crosstalk vs. Frequency 10 +0 TTTVTT T=12V TTT DD -20 VDD =12V Ci=1µF COUT=150µF RL=10kΩ AV=10dB VO=1.25V LPF=80kHz VAROUT 0.1 Crosstalk (dB) THD+N (%) 1 -40 -60 Ci=1µF COUT=150µF RL=10kΩ AV=10dB VO=1.25V LPF=80kHz VAROUT -80 0.01 Left channel to Right channel -100 Right channel to Left channel 0.001 20 100 1k Frequency (Hz) -120 20 10k 20k 100 Noise vs. Frequency 1k Frequency (Hz) 10k 20k Frequency Response 100µ +10 +230 Gain Gain (dB) +8 10µ VDD =12V Ci=1µF COUT=150µF RL=10kΩ AV=10dB A-Weighting VAROUT 1µ 20 100 +7 +6 +210 +200 +190 +180 Phase +170 +5 1k Frequency (Hz) +4 10 10k 20k Input Resistance vs. Gain +160 100 +150 200k 1k 10k Frequency (Hz) Supply Current vs. Output Power 1.2 160 VAROUT 140 1.0 120 Supply Current (A) Input Resistance (kΩ) +220 VDD =12V Ci=1µF COUT=150µF RL=10kΩ AV=10dB PO=0.18V VAROUT Phase (Degree) Output Noise Voltage (V) +9 100 80 60 0.8 0.6 RL=8Ω&33µH fin=1kHz Ci=1µF Mono AUX-0025 AES-17 (20kHz) VDD=12V VDD=14V VDD=8.5V 0.4 40 0.2 20 0 -60 -45 -30 -15 0 Gain (dB) Copyright ANPEC Electronics Corp. Rev. A.6 - Sep., 2009 15 00 30 11 2 4 6 8 Output Power (W) 10 12 www.anpec.com.tw APA3002 Typical Operating Characteristics (Cont.) Supply Current vs. Supply Voltage 30 No Load Supply Current (mA) 25 20 15 10 5 0 0 5 10 15 Supply Voltage (V) Copyright ANPEC Electronics Corp. Rev. A.6 - Sep., 2009 12 www.anpec.com.tw APA3002 Pin Description PIN I/O FUNCTION NO. NAME 1 SD I 2 RIN- I Shutdown mode control signal input. Pulling the voltage on SD below 0.8V makes the IC enter low-power shutdown mode with 10µA (typical) IDD. Right channel negative input. 3 RIN+ I Right channel positive input. 4 2.5VREF O 2.5V reference for analog circuits. 5 LIN+ I Left channel positive input. Left channel negative input. 6 LIN- I 7 LDOREF O 5V reference output (5V LDO), connect it to VREF pin. 8 VREF I Gain control section’s reference voltage input. 9 VARDIFF I Input pin to set the difference in gain between the VAROUT and Class-D outputs by using the DC voltage. Connect this pin to the ground or LDOREF when the VAROUT is not used. 10 VARMAX I Input pin to set the maximum gain of VAROUT by using the DC voltage. Connect this pin to ground or LDOREF directly when the VAROUT is not used. 11 VOLUME 1 Input pin to set the gain of VAROUT and Class-D outputs by using the DC voltage. - Ground for gain control circuitry. Connect to AGND. If using a DAC to control the volume, connect the DAC ground to this terminal. 12 REFGND 13 LBS- 14,15,22 ,23 LPVDD - Power supply for left channel H-bridge. 16,17 LOUT- O Class-D left channel negative output. 18,19 LPGND - Power ground for left channel H-bridge. 20,21 LOUT+ O Class-D left channel positive output. 24 LBS+ I/O Left channel bootstrap power input for negative high-side MOSFET. I/O Left channel bootstrap power input for positive high-side MOSFET. 25 LCLAMP - Left channel internal voltage supply output for bootstrap capacitor. 26,30 AGND - Analog ground. 27 ROSC I/O Voltage of ROSC pin equal 0.125VDD, current setting resistor for internal ramp generator. 28 COSC I/O Charge/Discharge capacitor for generating triangle wave. 29 5VLDO O Internal 5V regulator output for external headphone driver used. 31 LVAROUT O Left channel variable audio output, for external headphone driver. 32 RVAROUT O Right channel variable audio output, for external headphone driver. 33 AVDD - Analog power supply (8.5 to 14V). 34 MODE I Control pin for amplifier operation. A logic high places the amplifier in variable output mode, and the Class-D output will disable; a logic low places the amplifier in variable output mode (line-level output for external amplifier) and stereo Class-D outputs. 35 MODEOUT O Inverse output of MODE pin, this pin can control the external headphone driver’s (APA4801) mute pin for changing operation from speaker operation to headphone operation. Leave this pin unconnected when the external headphone driver is not in using. 36 RCLAMP - Right channel internal voltage supply output for bootstrap capacitor. 37 RBS+ 38,39,46 ,47 RPVDD - Power supply for right channel H-bridge. 40,41 ROUT+ O Class-D right channel positive output. 42,43 RPGND - Power ground for right channel H-bridge. 44,45 ROUT- O Class-D right channel negative output. 48 RBS- I/O Right channel bootstrap voltage input for positive high-side MOSFET. I/O Right channel bootstrap voltage input for negative high-side MOSFET. Copyright ANPEC Electronics Corp. Rev. A.6 - Sep., 2009 13 www.anpec.com.tw APA3002 Block Diagram RCLAMP RBSRPVDD VOLTAGE CLAMP GEN. ROUT- Gate Drive RIN- RPGND RBS+ RPVDD De-glitch & Modulation Logic Gain Adj. RIN+ ROUT+ Gate Drive RPGND Gain Adj. 2.5VREF Over-Current Protection RVAROUT ROSC RAMP GEN. COSC VREF Biases & Reference Startup protection logic AVDD 5VLDO ok AGND VARDIFF VARMAX VOLUME Thermal Shutdown AVDD ok Gain Control REFGND SD 5VLDO 5VLDO TTL Input Buffer Gain Adj. LDOREF LCLAMP LBS- VOLTAGE CLAMP GEN. LPVDD LVAROUT Gate Drive LIN- LPGND LBS+ LPVDD De-glitch & Modulation Logic Gain Adj. LOUT- LIN+ Gate Drive LOUT+ LPGND Copyright ANPEC Electronics Corp. Rev. A.6 - Sep., 2009 14 www.anpec.com.tw APA3002 Operating Mode Selection Table MODE SD Operating mode H L H L H H Shutdown mode Class-D operation Class-D disable, VAROUT output. Class-D DC Volume Control Table GAIN Voltage range (% of VVREF) Increasing VVOLUME Decreasing VVOLMUE (dB) (%) (%) -75 0 -4.5 0 -2.9 -40 4.5 -6.7 2.9 -5.1 -37.5 6.7 -8.9 5.1 -7.2 -35 8.9 -11.1 7.2 -9.4 -32.4 11.1 -13.3 9.4 -11.6 -29.9 13.3 -15.5 11.6 -13.8 -27.4 15.5 -17.7 13.8 -16.0 -24.8 17.7 -19.9 16.0 -18.2 -22.3 19.9 -22.1 18.2 -20.4 -19.8 22.1 -24.3 20.4 -22.6 -17.2 24.3 -26.5 22.6 -24.8 -14.7 26.5 -28.7 24.8 -27.0 -12.2 28.7 -30.9 27.0 -29.1 -9.6 30.9 -33.1 29.1 -31.3 -7.1 33.1 -35.3 31.3 -33.5 -4.6 35.3 -37.5 33.5 -35.7 -2 37.5 -39.7 35.7 -37.9 0.5 39.7 -41.9 37.9 -40.1 3.1 41.9 -44.1 40.1 -42.3 5.6 44.1 -46.4 42.3 -44.5 8.1 46.4 -48.6 44.5 -46.7 10.7 48.6 -50.8 46.7 -48.9 13.2 50.8 -53 48.9 -51.0 15.7 53 -55.2 51.0 -53.2 18.3 55.2 -57.4 53.2 -55.4 20.8 57.4 -59.6 55.4 -57.6 23.3 59.6 -61.8 57.6 -59.8 25.9 61.8 -64 59.8 -62.0 28.4 64 -66.2 62.0 -64.2 30.9 66.2 -68.4 64.2 -66.4 33.5 68.4 -70.6 66.4 -68.4 36 >70.6 Copyright ANPEC Electronics Corp. Rev. A.6 - Sep., 2009 >68.6 15 www.anpec.com.tw APA3002 VAROUT VOLUME Control Table GAIN Voltage range (% of V VREF) Increasing V VOLUME Decreasing V VOLMUE (dB) (%) (%) -66 0 -4.5 0 -2.9 -56 4.5 -6.7 2.9 -5.1 -53.5 6.7 -8.9 5.1 -7.2 -50.9 8.9 -11.1 7.2 -9.4 -48.4 11.1 -13.3 9.4 -11.6 -45.9 13.3 -15.5 11.6 -13.8 -43.3 15.5 -17.7 13.8 -16.0 -40.8 17.7 -19.9 16.0 -18.2 -38.3 19.9 -22.1 18.2 -20.4 -35.7 22.1 -24.3 20.4 -22.6 -33.2 24.3 -26.5 22.6 -24.8 -30.7 26.5 -28.7 24.8 -27.0 -28.1 28.7 -30.9 27.0 -29.1 -25.6 30.9 -33.1 29.1 -31.3 -23.1 33.1 -35.3 31.3 -33.5 -20.5 35.3 -37.5 33.5 -35.7 -18.0 37.5 -39.7 35.7 -37.9 -15.5 39.7 -41.9 37.9 -40.1 -13.0 41.9 -44.1 40.1 -42.3 -10.4 44.1 -46.4 42.3 -44.5 -7.9 46.4 -48.6 44.5 -46.7 -5.3 48.6 -50.8 46.7 -48.9 -2.8 50.8 -53 48.9 -51.0 -0.3 53 -55.2 51.0 -53.2 2.3 55.2 -57.4 53.2 -55.4 4.8 57.4 -59.6 55.4 -57.6 7.3 59.6 -61.8 57.6 -59.8 9.9 61.8 -64 59.8 -62.0 12.4 64 -66.2 62.0 -64.2 14.9 66.2 -68.4 64.2 -66.4 17.5 68.4 -70.6 66.4 -68.4 20.0 >70.6 >68.6 Copyright ANPEC Electronics Corp. Rev. A.6 - Sep., 2009 16 www.anpec.com.tw APA3002 Typical Application Circuits Right channel SPEAKER 1nF 1nF Bead Bead VDD CBS(R-) VDD 10µF CBS(R+) 10nF 10nF 1µF 1µF RIN+ CB 1µF 37 RPVDD RBS+ 38 40 39 ROUT+ ROUT+ 41 RPGND 42 RPGND 43 ROUT44 45 ROUT- RPVDD 46 RPVDD 33 AVDD 32 31 LVAROUT 30 AGND 29 5VLDO TOP VIEW APA3002 ROSC 11 26 AGND REFGND 12 25 LCLAMP CBS(L-) 10nF VDD 10µF RVAROUT LVAROUT 0.1µF 5V COSC COSC 220pF ROSC 120kΩ 24 1µF CCLAMP(L) LBS+ LPVDD LOUT+ LPVDD LOUT+ LPGND LBS- RVARMAX 23 27 22 10 VOLUME 21 28 20 9 19 VARDIFF 18 8 MODE 0.1µF RVAROUT 6 7 MODEOUT VDD 5 17 50kΩ RVOLUME 4 MODEOUT VREF VARMAX 50kΩ MODE LPGND RVARDIFF 34 16 50kΩ LDOREF 3 LOUT- Ci(LIN-) LIN- 35 LOUT- Ci(LIN+) LIN+ 2 15 LIN- 2.5VREF 1µF 1µF RCLAMP 36 14 1µF RIN- CCLAMP(R) 1 LPVDD Ci(RIN-) Ci(RIN+) 47 RBS48 SD 13 SHUTDOWN LPVDD RIN- RPVDD 0.1µF 0.1µF 0.1µF 0.1µF 10nF 10µF VDD Bead 1nF Left channel CBS(L+) AGnd PGnd Bead 1nF SPEAKER ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright ANPEC Electronics Corp. Rev. A.6 - Sep., 2009 17 www.anpec.com.tw APA3002 Typical Application Circuits (Cont.) Right channel SPEAKER 1nF Bead 10µF VDD VDD 10nF 50kΩ REFGND 12 21 LPVDD 22 LPVDD 23 LBS+ 24 LOUT+ LPGND 17 18 19 LOUT+ 20 CBS(L-) 0.1µF LPGND LOUT- 14 LPVDD 15 LOUT16 LBS- LPVDD 13 25 MUTE OUTA VSS Sleeve Jack 10µF 120kΩ ROSC LCLAMP 1kΩ 1µF 220µF 4.7µF 1µF CCLAMP(L) 0.1µF 10nF VDD Tip APA4801 VDD 28 27 ROSC 26 AGND VOLUME 11 RVARMAX RVOLUME COSC 220pF COSC VARDIFF 9 VARMAX 10 50kΩ 1kΩ Headphone OUTB TOP VIEW APA3002 6 LDOREF 7 VREF 8 RVARDIFF 50kΩ 0.1µF RVAROUT 32 LVAROUT 31 0.1µF 30 AGND 29 5VLDO Ring Pin 1µF INPUTA Ci(LIN+) CB 1µF 1µF LIN+ 5 Ci(LIN-) 1µF LIN- 35 MODE VDD 34 AVDD 10µF 33 3 2.5VREF 4 Control 220µF MODEOUT BIAS Ci(RIN+) 120kΩ 36 RCLAMP 1 Ci(RIN-) 1µF RIN2 1µF RIN+ CCLAMP(R) 1µF INPUTB RBS+ ROUT+ ROUT+ RPGND RPGND ROUT- ROUT- RPVDD 46 45 44 43 42 41 RBS- 48 RPVDD 47 LIN- SD 40 RPVDD 39 RPVDD 38 0.1µF 0.1µF RIN- SHUTDOWN CBS(R+) 10nF 37 CBS(R-) 1nF Bead 10nF 10µF VDD CBS(L+) AGnd Bead Bead 1nF 1nF Left channel PGnd SPEAKER ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright ANPEC Electronics Corp. Rev. A.6 - Sep., 2009 18 www.anpec.com.tw APA3002 Application Information Class-D Operation Square Wave Into the Speaker Output = 0V To apply the square wave into the speaker may cause the voice coil of speaker jumps out the air gap and defaces the OUT+ voice coil. However, this depends on if the amplitude of square wave is high enough and the bandwidth of speaker OUT- is higher than the square wave’s frequency. For 250kHz switching frequency, this is not an issue for the OUT (OUT+)-(OUT-) speaker because the frequency is beyond the audio band, and can’t significantly move the voice coil, as cone move- IOUT ment is proportional to 1/f2 for frequency out of audio band. Output > 0V OUT+ Input Resistor (Ri) OUT- In order to achieve the 32 steps gain setting, the Ri varies the input resistance network (Ri & Rf) of amplifier. The input resistor’s range from the smallest to the maximum is about 15 times, therefore, the input high-pass filter’s OUT (OUT+)-(OUT-) IOUT low cutoff frequency will change 15 times from low to high. The cutoff frequency can be calculated by equation Output < 0V 1. OUT+ Input Capacitor (Ci) In the typical application, an input capacitor, Ci, is required OUT- to allow the amplifier to bias the input signal to the proper DC level for optimum operation. In this case, Ci and the minimum input impedance Ri form a high-pass filter with (OUT+)-(OUT-) OUT the corner frequency is determined in the following equation: 1 fC(highpass) = (1) 2πRiCi IOUT Figure1. APA3002 Output Waveform (Voltage & Current) The value of Ci must be considered carefully because The APA3002 modulation scheme is shown in Figure 1, it directly affects the low frequency performance of the circuit. Consider the example, where Ri is 10kΩ and the outputs OUT+ and OUT- are in phase with each other when no input signals. When output > 0V, the duty cycle the specification calls for a flat bass response down to 40Hz. The equation is reconfigured as below: of OUT+ is greater than 50% and OUT- is less than 50%; on the contrary, when output <0V, the duty cycle of OUT+ Ci = is less than 50% and OUT- is greater than 50%. This method reduces the switching current across the load 1 (2) 2πRifc When the input resistance variation is considered, the Ci is 0.40µF, so a value in the range of 0.47µF to 1.0µF and reduces the I2R loss in the load that improves the amplifier’s efficiency. would be chosen. A further consideration for this capacitor is the leakage path from the input source This modulation scheme has very short pulses across the load. This makes the small ripple current and very through the input network (Ri + Rf, Ci) to the load. little loss on the load, and the LC filter can be eliminated in most applications. Adding the LC filter can increase the This leakage current creates a DC offset voltage at the input to the amplifier that reduces useful headroom, efficiency by filter the ripple current. Copyright ANPEC Electronics Corp. Rev. A.6 - Sep., 2009 19 www.anpec.com.tw APA3002 Application Information (Cont.) Input Capacitor (Ci) (Cont.) CLAMP Capacitor (CCLAMP) especially in high gain applications. For this reason, a These capacitors are regulated the clamp voltage of N- low-leakage tantalum or ceramic capacitor is the best choice. When polarized capacitors are used, the positive channel power MOSFET’s gate voltage, ensuring the maximum gate-to-source voltage of the MOSFET not to side of the capacitor should face the amplifier input in most applications because the DC level of the amplifiers’inputs exceed. 1µF/25V capacitors are recommended. Power Supply Decoupling (Cs) is held at 2.5VREF. Please note that it is important to confirm the capacitor polarity in the application. The APA3002 is a high-performance CMOS audio amplifier COSC & ROSC that requires adequate power supply decoupling to ensure the output total harmonic distortion (THD+N) is The Class-D amplifier’s switching frequency is determined by the component that connected to ROSC (pin) as low as possible. Power supply decoupling also prevents the oscillations being caused by long lead and COSC (pin). The frequency can be calculated by the following equation: length between the amplifier and the speaker. The optimum decoupling is achieved by using two dif- fosc = ferent types of capacitors that target on different types of noise on the power supply leads. For higher frequency 6.6 (3) RoscCosc transients, spikes, or digital hash on the line, a good low equivalent-series-resistance (ESR) ceramic capacitor, BS+ &BS- Capacitor (CBS) typically is 0.1µF which is placed as close as possible to the device VDD lead to achieve the best performance. Since the Full-bridge output stages are only using the Nchannel power MOSFET, the high-side MOSFET’s driver needs bootstrap circuit to turn on the high side power For filtering lower frequency noise signals, a large aluminum electrolytic capacitor of 10µF or greater placed near MOSFET correctly. A 10nF/35V ceramic capacitor is recommended. the audio power amplifier is recommended. The bootstrap capacitors are like floating power supply Ferrite Bead Selection for high side N-channel power MOSFET gate driver. The bootstrap capacitors hold the gate-to-source voltage high If the traces from the APA3002 to speaker are short, the ferrite bead filters can reduce the high frequency radiated enough to keep the high-side N-channel power MOSFET turn-on at high side switching cycle. At the high-side turn- to meet the FCC & CE’s requirements. on cycle, the voltage of bootstrap capacitors will decrease through the leakage path. The bootstrap voltage can de- A ferrite that has very low impedance at low frequencies and high impedance at high frequencies (above 1 MHz) is recommended. crease below the minimum Vgs that required to keep the high-side N-channel power MOSFET turn-on, if driving Output LC Filter into heavy clipping with a less than 50Hz sine wave. When this occurs, the output power MOSFET becomes source- If the traces from the APA3002 to speaker are short, it doesn’t require output filter for FCC & CE standard. Fig- follower and the output drops from VDD to approximately Vclamp. ure 2 is an example for adding the LC filter, it’s recommended for the situation that the trace from amplifier to Driving a square wave at low frequencies is not a design consideration for majority application, so the 10nf boot- speaker is too long, and needed to eliminate the radiated emission or EMI. strap capacitor is recommended. If the low frequency is a concern, please increase the bootstrap capacitor value to hold the gate voltage for a longer period and the voltage drop will not occur. Copyright ANPEC Electronics Corp. Rev. A.6 - Sep., 2009 20 www.anpec.com.tw APA3002 Application Information (Cont.) If a DAC controls the Class-D gain is used, VREF and Output LC Filter (Cont.) REFGND should be connected to the reference voltage for the DAC and the GND terminal of the DAC respectively. For the DAC application, LDOREF would be left unconnected. The reference voltage of the DAC provides OUT+ 33µH the reference to the internal gain circuitry through the VREF input and any fluctuations in the DAC output voltage 0.1µF will not affect the Class-D gain. 0.47µF OUT- 0.1µF 8 Ω 33µH The percentages in the “Increasing VVOLUME” of table should be used for setting the voltages of the DAC when the voltage on the VOLUME pin is increased. The percentages in the “ decreasing VVOLUME” of the table should be used for the DAC voltages when decreasing the voltage on the VOLUME pin. Two lookup tables should be used Figure 2. LC Output Filter in software to control the gain based on an increase or decrease in the desired system volume. DC Volume Decreasing VVOLUME If using an analog potentiometer to control the gain, it Class-D Gain (dB) 3.1 should be connected between VREF and REFGND. VREF can be connected to LDODREF or an external voltage source, if desired. The table of “Increasing VVOLUME” and “Decreasing VVOLUME” in “Class-D DC Volume Control 0.5 Increasing VVOLUME Table” should be used to determine the point at which gain changes depending on the direction that the poten- -2.0 tiometer is turned. If the voltage on the center tap of the potentiometer is increasing, the table “Increasing VVOLUME” (39.7% x VVREF) 1.90 (37.9% x V VREF ) 1.99 2.01 (40.1% x VVREF) 2.12 (41.9% x V VREF) at “Class-D DC Volume Control Table” should be referenced to determine the trip points. If the voltage is Volume’s Voltage (V) decreasing, the trip points in the ”Decreasing VVOLUME” should be referenced. Figure 3. DC Volume Control Operation (VVREF=5V) The Class-D’s gain is determined by the voltage of VOL- The trip point, where the gain actually changes, is various depending on whether the voltage on the VOLUME pin is UME control pin. “Class-D DC Volume Control Table” lists the gain in Class-D that is determined by the VOLUME increasing or decreasing as a result of hysteresis about each trip point. The hysteresis ensures that the gain con- pin’s voltage (VVOLUME) in reference to the VREF’s voltage (V VREF). The maximum voltage of VOLUME should not trol is monotonic and does not oscillate from one gain step to another. A pictorial representation of the volume exceed the VREF’s voltage. If the resistor divider fixed the Class-D’s gain is used, control can be found in Figure 3. The graph focuses on three gain steps with the trip points defined in the table and then the resistor divider values to center the voltage between the two percentage points of the table’s “Increasing VVOLUME” and ”Decreasing VVOLUME” of “ClassD DC Volume Control Table” for Class-D gain. The dotted column “Increasing VVOLUME” need to be calculated, see figure 3. The resistor can be connected between VREF lines represent the hysteresis about each gain step. and REFGND, and then VREF and LDOREF are connected together. Copyright ANPEC Electronics Corp. Rev. A.6 - Sep., 2009 21 www.anpec.com.tw APA3002 Application Information (Cont.) LDO Operation DC Volume VVARDIFF(V) The 5VLOD terminal is the output of an internal-generated 5V power supply that is used for oscillator, pream- VVARMAX(V) plifier and DC volume control circuitry. The regulator can be powered the external headphone amplifier like the - VVOLUMEVVARDIFF + VVOLUME(V) YES Is VVARMAX>(VVOLUMEVVARDIFF) VAROUT s VOLUME(V) = VVOLUME(V)-V VARDIFF(V) APA4801, or other circuitry, up to the current limit of 5VLDO pin (on specification table). With 10µF & 0.1µF capacitors NO connected to the terminal are recommended if powered by the APA4801; however, if there is no other larger loading, VAROUT s VOLUME(V) = VVARMAX(V) 1µF and 0.1µF are sufficient enough. Figure 4. VAROUT Volume Control Flow Shutdown Function In order to reduce power consumption when not in use, Three pins, VOLUME, VARMAX, and VARDIFF, determine the VAROUT’s gain. The figure 4 shows the VAROUT vol- the APA3002 contains a shutdown function to externally turn off the amplifier bias circuitry. This shutdown feature ume control flow. All the values are DC voltage, and the VAROUT channel gain can be determined by consulting the turns the amplifier off when logic low is placed on the SD pin for the APA3002. The trigger point between a logic table “VAROUT VOLUME Control Table”. high and logic low level is typically 1.2V. It will be the best to switch between ground and the supply voltage VDD to VARMAX The VARMAX limits the maximum gain of VAROUT chan- provide maximum device performance. By switching the SD pin to low level, the amplifier enters a low-consump- nels to avoid the un-comfortable listening of headphone. tion-current state, I DD for the APA3002 is in shutdown mode. Under normal operating, APA3002’s SD pin should VARDIFF To avoid the uncomfortable listening when headphone is plugging, the VARDIFF sets the different gain between pull to a high level to keep the IC out of the shutdown mode. The SD pin should be tied to a definite voltage to the Class-D and VAROUT channels. At initial (VVARDIFF=0V), the difference gain between the Class-D and VAROUT is avoid unwanted state change. Thermal Pad Consideration 16dB. W hen voltage of VARDIFF is increasing, the VAROUT’s gain decreases. The thermal pad must be connected to the ground. The package with thermal pad of the APA3002 requires special attention on thermal design. If the thermal design MODE Operation The mode controls the output mode of the APA3002, a logic “HIGH” will disable the Class-D outputs; a logic issues are not properly addressed, the APA3002 will go into thermal shutdown. The thermal pad on the bottom of “LOW” will enable the Class-D outputs. This pin can connect to the switch on the headphone jack to disable the the APA3002 should be soldered down to a copper pad on the circuit board. Heat can be conducted away from Class-D outputs when headphone plug is inserted. The “Typical Application Circuit “ shows an example for this the thermal pad through the copper plane to ambient. If the copper plane is not on the top surface of the circuit application. board, 10 to 16 vias of 15 mil or smaller in diameter should be used to thermally couple the thermal pad to the bot- MODE_OUT Operation tom plane. For good thermal conduction, the vias must be plated through and solder filled. The copper plane The MODE_OUT is the inverting output of MODE, and it controls the external headphone amplifier’s SD pin (like the APA4801) for switching the Speaker mode or used to conduct heat away from the thermal pad should headphone. Copyright ANPEC Electronics Corp. Rev. A.6 - Sep., 2009 22 www.anpec.com.tw APA3002 Application Information (Cont.) Thermal Pad Consideration (Cont.) be as large as practical. If the ambient temperature is higher than 25°C, a larger copper plane or forced-air cooling will be required to keep the APA3002 junction temperature below the thermal shutdown temperature (150°C). In higher ambient temperature, higher airflow rate and/or larger copper area will be required to keep the IC out of thermal shutdown. See TQFP7x7-48 thermal pad layout recommendation. 0.28mm 5.5mm Via diameter =0.3mm X16 1.7mm 0.5mm 6.5mm 4.5mm Ground plane for Thermal PAD Exposed for thermal PAD connected Figure 5. TQFP7x7-48 thermal pad layout recommendation Copyright ANPEC Electronics Corp. Rev. A.6 - Sep., 2009 23 www.anpec.com.tw APA3002 Package Information TQFN7x7-48 D E A b Pin 1 A1 D2 A3 L K E2 Pin 1 Corner e S Y M B O L TQFN7x7-48 MILLIMETERS INCHES MIN. MAX. MIN. MAX. A 0.70 0.80 0.028 0.031 A1 0.00 0.05 0.000 0.002 0.30 0.007 0.012 0.280 A3 b 0.20 REF 0.18 0.008 REF D 6.90 7.10 0.272 D2 5.50 5.80 0.217 0.228 E 6.90 7.10 0.272 0.280 E2 5.50 5.80 0.217 e 0.50 BSC L 0.35 K 0.20 0.228 0.020 BSC 0.014 0.45 0.018 0.008 Note : 1. Followed from JEDEC MO-220 WKKD-4. Copyright ANPEC Electronics Corp. Rev. A.6 - Sep., 2009 24 www.anpec.com.tw APA3002 Package Information TQ TQFP7x7-48P D D1 E A e 0.25 c A1 b E1 EXPOSED PAD A2 E2 D2 GAUGE PLANE SEATING PLANE S Y M B O L 0 L TQFP7x7-48P MILLIMETERS MIN. INCHES MIN. MAX. A MAX. 0.047 1.20 A1 0.05 0.15 0.002 0.006 A2 0.95 1.05 0.037 0.041 b 0.17 0.27 0.007 0.011 c 0.09 0.20 0.004 0.008 D 8.80 9.20 0.346 0.362 D1 6.90 7.10 0.272 0.280 D2 3.00 4.50 0.118 0.177 E 8.80 9.20 0.346 0.362 E1 6.90 7.10 0.272 0.280 E2 3.00 4.50 0.118 0.177 e L 0 0.50 BSC 0.45 0o 0.020 BSC 0.75 7o 0.018 0.030 0o 7o Note : 1. Followed from JEDEC MS-026 ABC. 2. Dimension "D1" and "E1" do not include mold protrusions. Allowable protrusions is 0.25 mm per side. "D1" and "E1" are maximun plasticbody size dimensions including mold mismatch. Copyright ANPEC Electronics Corp. Rev. A.6 - Sep., 2009 25 www.anpec.com.tw APA3002 Carrier Tape & Reel Dimensions P0 P2 P1 A B0 W F E1 OD0 K0 A0 A OD1 B B T SECTION A-A SECTION B-B H A d T1 Application A H 330.0±2.00 50 MIN. P0 P1 TQFP7x7-48P 4.0±0.10 12.0±0.10 A H Application 330.0±2.00 50 MIN. P0 P1 TQFN7x7-48 4.0±0.10 T1 C 16.4+2.00 13.0+0.50 -0.00 -0.20 D 1.5 MIN. 20.2 MIN. W E1 16.0±0.30 1.75±0.10 F 7.5±0.10 P2 D0 D1 T A0 B0 K0 2.0±0.10 1.5+0.10 -0.00 1.5 MIN. 0.6+0.00 -0.40 9.4±0.20 9.4±0.20 1.8±0.20 T1 C d D W E1 F 1.5 MIN. 20.2 MIN. 16.4+2.00 13.0+0.50 -0.00 -0.20 12.0±0.10 d P2 D0 2.0±0.10 1.5+0.10 -0.00 16.0±0.30 1.75±0.10 5.5±0.10 D1 T A0 B0 K0 1.5 MIN. 0.6+0.00 -0.40 7.30±0.20 7.30±0.20 1.3±0.20 (mm) Devices Per Unit Package Type Unit Quantity TQFP7x7-48P Tape & Reel 2500 TQFN7x7-48 Tape & Reel 2500 Copyright ANPEC Electronics Corp. Rev. A.6 - Sep., 2009 26 www.anpec.com.tw APA3002 Taping Direction Information TQFN7x7-48 USER DIRECTION OF FEED TQFP7x7-48P USER DIRECTION OF FEED Copyright ANPEC Electronics Corp. Rev. A.6 - Sep., 2009 27 www.anpec.com.tw APA3002 Classification Profile Classification Reflow Profiles Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly 100 °C 150 °C 60-120 seconds 150 °C 200 °C 60-120 seconds 3 °C/second max. 3°C/second max. 183 °C 60-150 seconds 217 °C 60-150 seconds See Classification Temp in table 1 See Classification Temp in table 2 Time (tP)** within 5°C of the specified classification temperature (Tc) 20** seconds 30** seconds Average ramp-down rate (Tp to Tsmax) 6 °C/second max. 6 °C/second max. 6 minutes max. 8 minutes max. Preheat & Soak Temperature min (Tsmin) Temperature max (Tsmax) Time (Tsmin to Tsmax) (ts) Average ramp-up rate (Tsmax to TP) Liquidous temperature (TL) Time at liquidous (tL) Peak package body Temperature (Tp)* Time 25°C to peak temperature * Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum. ** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum. Copyright ANPEC Electronics Corp. Rev. A.6 - Sep., 2009 28 www.anpec.com.tw APA3002 Classification Reflow Profiles Table 1. SnPb Eutectic Process – Classification Temperatures (Tc) 3 Package Thickness <2.5 mm Volume mm <350 235 °C Volume mm ≥350 220 °C ≥2.5 mm 220 °C 220 °C 3 Table 2. Pb-free Process – Classification Temperatures (Tc) Package Thickness <1.6 mm 1.6 mm – 2.5 mm ≥2.5 mm Volume mm <350 260 °C 260 °C 250 °C 3 Volume mm 350-2000 260 °C 250 °C 245 °C 3 Volume mm >2000 260 °C 245 °C 245 °C 3 Reliability Test Program Test item SOLDERABILITY HOLT PCT TCT HBM MM Latch-Up Method JESD-22, B102 JESD-22, A108 JESD-22, A102 JESD-22, A104 MIL-STD-883-3015.7 JESD-22, A115 JESD 78 Description 5 Sec, 245°C 1000 Hrs, Bias @ 125°C 168 Hrs, 100%RH, 2atm, 121°C 500 Cycles, -65°C~150°C VHBM≧2KV VMM≧200V 10ms, 1tr≧100mA Customer Service Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 2F, No. 11, Lane 218, Sec 2 Jhongsing Rd., Sindian City, Taipei County 23146, Taiwan Tel : 886-2-2910-3838 Fax : 886-2-2917-3838 Copyright ANPEC Electronics Corp. Rev. A.6 - Sep., 2009 29 www.anpec.com.tw