APA2036/APA2036A Stereo 2.6W Audio Power Amplifier Features • • • • • • • • • General Description The APA2036/APA2036A is a stereo audio power ampli- Operating Voltage: 3.0 ~ 5.5V Low Shutdown Current – IDD= 0.5µA (Typical) at VDD= 5V Selectable Bridge-Tied Load (BTL) or Singled- fier in a TQFN4x4-16 or TQFN3x3-16 (APA2036A) package. To simplify the audio system design in notebook computer applications, the APA2036/APA2036A combines a stereo bridge-tied mode for speaker drive and a stereo Ended (SE) Operation Output Power (BTL) at 1% THD+N, VDD= 5V – 2.4W at RL = 3Ω – 2.0W at RL = 4Ω – 1.3W at RL = 8Ω Output Power (SE) at 1% THD+N, VDD= 5V – 160mW at RL = 16Ω – 85mW at RL = 32Ω Depop Circuitry Integrated Thermal and Over-Current Protections Short Circuit Protection Space Saving Packaging – 4mmx4mm 16-Lead Thin QFN Package (TQFN4X4-16) single-end mode for headphone drive into a single chip, where both modes are easily switched by the SE/BTL input control pin signal. When the APA2036/APA2036A is in the BTL mode with 5V supply voltage, it is capable of delivering 2.4W/2.0W/1.3W of continuous output power per channel into 3Ω/4Ω/8Ω load (Speaker) with less than 1% THD+N respectively. When the APA2036/APA2036A operates in the single-ended mode, it is capable of delivering 160mW/85mW of continuous output power per channel into 16Ω/32Ω load (Headphone). The APA2036/APA2036A also serves low-voltage applications well. The APA2036/APA2036A, with 3.3V supply voltage, pro- – 3mmx3mm 16-Lead Thin QFN Package • vides 900mW (at 1% THD+N) per channel into 4Ω load. Both of the depop circuitry and the thermal shutdown pro- (TQFN3X3-16) Lead Free and Green Devices Available tection circuitry are integrated in the APA2036/APA2036A. (RoHS Compliant) The depop function reduces pops and clicks noise dur- Applications ing power on/off and enable/shutdown processes. The • • • thermal protection protects the chip from being destroyed by over-temperature failure. For power sensitive Handsets applications, the APA2036/APA2036A also features a shutdown function which reduces the supply current only Portable Multimedia Devices Notebooks 0.5µA (typical). Simplified Application Circuit L-CH Input LINN THD+N vs. Output Power 10 LOUTP LOUTN R-CH Input RINN THD+N (%) LBYPASS SE-BTL Signal ROUTP 1 VDD=5V RL=4Ω Ci=1µF BW<80kHz BTL mode fin=20kHz 0.1 RBYPASS fin=20Hz fin=1kHz ROUTN 0.0110m 100m 1 2 4 Output Power (W) ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright ANPEC Electronics Corp. Rev. A.3 - Jun., 2013 1 www.anpec.com.tw APA2036/APA2036A Ordering and Marking Information Package Code QB : TQFN4x4-16 QB : TQFN3x3-16 Operating Ambient Temperature Range I : - 40 to 85 oC Handling Code TR : Tape & Reel Assembly Material G : Halogen and Lead Free Device APA2036 APA2036A Assembly Material Handling Code Temperature Range Package Code APA2036 QB : XXXXX - Date Code APA2036 XXXXX APA 2036A XXXXX APA2036A QB : XXXXX - Date Code Note : ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD020C for MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by weight). 8 LIN- ROUT+ 14 TQFN4x4-16 9 GND 7 LOUT+ 6 VDD 5 LOUT- GND 1 GND 4 SHUTDOWN 3 SE-BTL 2 10 LBYPASS ROUT- 16 5 LOUT- GND 1 APA2036A TOP VIEW VDD 15 6 VDD ROUT- 16 8 LIN- GND 4 APA2036 TOP VIEW VDD 15 RIN- 13 7 LOUT+ SHUTDOWN 3 ROUT+ 14 SE-BTL 2 RIN- 13 11 GND 12 RBYPASS 9 GND 10 LBYPASS 11 GND 12 RBYPASS Pin Configuration TQFN3x3-16 = Thermal Pad (connected the Thermal Pad to the GND plane for better heat dissipation) Copyright ANPEC Electronics Corp. Rev. A.3 - Jun., 2013 2 www.anpec.com.tw APA2036/APA2036A Absolute Maximum Ratings Symbol VDD TA TJ (Note 1) Parameter Rating Unit -0.3 to 6 V Input Voltage (SE/BTL, SHUTDOWN, RINN, LINN, RBYPASS, LBYPASS) -0.3 to VDD+0.3 V Output Voltage (ROUTP, ROUTN, LOUTP, LOUTN) -0.3 to VDD+0.3 V Supply Voltage Operating Ambient Temperature Range Maximum Junction Temperature TSTG Storage Temperature Range TSDR Maximum Lead Soldering Temperature, 10 seconds PD Power Dissipation -40 to 85 ο 150 ο -65 to 150 ο 260 ο C C C C Internally Limited W Note1: Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Thermal Characteristics (Note 2,3) Symbol θJA θJC Parameter Thermal Resistance - Junction to Ambient Typical Value Unit (Note 2) TQFN4x4-16 TQFN3x3-16 45 60 Junction-to-Case Resistance in Free Air (Note 3) o C/W 9 TQFN4x4-16 12 TQFN3x3-16 Note 2 : θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. The thermal pad of TQFN4x4-16 and TQFN3x3-16 is soldered directly on the PCB. Note 3 : The case temperature is measured at the center of the thermal pad on the underside of the TQFN4x4-16 and TQFN3x3-16 packages. Recommended Operating Conditions Symbol VDD VIH Parameter Supply Voltage High level threshold voltage Range Unit 3.0 ~ 5.5 V SHUTDOWN 0.4 VDD ~ VDD V SE/BTL 0.8 VDD ~ VDD V 0 ~ 1.0 V 0 ~ 0.6VDD V SHUTDOWN VIL Low level threshold voltage VIC Common mode input voltage ~ VDD-0.5 TA Ambient Temperature Range -40 ~ 85 o -40 ~ 125 o SE/BTL V C TJ Junction Temperature Range RL Speaker Resistance 3~ Ω RL Headphone Resistance 16 ~ Ω Copyright ANPEC Electronics Corp. Rev. A.3 - Jun., 2013 3 C www.anpec.com.tw APA2036/APA2036A Electrical Characteristics Unless otherwise noted, these specifications apply over VDD=5V, VGND=0V, TA= -40 ~ 85OC, Typical values are at TA= 25OC Symbol Parameter VDD Supply Voltage IDD Supply Current Test Conditions APA2036/APA2036A Min. Typ. Max. 3 - 5.5 VSE/BTL=0V - 5.5 13.5 VSE/BTL=5V - 3 7.5 Unit V mA ISD Shutdown Current VSHUTDOWN=5V - 0.5 5 µA TSTART-UP Start-Up time from Shutdown CB=2.2µF - 700 - ms RL=3Ω - 2.4 - RL=4Ω - 2.0 - RL=8Ω 1.1 1.3 - RL=3Ω - 3.0 - RL=4Ω - 2.6 - RL=8Ω - 1.6 - RL=4Ω PO=1.3W - 0.06 - RL=8Ω PO=0.9W - 0.03 - BTL MODE, VDD=5V THD+N=1%, fin=1kHz PO Output Power W THD+N=10%, fin=1kHz Total Harmonic Distortion Pulse Noise fin=1kHz Power Supply Rejection Ratio RL=8Ω, fin=217Hz - 61 - dB Output Offset Voltage VIN=0V - 10 - mV Channel separation RL=8Ω, PO=0.9W, fin=1kHz - 100 - dB S/N Signal to Noise Ratio RL=8Ω, PO=1.1W, A_weighting - 93 - dB Vn Noise Output Voltage RL=8Ω - 22 - µV(rms) RL=16Ω - 160 - RL=32Ω 70 85 - RL=16Ω - 210 - RL=32Ω - 110 - RL=32Ω PO=60mW - 0.02 - % THD+N PSRR VOS Crosstalk % SE MODE, VDD=5V THD+N=1%, fin=1kHz PO Output Power mW THD+N=10%, fin=1kHz THD+N Total Harmonic Distortion Pulse Noise fin=1kHz PSRR Power Supply Rejection Ratio RL=32Ω, fin=217Hz - 60 - dB Output Offset Voltage VIN=0V - 10 - mV Crosstalk Channel Separation RL=32Ω, PO=60mW, fin=1kHz - 85 - dB S/N Signal to Noise Ratio RL=32Ω, PO=65mW, A_weighting - 100 - dB Vn Noise Output Voltage RL=32Ω - 8 - µV(rms) VOS Copyright ANPEC Electronics Corp. Rev. A.3 - Jun., 2013 4 www.anpec.com.tw APA2036/APA2036A Typical Operating Characteristics THD+N vs. Output Power THD+N (%) 1 THD+N vs. Output Power 10 VDD=5V RL=4Ω Ci=1µF BW<80kHz BTL mode 1 THD+N (%) 10 fin=20kHz fin=20Hz 0.1 VDD=5V RL=8Ω Ci=1µF BW<80kHz BTL mode fin=20kHz fin=20Hz 0.1 fin=1kHz 0.01 10m 100m Output Power (W) 1 fin=1kHz 2 0.01 10m 4 10 VDD=5V RL=16Ω Ci=1µF Cc=1000µF BW<80kHz SE mode 1 THD+N (%) THD+N (%) 1 fin=20Hz 0.1 fin=20kHz 0.1 VDD=5V RL=32Ω Ci=1µF CC=1000µF BW<80kHz SE mode 100m Output Power (W) 0.01 10m 300m VDD=3.3V RL=4Ω Ci=1µF BW<80kHz BTL mode 1 fin=20kHz fin=20Hz VDD=3.3V RL=8Ω Ci=1µF BW<80kHz BTL mode fin=20kHz 0.1 fin=1kHz 0.01 10m 100m fin=20Hz fin=1kHz 1 0.01 10m 2 Output Power (W) Copyright ANPEC Electronics Corp. Rev. A.3 - Jun., 2013 200m THD+N vs. Output Power 10 0.1 100m Output Power (W) THD+N (%) THD+N (%) 1 fin=20Hz fin=1kHz THD+N vs. Output Power 10 2 3 fin=20kHz fin=1kHz 0.01 10m 1 THD+N vs. Output Power THD+N vs. Output Power 10 100m Output Power (W) 5 100m Output Power (W) 1 www.anpec.com.tw APA2036/APA2036A Typical Operating Characteristics (Cont.) THD+N vs. Output Power VDD=3.3V RL=16Ω Ci=1µF CC=1000µF BW<80kHz SE mode THD+N (%) 1 THD+N vs. Output Power 10 1 fin=20Hz THD+N (%) 10 fin=20kHz 0.1 VDD=3.3V RL=32Ω Ci=1µF CC=1000µF BW<80kHz SE mode fin=20kHz 0.1 fin=20Hz fin=1kHz fin=1kHz 0.01 10m 20m 50m Output Power (W) 0.01 10m 100m 1 THD+N (%) THD+N (%) 10 VDD=5V RL=4Ω Ci=1µF 1 PO=1.3W BW<80kHz BTL mode Left Channel Right Channel 0.01 0.001 VDD=5V RL=8Ω Ci=1µF PO=0.9W BW<80kHz BTL mode 0.1 Right Channel Left Channel 0.01 20 100 1k Frequency (Hz) 0.001 10k 20k 20 1 THD+N (%) THD+N (%) 10 VDD=5V RL=16Ω Ci=1µF CC=1000µF PO=110mW BW<80kHz SE mode 1 0.1 Right Channel 0.01 0.001 20 1k Frequency (Hz) Copyright ANPEC Electronics Corp. Rev. A.3 - Jun., 2013 1k Frequency (Hz) 10k 20k 0.1 VDD=5V RL=32Ω Ci=1µF CC=1000µF PO=60mW BW<80kHz SE mode Right Channel 0.01 Left Channel 100 100 THD+N vs. Frequency THD+N vs. Frequency 10 100m THD+N vs. Frequency THD+N vs. Frequency 10 0.1 20m 50m Output Power (W) 0.001 10k 20k 6 Left Channel 20 100 1k Frequency (Hz) 10k 20k www.anpec.com.tw APA2036/APA2036A Typical Operating Characteristics (Cont.) Crosstalk vs. Frequency +0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 Crosstalk (dB) VDD=5V RL=4Ω Ci=1µF PO=1.3W BW<80kHz BTL mode Crosstalk (dB) -120 Crosstalk vs. Frequency Left to Right 100 1k Frequency (Hz) T VDD=5V RL=8Ω Ci=1µF PO=0.9W BW<80kHz BTL mode -70 -80 -90 -100 -110 Right to Left 20 +0 -10 -20 -30 -40 -50 -60 -120 10k 20k Left to Right Right to Left 20 100 Crosstalk vs. Frequency Crosstalk (dB) -30 -40 -50 -60 VDD=5V RL=16Ω Ci=1µF Cc=1000µF PO=110mW BW<80kHz SE mode -70 -80 Left to Right -90 -100 -110 -120 Right to Left 100 1k Frequency (Hz) 10k 20k Output Noise Voltage vs. Frequency Left to Right Right to Left 20 100 1k Frequency (Hz) 10k 20k 50µ Right Channel Output Noise Voltage (Vrms) Output Noise Voltage (Vrms) VDD=5V RL=32Ω Ci=1µF Cc=1000µF Po=60mW BW<80kHz SE mode Output Noise Voltage vs. Frequency 50µ 20µ Left Channel 10µ VDD=5V RL=4Ω Ci=1µF BW<80kHz A-Weighting BTL mode 1µ +0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 20 10k 20k Crosstalk vs. Frequency Crosstalk (dB) +0 -10 -20 1k Frequency (Hz) 20 100 1k Frequency (Hz) Copyright ANPEC Electronics Corp. Rev. A.3 - Jun., 2013 Right Channel 20µ Left Channel 10µ 1µ 10k 20k 7 VDD=5V RL=8Ω Ci=1µF BW<80kHz A-Weighting BTL mode 20 100 1k Frequency (Hz) 10k 20k www.anpec.com.tw APA2036/APA2036A Typical Operating Characteristics (Cont.) Output Noise Voltage vs. Frequency Output Noise Voltage vs. Frequency 50µ Output Noise Voltage (Vrms) 20µ Right Channel Left Channel 1µ VDD=5V RL=16Ω Ci=1µF BW<80kHz A-Weighting SE mode 20 100 1k Frequency (Hz) Left Channel VDD=5V RL=32Ω Ci=1µF BW<80kHz A-Weighting SE mode 1µ 10k 20k +2 +0 10 VDD=5V RL=4Ω Ci=1µF PO=130mW BTL mode 100 +8 +60 +6 +0 Gain(dB) Gain(dB) Phase +4 +120 Phase(deg) Gain +6 Gain 10k 20k +60 Phase VDD=5V RL=8Ω Ci=1µF PO=90mW +0 BTL mode 10 100 -120 100k 200k +0 -60 1k 10k Frequency (Hz) -120 100k 200k Frequency Response +270 -0 +270 Gain Gain -1 +240 -1 +240 -2 +210 -2 +210 VDD=5V RL=16Ω Ci=1µF CC=1000µF -5 PO=11mW SE mode -6 10 100 1k 10k Frequency (Hz) -4 Copyright ANPEC Electronics Corp. Rev. A.3 - Jun., 2013 +180 +150 Gain(dB) Phase -3 Phase(deg) Gain(dB) 1k Frequency (Hz) +120 +4 Frequency Response -0 100 +2 -60 1k 10k Frequency (Hz) 20 Frequency Response Frequency Response +8 Right Channel 10µ Phase(deg) 10µ 20µ -3 +90 100k200k 8 +180 VDD=5V RL=32Ω Ci=1µF -5 CC=1000µF PO=6mW SE mode -6 10 100 1k 10k Frequency (Hz) -4 +120 Phase +150 Phase(deg) Output Noise Voltage (Vrms) 50µ +120 +90 100k 200k www.anpec.com.tw APA2036/APA2036A Typical Operating Characteristics (Cont.) PSRR vs. Frequency +0 VDD=5V RL=4Ω CB=2.2µF Vrr=200mVrms BTL mode -10 -20 -20 -30 -40 -50 Left Channel -30 -40 -50 Left Channel -60 -60 Right Channel -70 -70 -80 VDD=5V RL=8Ω CB=2.2µF Vrr=200mVrms BTL mode -10 PSRR (dB) PSRR (dB) PSRR vs. Frequency +0 20 100 1k Frequency (Hz) -80 10k 20k Right Channel 20 100 +0 VDD=5V RL=16Ω CB=2.2µF Vrr=200mVrms SE mode -30 -20 -40 -50 Right Channel -60 Left Channel -70 -80 20 100 VDD=5V RL=32Ω CB=2.2µF Vrr=200mVrms SE mode -10 PSRR (dB) PSRR (dB) -20 1k Frequency (Hz) -30 -40 -50 -60 Left Channel -70 Right Channel -80 10k 20k 20 Output Power vs. Supply Voltage RL=4Ω Ci=1µF fin=1kHz BTL mode 1.75 1.50 Output Power (W) Output Power (W) 3.0 2.5 2.0 THD+N=10% 1.5 THD+N=1% 1.0 0.5 0.0 3.0 100 1k Frequency (Hz) 10k 20k Output Power vs. Supply Voltage 2.00 4.0 3.5 10k 20k PSRR vs. Frequency PSRR vs. Frequency +0 -10 1k Frequency (Hz) RL=8Ω Ci=1µF fin=1kHz BTL mode 1.25 THD+N=10% 1.00 THD+N=1% 0.75 0.50 0.25 3.5 4.0 4.5 Supply Voltage (V) Copyright ANPEC Electronics Corp. Rev. A.3 - Jun., 2013 5.0 0.00 3.0 5.5 9 3.5 4.0 4.5 Supply Voltage (V) 5.0 5.5 www.anpec.com.tw APA2036/APA2036A Typical Operating Characteristics (Cont.) Output Power vs. Supply Voltage Output Power vs. Supply Voltage 300 150 RL=16Ω Ci=1µF CC=1000µF fin=1kHz SE mode 200 125 Output Power (mW) Output Power (mW) 250 THD+N=10% 150 THD+N=1% 100 100 THD+N=10% 75 0 3.0 0 3.5 4.0 4.5 Supply Voltage (V) 5.0 5.5 3.5 4.0 4.5 Supply Voltage (V) 5.0 5.5 100 1.2 RL=16Ω RL=4Ω Power Dissipation(mW) Power Dissipation(W) 3.0 Power Dissipation vs. Output Power Power Dissipation vs. Output Power 1.4 1.0 0.8 RL=8Ω 0.6 0.4 VDD=5V THD+N<1% BTL mode 0.2 0.0 0.0 0.5 1.0 1.5 Output Power (W) 2.0 80 60 RL=32Ω 40 VDD=5V THD+N<1% SE mode 20 0 2.5 0 50 100 150 200 Output Power (mW) Supply Current vs. Output Power Supply Current vs. Output Power 0.8 50 40 Supply Current (mA) 0.6 Supply Current (A) THD+N=1% 50 25 50 RL=4Ω 0.4 RL=8Ω 0.2 0.0 RL=32Ω Ci=1µF CC=1000µF fin=1kHz SE mode VDD=5V THD+N<1% BTL mode 0.0 0.5 1.0 1.5 Output Power (W) Copyright ANPEC Electronics Corp. Rev. A.3 - Jun., 2013 2.0 30 10 RL=32Ω 20 VDD=5V THD+N<1% SE mode 10 0 2.5 RL=16Ω 0 50 100 150 Output Power (mW) 200 www.anpec.com.tw APA2036/APA2036A Typical Operating Characteristics (Cont.) GSM Power Supply Rejection vs. Frequency +0 6.0 No Load -50 BTL mode 4.0 -100 3.0 Output Voltage (dBV) Supply Current (mA) 5.0 SE mode 2.0 1.0 0.0 2.0 2.5 3.0 3.5 4.0 4.5 Supply Voltage (Volt) Copyright ANPEC Electronics Corp. Rev. A.3 - Jun., 2013 5.0 5.5 11 -150 +0 Supply Voltage (dBV) Supply Current vs. Supply Voltage -50 -100 -150 0 400 800 1.2k Frequency (Hz) 1.6k 2k www.anpec.com.tw APA2036/APA2036A Operating Waveforms GSM Power Supply Rejection vs. Time Output Transient at Power-On VDD 1 VDD VOUT 3 VOUT VOUTP 2 1,2 CH1: VDD, 500mV/Div, DC Voltage Offset = 5.0V CH2: VOUT (VOUTP-VOUTN), 20mV/Div, DC CH1: VDD, 1V/Div, DC CH2: VOUTP, 1V/Div, DC CH3: VOUT (VOUTP-VOUTN), 50mV/Div, DC TIME: 20ms/Div TIME: 100ms/Div Output Transient at Shutdown Active Output Transient at Shutdown Release VSHUTDOWN VOUT VOUT 3 3 VOUTP VOUTP VSHUTDOWN 1,2 1,2 CH1: V SHUTDOWN, 1V/Div, DC CH2: V OUTP, 1V/Div, DC CH1: VSHUTDOWN, 1V/Div, DC CH2: VOUTP, 1V/Div, DC CH3: VOUT(VOUTP-VOUTN), 50mV/Div, DC CH3: V OUT(VOUTP-VOUTN), 50mV/Div, DC TIME: 100ms/Div TIME: 500ms/Div Copyright ANPEC Electronics Corp. Rev. A.3 - Jun., 2013 12 www.anpec.com.tw APA2036/APA2036A Block Diagram LINN LOUTP LBYPASS Bias Voltage Generator LOUTN RINN ROUTP RBYPASS Bias Voltage Generator ROUTN SE/BTL SE/BTL Mode Selection SHUTDOWN VDD Power and Depop Circuit Shutdown Circuit GND Pin Description PIN FUNCTION NO. NAME 1,4,9,11 GND 2 SE/BTL 3 SHUTDOWN 5 LOUTN 6,15 VDD 7 LOUTP 8 LINN 10 LBYPASS Bypass capacitor connection pin for the bias voltage generator. 12 RBYPASS Bypass capacitor connection pin for the bias voltage generator. 13 RINN 14 ROUTP Right channel output in BTL mode and SE mode. As “Typical Application Circuit” shown, this pin’s output signal is inverted against RINN input signal. 16 ROUTN Right channel output in BTL mode, high impedance in SE mode. Copyright ANPEC Electronics Corp. Rev. A.3 - Jun., 2013 Ground connection of circuitry. Connect all GND pins to the thermal pad and system ground plane. Output Mode control pin, high for SE output mode and low for BTL mode. Shutdown mode control pin. Pulling high the voltage on this pin shuts off the IC. In shutdown mode, the IC only draws 0.5µA (typical) of supply current. Left channel output in BTL mode, high impedance in SE mode. Supply voltage input pin. Connect all of the VDD pins to supply voltage. Left channel output in BTL mode and SE mode. As “Typical Application Circuit” shown, this pin’s output signal is inverted against LINN input signal. Left channel input terminal. Right channel input terminal. 13 www.anpec.com.tw APA2036/APA2036A Typical Application Circuit VDD Cs 0.1µF CiL 1µF RiL 20kΩ RfL VDD 20kΩ 10µF GND CCL LINN L-CH Input LOUTP 100µF LBYPASS CB 2.2µF 4Ω LOUTN CinR RiR 1µF 20kΩ R-CH Input Bias Voltage Generator 1kΩ SE/BTL Signal CCR RINN Control Pin Ring ROUTP Sleeve Tip Headphone Jack RfR 100µF 1kΩ 20kΩ RBYPASS VDD 100kΩ SE/BTL Signal Shutdown Signal Bias Voltage Generator 4Ω ROUTN 100kΩ SE/BTL SHUTDOWN Copyright ANPEC Electronics Corp. Rev. A.3 - Jun., 2013 SE/BTL Mode Selection Shutdown Circuit 14 www.anpec.com.tw APA2036/APA2036A Function Description Bridge-Tied Load (BTL) Operation Single-Ended (SE) Operation Rf To consider the single-supply SE configuration shown in the Typical Application Circuit, a coupling capacitor is re- Ri OUTP quired to block the DC offset voltage from reaching the load. These capacitors can be quite large (approximately OP1 33µF to 1000µF), so they tend to be expensive, occupy valuable PCB area, and have the additional drawback of RL OUTN limiting low-frequency performance of the system (refer to the Output Coupling Capacitor). OP2 Bias Voltage Generator SE/BTL Mode Selection Function The best cost saving feature of APA2036/APA2036A is that it can be switched easily between BTL and SE modes. Figure 1. APA2036/APA2036A Internal Configuration (each channel) This feature eliminates the requirement for an additional headphone amplifier in applications where internal ste- The power amplifier’s (OP1) gain is set by external resistance Ri and Rf, while the second amplifier (OP2) is inter- reo speakers are driven in the BTL mode but external headphone or speakers must be accommodated. nally fixed in a unity-gain and inverting configuration. Figure 1 shows that the output of OP1 is connected to the Inside of the APA2036/APA2036A, two separate amplifiers drive OUTP and OUTN (see Figure 1). The SE/BTL input of OP2, which results in the output signals of both amplifiers with identical in magnitude but out of phase input controls the operation of the follower amplifier that drives LOUTP and ROUTN. • When SE/BTL keeps low, the OP2 turns on and the 180°. Consequently, the differential gain for each channel is 2X (Gain of SE mode). By driving the load differentially through outputs OUTP • and OUTN, an amplifier configuration is commonly referred to established bridged mode. BTL mode opera- APA2036/APA2036A is in the BTL mode. When SE/BTL keeps high, the OP2 is in a high output impedance state, which configures the APA2036/ APA2036A as SE driver from OUTP. IDD is reduced by tion is different from the classical single-ended SE amplifier configuration where one side of its load is con- approximately one-half in SE mode. Control of the SE/BTL input can be a logic-level TTL source nected to the ground. A BTL amplifier design has a few distinct advantages over or a resistor divider network or the stereo headphone jack with switch pin as shown in the Typical Application the SE configuration, as it provides differential drive to the load, thus doubles the output swing for a specified sup- Circuit. ply voltage. When placed under the same conditions, a BTL ampli- 1kΩ VDD fier has four times the output power of a SE amplifier. A BTL configuration, such as the one used in the APA2036/ 100kΩ APA2036A, also creates a second advantage over SE amplifiers. Since the differential outputs, ROUTP, ROUTN, Ring SE/BTL LOUTP, and LOUTN, are biased at half-supply, it’s not necessary for DC voltage to be across the load. This Tip Sleeve Headphone Jack eliminates the need for an output coupling capacitor which is required in a single supply, SE configuration. Copyright ANPEC Electronics Corp. Rev. A.3 - Jun., 2013 Control Pin Figure 2. SE/BTL input selection by phonejack plug 15 www.anpec.com.tw APA2036/APA2036A Function Description (Cont.) SE/BTL Mode Selection Function (Cont.) Over-Current Protection In Figure 2, input SE/BTL operates as below: When the phonejack plug is inserted, the 1kΩ resistor is The APA2036/APA2036A monitors the output current. When the current exceeds the current-limit threshold, the disconnected and the SE/BTL input is pulled high to enable the SE mode. Meanwhile, the OUTN amplifier is shut APA2036/APA2036A turns off the output to prevent the IC damages from over-current or short-circuits condition. down which turns the speaker to be mute. The OUTP amplifier then drives through the output capacitor into the When the over-current occurs in power amplifier, the output buffer’s current will be foldbacked to a low setting headphone jack. When there is no headphone plugged into the system, the contact pin of the headphone jack is level, and it will release when over-current situation is no long existence. On the contrary, if the over-current period connected from the signal pin, and the voltage divider is set up by resistors 100kΩ and 1kΩ. Resistor 1kΩ then is is long enough and the IC’s junction temperature reaches the thermal protection threshold, the IC will enter thermal pulled low the SE/BTL pin, enabling the BTL function. protection mode. Shutdown Function In order to reduce power consumption while not in use, the APA2036/APA2036A with shutdown function externally turns off the amplifier bias circuitry. This shutdown feature turns the amplifier off when logic high is placed on the SHUTDOWN pin for the APA2036/APA2036A. The trigger point between a logic high and logic low level is typical 0.4 VDD. It would be better to switch between ground and the supply voltage VDD to provide maximum device performance. By switching the SHUTDOWN pin to a high level, the amplifier enters to a low consumption current state; IDD for the APA2036/APA2036A is in shutdown mode. In normal operation, the APA2036/APA2036A’s SHUTDOWN pin should be pulled to a low level to keep the IC out of the shutdown mode. The SHUTDOWN pin should be tied to a definite voltage to avoid unwanted state changing. Thermal Protection The over-temperature circuit limits the junction temperature of the APA2036/APA2036A. When the junction temperature exceeds TJ = +150oC, a thermal sensor turns off the amplifier, allowing the devices to cool. The thermal sensor allows the amplifier to start up after the junction temperature cools down about 125oC. The thermal protection is designed with a 25oC hysteresis to lower the average T J during c ontinuous thermal overload conditions, which is increasing lifetime of the IC. Copyright ANPEC Electronics Corp. Rev. A.3 - Jun., 2013 16 www.anpec.com.tw APA2036/APA2036A Application Information Input Resistance (Ri) Effective Bypass Capacitor (CB) The gain of the APA2036/APA2036A is set by the external resistors (Ri and Rf). R (1) BTL Gain = −2 × f Ri R SE Gain = − f (2) Ri As to the other power amplifiers, proper supply bypassing is critical for low noise performance and high power BTL mode operation brings the factor of 2 in the gain equation due to the inverting amplifier mirroring the volt- stability. Typical application employs a 5V regulator with 1.0µF and a 0.1µF bypass as supply filtering. This does age swing across the load. The input resistance will affect the low frequency performance of audio signal. not eliminate the need for bypassing the supply nodes of the APA2036/APA2036A. The selection of bypass Input Capacitor (Ci) capacitors, especially CB, thus depends upon desired PSRR requirements, click-and-pop performance. supply rejection. The capacitors located on the bypass and power supply pins should be as close to the device as possible. The effect of a larger half-supply bypass capacitor will improve PSRR due to increased half-supply In the typical application, an input capacitor (Ci) is required To avoid the start-up pop noise, the bypass voltage should rise slower than the input bias voltage and the relation- to allow the amplifier to bias the input signal to the proper DC level for optimum operation. In this case, Ci and the ship shown in equation (5) should be maintained. V (5) CB B + 0.4 > 3RiCi 20µ minimum input impedance Ri from a high-pass filter with the corner frequency are determined in the following equation: FC(highpass ) 1 = 2πR iCi The bypass capacitor is fed from a 160kΩ resistor inside the amplifier. Bypass capacitor, CB, values of 1µF to 2.2µF (3) ceramic or tantalum low-ESR capacitors are recommended for the best THD+N and noise performance. The The value of Ci is important to consider as it directly affects the low frequency performance of the circuit. Consider the example where Ri is 20kΩ and the specification bypass capacitance also effects the start up time. It is determined in the following equation: V Tstart-up = CB B + 0.4 (6) 20µ 1 Note : VB = VDD 2 calls for a flat bass response down to 40Hz. Equation is reconfigured as below: Ci = 1 2πR iFC (4) When input resistance variation is considered, the Ci is For example, if CB=2.2µF, VDD=5V, then the start-up time is 0.68s. 0.2µF, so a value in the range of 0.22µF to 1.0µF would be chosen. A further consideration for this capacitor is the Output Coupling Capcaitor (CC) leakage path from the input source through the input network (Ri +Rf, Ci) to the load. In the typical single-supply SE configuration, an output coupling capacitor (CC) is required to block the DC bias at the output of the amplifier thus preventing DC currents in This leakage current creates a DC offset voltage at the input to the amplifier that reduces useful headroom, es- the load. As with the input coupling capacitor, the output coupling capacitor and impedance of the load form a high- pecially in high gain applications. For this reason, a lowleakage tantalum or ceramic capacitor is the best choice. When polarized capacitors are used, the positive side of the capacitor should face the amplifiers’ input in most pass filter governed by the following equation: 1 FC(highpass ) = 2πRLCC applications because the DC level of the amplifiers’ inputs are held at VDD/2. Please note that it is important to For example, a 330µF capacitor with an 8Ω speaker would attenuate low frequencies below 60.6Hz. The main confirm the capacitor polarity in the application. disadvantage, from a performance standpoint, is typically Copyright ANPEC Electronics Corp. Rev. A.3 - Jun., 2013 17 (7) www.anpec.com.tw APA2036/APA2036A Application Information (Cont.) In a SE configuration, the output coupling capacitor (CC) is the particular concern. This capacitor discharges Output Coupling Capcaitor (CC) (Cont.) small load impedance, which drives the low-frequency corner higher degrading the bass response. Large val- through the internal 10kΩ resistors. Depending on the size of CC, the time constant can be relatively large. To ues of CC are required to pass low frequencies into the load. reduce transients in SE mode, an external 1kΩ resistor can be placed in parallel with the internal 10kΩ resistor. Power Supply Decoupling (CS) The APA2036/APA2036A is a high-performance CMOS au- The tradeoff for using this resistor is an increase in quiescent current. dio amplifier that requires adequate power supply decoupling to ensure the output total harmonic distortion In most cases, choosing a small value of Ci in the range of 0.22µF to 1µF and CB being equal to 2.2µF should (THD+N) is as low as possible. Power supply decoupling also prevents the oscillations being caused by long lead cause a virtually click-less and pop-less turn-on. A high gain amplifier intensifies the problem as the small length between the amplifier and the speaker. The optimum decoupling is achieved by using two differ- delta in voltage is multiplied by the gain. Therefore, it is advantageous to use low-gain configurations. ent capacitors that target on different types of noise on the power supply leads. For higher frequency transients, BTL Amplifier Efficiency An easy-to-use equation to calculate efficiency starts out spikes, or digital hash on the line, a good low equivalentseries-resistance (ESR) ceramic capacitor, typically 0.1µF as being equal to the ratio of power from the power supply to the power is delivered to the load. The following is placed as close as possible to the device VDD lead works best. For filtering lower frequency noise signals, a equations are the basis for calculating amplifier efficiency. PO PSUP Efficiency = large aluminum electrolytic capacitor of 10µF or greater placed near the audio power amplifier is recommended. (8) where: Optimizing Depop Circuitry 2 PO = Circuitry has been included in the APA2036/APA2036A to minimize the amount of popping noise at power-up while VO.RMS = not in shutdown mode. Popping occurs whenever a voltage step is applied to the speaker. In order to eliminate (9) VP (10) 2 PSUP = VDD × IDD.AVG = VDD click-and- pop, all capacitors must be fully discharged before turn-on. 2VP πRL (11) Efficiency of a BTL configuration: Rapid on/off switching of the device or the shutdown function will cause the click-and-pop circuitry. The value of Ci 2 PO PSUP will also affect turn-on pops (refer to Effective Bypass Capacitance). The bypass voltage rises up but should be slower than input bias voltage. Although the bypass pin current source cannot be modified, the size of CB can be VP 2RL πVP = = 2VP 4VDD VDD × πRL (12) Table 1 is for calculating efficiency for four different output power levels. Note that the efficiency of the amplifier is quite low for changed to alter the device turn-on time and the amount of click-and-pops. By increasing the value of CB, turn-on lower power levels and rises sharply as power to the load is increased resulting in nearly flat internal power dissi- pop can be reduced. However, the tradeoff for using a larger bypass capacitor is to increase the turn-on time for pation over the normal operating range. In addition, the internal dissipation at full output power is less than in the this device. There is a linear relationship between the size of CB and the turn-on time. Copyright ANPEC Electronics Corp. Rev. A.3 - Jun., 2013 2 VO.RMS V = P 2RL RL half power range. Calculating the efficiency for a specific 18 www.anpec.com.tw APA2036/APA2036A Application Information (Cont.) BTL Amplifier Efficiency (Cont.) PD, MAX = TJ, MAX − TA θ JA (15) system is the key to proper power supply design. For a stereo 1W audio system with 8Ω loads and a 5V supply, Since the maximum junction temperature (TJ.MAX) of the the maximum draw on the power supply is almost 3W. In the equation, VDD is in the denominator. One last key APA2036/APA2036A is 150OC and the ambient temperature (TA) is defined by the power system design, the maxi- point to remember about linear amplifiers (either SE or BTL) is how to manipulate the terms in the efficiency equa- mum power dissipation, which the IC package is able to handle, can be obtained from equation (15). Once the tion to an utmost advantage when possible. Note that in equation (12), VDD is in the denominator. This indicates power dissipation is greater than the maximum limit (PD, ), the supply voltage (VDD) must be decreased, the load Max that as VDD goes down, and efficiency goes up. In other words, choosing the correct supply voltage and speaker impedance (RL) must be increased or the ambient temperature should be reduced. impedance for the application by using the efficiency analysis. Thermal Consideration PO (W) Efficiency (%) IDD (A) VPP (V) PO (W) 0.25 30.37 0.16 2.00 0.57 0.50 43.37 0.23 2.83 0.65 1.00 61.65 0.32 4.00 0.62 1.25 69.03 0.36 4.47 0.56 Linear power amplifiers dissipates a significant amount of heat in the package in normal operating condition. The first consideration to calculate maximum ambient temperatures is the numbers from the Power Dissipation vs. Output Power graphs are per channel values, so the dissipation of the IC heat needs to be doubled for two-channel operation. Given TQFN4x4-16 package θJA, the maxi- * *High peak voltages cause increasing of the THD+N. Table 1. Efficiency vs. Output Power in 5-V/8Ω Differential mum allowable junction temperature (TJMax), the total internal dissipation (PD), and the maximum ambient tem- Amplifier Systems Power Dissipation perature can be calculated with the following equation. The maximum recommended junction temperature for Whether the power amplifier is operated in BTL or SE modes, power dissipation is a major concern. Equation the APA2036/APA2036A is 150°C. The internal dissipation figures are taken from the Power Dissipation vs. Out- (13) states the maximum power dissipation point for a SE mode operating at a given supply voltage and driving put Power graphs. a specified load. SE mode : PD, MAX = VDD TAMax = TJMax -θJA x PD 150 – 45 (0.8x2) = 78°C 2 (13) 2 π 2R L (16) The APA2036/APA2036A is designed with a thermal shut- In BTL mode operation, the output voltage swing is doubled in SE mode. Thus, the maximum power dissi- down protection that turns the device off when the junction temperature surpasses 150°C to prevent damaging pation point for a BTL mode operated at the same given conditions is 4 times in SE mode. the IC. BTL mode : PD, MAX = 2 VDD 2 π 2R L (14) Even with this substantial increase in power dissipation, the APA2036/APA2036A does not require extra heatsinking. The power dissipation from equation (14), assuming a 5V power supply and an 8Ω load, must not be greater than the power dissipation that results from the equation (15): Copyright ANPEC Electronics Corp. Rev. A.3 - Jun., 2013 19 www.anpec.com.tw APA2036/APA2036A Application Information (Cont.) Layout Consideration Thermal Via diameter 0.3mm x 4 1mm 4.9mm 2.5mm 0.5mm 0.65mm 2.5mm Ground plane for Thermal PAD Figure 3. TQFN4x4-16 Land Pattern Recommendation 1. All components should be placed close to the APA2036/ APA2036A. For example, the input capacitor (Ci) should be close to APA2036/APA2036A’s input pins to avoid causing noise coupling to APA2036/APA2036A’s high impedance inputs; the decoupling capacitor (C S ) should be placed by the APA2036/APA2036A’s power pin to decouple the power rail noise. 2. The output traces should be short, wide (>50mil), and symmetric. 3. The input trace should be short and symmetric. 4. The power trace width should be greater than 50mil. 5. The Thermal PAD should be soldered on PCB, and the ground plane needs soldered mask (to avoid short circuit) except the Thermal PAD area. Copyright ANPEC Electronics Corp. Rev. A.3 - Jun., 2013 20 www.anpec.com.tw APA2036/APA2036A Package Information TQFN4x4-16 D b E A Pin 1 A1 D2 A3 L K E2 Pin 1 Corner e S Y M B O L TQFN4x4-16 MILLIMETERS INCHES MIN. MAX. MIN. MAX. A 0.70 0.80 0.028 0.031 A1 0.00 0.05 0.000 0.002 0.014 A3 0.20 REF 0.008 REF b 0.25 0.35 0.010 D 3.90 4.10 0.154 0.161 D2 2.10 2.50 0.083 0.098 E 3.90 4.10 0.154 0.161 E2 2.10 2.50 0.083 0.098 0.50 0.012 e 0.65 BSC L 0.30 K 0.20 Copyright ANPEC Electronics Corp. Rev. A.3 - Jun., 2013 0.026 BSC 0.020 0.008 21 www.anpec.com.tw APA2036/APA2036A Package Information TQFN3x3-16 D b E A Pin 1 D2 A1 A3 NX aaa c k E2 Pin 1 Corner e S Y M B O L TQFN3x3-16 MILLIMETERS INCHES MIN. MAX. MIN. MAX. A 0.70 0.80 0.028 0.031 A1 0.00 0.05 0.000 0.002 A3 0.20 REF 0.008 REF b 0.18 0.30 0.007 0.012 D 2.90 3.10 0.114 0.122 D2 1.50 1.80 0.059 0.071 E 2.90 3.10 0.114 0.122 E2 1.50 1.80 0.059 0.071 e 0.50 BSC L 0.30 K 0.20 aaa 0.020 BSC 0.012 0.50 0.020 0.008 0.08 0.003 Note : Follow JEDEC MO-220 WEED-4. Copyright ANPEC Electronics Corp. Rev. A.3 - Jun., 2013 22 www.anpec.com.tw APA2036/APA2036A Carrier Tape & Reel Dimensions P0 P2 P1 A B0 W F E1 OD0 K0 A0 A OD1 B B T SECTION A-A SECTION B-B H A d T1 Application TQFN4x4-16 Application TQFN3x3-16 A H 330.0±2.00 50 MIN. P0 P1 T1 C 12.4+2.00 13.0+0.50 -0.00 -0.20 d D 1.5 MIN. 20.2 MIN. W E1 12.0±0.30 1.75±0.10 F 5.5±0.10 P2 D0 D1 T A0 B0 K0 1.5 MIN. 0.6+0.00 -0.40 4.30±0.20 4.30±0.20 1.30±0.20 W E1 F 4.0±0.10 8.0±0.10 2.0±0.10 1.5+0.10 -0.00 A H T1 C d D 330±2.00 50 MIN. 12.4+2.00 -0.00 13.0+0.50 -0.20 1.5 MIN. 20.2 MIN. P0 P1 P2 D0 D1 T A0 B0 K0 2.0±0.05 1.5+0.10 -0.00 1.5 MIN. 0.6+0.00 -0.40 3.30±0.20 3.30±0.20 1.30±0.20 4.0±0.10 8.0±0.10 5.5±0.05 (mm) Devices Per Unit Package Type TQFN4x4-16 TQFN3x3-16 12.0±0.30 1.75±0.10 Unit Tape & Reel Tape & Reel Copyright ANPEC Electronics Corp. Rev. A.3 - Jun., 2013 Quantity 3000 3000 23 www.anpec.com.tw APA2036/APA2036A Taping Direction Information TQFN4x4-16 USER DIRECTION OF FEED TQFN3x3-16 USER DIRECTION OF FEED Copyright ANPEC Electronics Corp. Rev. A.3 - Jun., 2013 24 www.anpec.com.tw APA2036/APA2036A Classification Profile Classification Reflow Profiles Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly 100 °C 150 °C 60-120 seconds 150 °C 200 °C 60-120 seconds 3 °C/second max. 3°C/second max. 183 °C 60-150 seconds 217 °C 60-150 seconds See Classification Temp in table 1 See Classification Temp in table 2 Time (tP)** within 5°C of the specified classification temperature (Tc) 20** seconds 30** seconds Average ramp-down rate (Tp to Tsmax) 6 °C/second max. 6 °C/second max. 6 minutes max. 8 minutes max. Preheat & Soak Temperature min (Tsmin) Temperature max (Tsmax) Time (Tsmin to Tsmax) (ts) Average ramp-up rate (Tsmax to TP) Liquidous temperature (TL) Time at liquidous (tL) Peak package body Temperature (Tp)* Time 25°C to peak temperature * Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum. ** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum. Copyright ANPEC Electronics Corp. Rev. A.3 - Jun., 2013 25 www.anpec.com.tw APA2036/APA2036A Classification Reflow Profiles (Cont.) Table 1. SnPb Eutectic Process – Classification Temperatures (Tc) Package Thickness <2.5 mm ≥2.5 mm Volume mm <350 235 °C 220 °C 3 Volume mm ≥350 220 °C 220 °C 3 Table 2. Pb-free Process – Classification Temperatures (Tc) Package Thickness <1.6 mm 1.6 mm – 2.5 mm ≥2.5 mm Volume mm <350 260 °C 260 °C 250 °C 3 Volume mm 350-2000 260 °C 250 °C 245 °C 3 Volume mm >2000 260 °C 245 °C 245 °C 3 Reliability Test Program Test item SOLDERABILITY HOLT PCT TCT HBM MM Latch-Up Method JESD-22, B102 JESD-22, A108 JESD-22, A102 JESD-22, A104 MIL-STD-883-3015.7 JESD-22, A115 JESD 78 Description 5 Sec, 245°C 1000 Hrs, Bias @ Tj=125°C 168 Hrs, 100%RH, 2atm, 121°C 500 Cycles, -65°C~150°C VHBM≧2KV VMM≧200V 10ms, 1tr≧100mA Customer Service Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 2F, No. 11, Lane 218, Sec 2 Jhongsing Rd., Sindian City, Taipei County 23146, Taiwan Tel : 886-2-2910-3838 Fax : 886-2-2917-3838 Copyright ANPEC Electronics Corp. Rev. A.3 - Jun., 2013 26 www.anpec.com.tw