APA2120/2121 Stereo 2-W Audio Power Amplifier (with DC_Volume Control) Features • • General Description Low Operating Current with 14mA APA2120/1 is a monolithic integrated circuit, which pro- Improved Depop Circuitry to Eliminate Turn-on vides precise DC volume control, and a stereo bridged audio power amplifiers is capable of producing 2.7W(2. and Turn-off Transients in Outputs • • 0W) into 3Ω with less than 10% (1.0%)THD+N. The attenuator range of the volume control in APA2120/1 is from High PSRR 32 Steps Volume Adjustable by DC Voltage with 20dB (DC_Vol=0V) to -80dB (DC_Vol=3.54V) with 32 steps. The advantage of internal gain setting can be less Hysteresis • 2W Per Channel Output Power into 4Ω Load at components and PCB area. Both of the depop circuitry and the thermal shutdown protection circuitry are inte- 5V, BTL Mode • Two Output Modes Allowable with BTL and SE grated in APA2120/1 and reduce pops and clicks noise during power up or shutdown mode operation. It also Modes Selected by SE/BTL Pin • Low Current Consumption in Shutdown Mode improves the power off pop noise and protects the chip from being destroyed by over temperature and short cur- (50µA) • • • Power off Depop Circuit Integration • Lead Free and Green Devices Available Short Circuit Protection rent failure. To simplify the audio system design, APA2120/ 1 combines a stereo bridge-tied loads (BTL) mode for speaker drive and a stereo single-end (SE) mode for headphone drive into a single chip, where both modes are TSSOP-24P with or without Thermal Pad Package easily switched by the SE/BTL input control pin signal. Besides, the multiple input selection is used for portable (RoHS Compliant) audio system. Applications • • NoteBook PC LCD Monitor or TV Ordering and Marking Information Package Code R : TSSOP-24P Operating Ambient Temperature Range I : - 40 to 85 oC Handling Code TR : Tape & Reel Assembly Material G : Halogen and Lead Free Device APA2120/1 Assembly Material Handling Code Temperature Range Package Code APA2120/1 R : APA2120/1 XXXXX XXXXX - Date Code Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by weight). ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright ANPEC Electronics Corp. Rev. A.4 - Jul., 2013 1 www.anpec.com.tw APA2120/2121 Pin Configuration GND PCBEN VOLUME LOUT+ LLINEIN LHPIN PVDD RBYPASS 1 2 3 4 5 6 7 8 LOUTLBYPASS BYPASS GND 9 24 23 22 21 20 19 18 17 16 10 11 12 15 14 13 APA2120 TOP View GND RLINEIN SHUTDOWN ROUT+ RHPIN VDD PVDD CLK GND HP/LINE VOLUME LOUT+ LLINEIN LHPIN PVDD RBYPASS 1 2 3 4 5 6 7 8 ROUTSE/BTL PC-BEEP GND LOUTLBYPASS BYPASS GND 9 10 11 12 APA2121 TOP View 24 23 22 21 20 19 18 17 16 GND RLINEIN SHUTDOWN ROUT+ RHPIN VDD PVDD CLK ROUTSE/BTL PC-BEEP GND 15 14 13 Thermal Pad APA2120 APA2121 Multiple Input Selection SE/BTL HP/LINE PCBEEP Control Input PCBEN - APA2120/1 Bottom View Absolute Maximum Ratings (Note 1) (Over operating free-air temperature range unless otherwise noted.) Symbol VDD Parameter Rating Supply Voltage Range VIN Input Voltage Range, SE/BTL, HP/LINE, SHUTDOWN, PCBEN TA Operating Ambient Temperature Range TJ TSTG Maximum Junction Temperature -0.3 to 6 V -0.3 to VDD+0.3 V -40 to 85 °C Intermal Limited Storage Temperature Range TS Maximum Lead Soldering Temperature,10 Seconds PD Power Dissipation Unit (Note 2) °C -65 to +150 °C 260 °C Intermal Limited W Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note 2: APA2120/1 integrated internal thermal shutdown protection when junction temperature ramp up to 150°C Copyright ANPEC Electronics Corp. Rev. A.4 - Jul., 2013 2 www.anpec.com.tw APA2120/2121 Thermal Characteristics Symbol θJA Parameter Thermal Resistance from Junction to Ambient in Free Air Typical Value Unit 45 °C/W (Note 3) TSSOP-24P Note 3 : 5 in2 printed circuit board with 2oz trace and copper pad through 9 25mil diameter vias. The thermal pad on the TSSOP_P package with solder on the printed circuit board. Recommended Operating Conditions Symbol Parameter VDD Supply Voltage VIH High Level Threshold Voltage VIL Low Level Threshold Voltage VICM Common Mode Input Voltage Range Unit V 4.5 ~ 5.5 SHUTDOWN, PCBEN 2~ SE/BTL , HP/LINE 4~ V SHUTDOWN, PCBEN ~ 1.0 SE/BTL , HP/LINE ~3 V VDD-1.0 ~ V Electrical Characteristics VDD=5V, -20°C<TA<85°C (unless otherwise noted) Symbol Parameter VDD Supply Voltage IDD Supply Current ISD Supply Current in Shutdown Mode IIH IIL VOS APA2120/1 Test Conditions Unit Min. Typ. Max. 4.5 - 5.5 V SE/BTL=0V - 14 25 SE/BTL=5V - 8.0 15 SE/BTL=5V SHUTDOWN=0V - 50 - µA High input Current - 900 - nA Low Input Current - 900 - nA Output Differential Voltage - 5 - mV mA Operating Characteristics, BTL mode VDD=5V,TA=25°C, RL=4Ω, AV=2V/V (unless otherwise noted) Symbol PO THD+N PSRR Parameter Maximum Output Power Total Harmonic Distortion Plus Noise Power Ripple Rejection Ratio Copyright ANPEC Electronics Corp. Rev. A.4 - Jul., 2013 APA2120/1 Test Conditions Unit Min. Typ. Max. THD+N=10%, RL=3Ω, fin=1kHz - 2.7 - THD+N=10%, RL=4Ω, fin=1kHz - 2.3 - THD+N=10%, RL=8Ω, fin=1kHz - 1.5 - THD+N=1%, RL=3Ω, fin=1kHz - 2.0 - THD+N=1%, RL=4Ω, fin=1kHz - 1.9 - THD+N=0.5%, RL=8Ω, fin=1kHz 1 1.1 - PO=1.5W, RL=4Ω, fin=1kHz - 0.05 - PO=1W, RL=8Ω, fin=1kHz - 0.07 - VIN=0.1Vrms, RL=8Ω, CB=1µF, fin=120Hz - 60 - 3 W % dB www.anpec.com.tw APA2120/2121 Electrical Characteristics (Cont.) Operating Characteristics, BTL mode VDD=5V,TA=25°C, RL=4Ω, AV=2V/V (unless otherwise noted) Symbol Parameter APA2120/1 Test Conditions Unit Min. Typ. Max. Xtalk Channel Separation CB=1µF, RL=8Ω, fin=1kHz - 90 - dB S/N Signal to Noise Ratio PO=1.1mW, RL=8Ω, A_weighting - 95 - dB Operating Characteristics, SE mode VDD=5V,TA=25°C, RL=4Ω, Gain=1V/V (unless otherwise noted) Symbol PO THD+N Parameter Maximum Output Power Total Harmonic Distortion Plus Noise APA2120/1 Test Conditions Unit Min. Typ. Max. THD+N=10%, RL=8Ω, fin=1kHz - 400 - THD+N=10%, RL=32Ω, fin=1kHz - 110 - THD+N=1%, RL=8Ω, fin=1kHz - 320 - THD+N=1%, RL=32Ω, fin=1kHz - 90 - PO=250mW, RL=8Ω, fin=1kHz - 0.08 - PO=75mW, RL=32Ω, fin=1kHz - 0.08 - mW % PSRR Power Ripple Rejection Ratio VIN=0.1Vrms, RL=8Ω, CB=1µF, fin=120Hz - 48 - dB Xtalk Channel Separation CB=1µF, RL=32Ω, fin=1kHz - 100 - dB S/N Signal to Noise Ratio PO=75mW, SE, RL=32Ω, A_weighting - 100 - dB Copyright ANPEC Electronics Corp. Rev. A.4 - Jul., 2013 4 www.anpec.com.tw APA2120/2121 Typical Operating Characteristics THD+N vs. Output Power THD+N vs. Frequency 10 10 VDD=5V RL=3Ω PO=1.75W BTL VDD=5V RL=3Ω AV=2 BTL 1 AV=10 AV=2 0.1 fin=20kHz THD+N (%) THD+N (%) 1 0.1 fin=1kHz AV=5 0.01 20 100 fin=20Hz 1k 0.01 10m 20k 100m THD+N vs. Output Power THD+N vs. Frequency 10 10 VDD=5V RL=4Ω AV=2 BTL VDD=5V RL=4Ω PO=1.5W BTL 1 THD+N (%) 1 THD+N (%) 2 3 Output Power (W) Frequency (Hz) 0.1 1 fin=20kHz 0.1 AV=2 fin=1kHz AV=5 fin=20Hz AV=10 0.01 20 50 100 200 500 1k 2k 5k 0.01 100m 20k Frequency (W) Copyright ANPEC Electronics Corp. Rev. A.4 - Jul., 2013 200m 500m 800m 2 3 Output Power (W) 5 www.anpec.com.tw APA2120/2121 Typical Operating Characteristics (Cont.) THD+N vs. Frequency THD+N vs. Output Power 10 10 VDD=5V RL=8Ω AV=2 BTL VDD=5V RL=8Ω PO=1.0W BTL 1 THD+N (%) THD+N (%) 1 0.1 0.01 20 fin=20kHz 0.1 AV=2 100 AV=5 fin=1kHz AV=10 fin=20Hz 1k 0.01 10m 20k 1 Output Power (W) THD+N vs. Frequency THD+N vs. Output Power 2 10 10 VDD=5V RL=8Ω PO=250mW SE VDD=5V RL=8Ω AV=2 BTL 1 THD+N (%) THD+N (%) 100m Frequency (Hz) AV=1 AV=5 0.1 1 fin=20kHz 0.1 fin=20Hz AV=2.5 0.01 20 100 1k fin=1kHz 0.01 10m 20k Frequency (Hz) Copyright ANPEC Electronics Corp. Rev. A.4 - Jul., 2013 100m 500m Output Power (W) 6 www.anpec.com.tw APA2120/2121 Typical Operating Characteristics (Cont.) THD+N vs. Output Power THD+N vs. Frequency 10 10 VDD=5V RL=16Ω PO=100mW SE VDD=5V RL=16Ω AV=1 BTL 0.1 1 THD+N (%) THD+N (%) 1 AV=1 AV=2 fin=20kHz fin=20Hz 0.1 fin=1kHz AV=2.5 0.01 20 100 1k 0.01 10m 20k 100m Output Power (W) Frequency (Hz) THD+N vs. Frequency THD+N vs. Output Power 10 10 VDD=5V RL=32Ω PO=75mW SE VDD=5V RL=32Ω AV=1 BTL fin=20kHz 1 THD+N (%) THD+N (%) 1 AV=2.5 AV=1 0.1 0.1 fin=20Hz fin=1kHz AV=5 0.01 20 300m 100 1k 0.01 10m 20k Frequency (Hz) Copyright ANPEC Electronics Corp. Rev. A.4 - Jul., 2013 50m 100m 200m Output Power (W) 7 www.anpec.com.tw APA2120/2121 Typical Operating Characteristics (Cont.) THD+N vs. Output Swing THD+N vs. Frequency 10 10 VDD=5V RL=10Ω AV=1 SE VDD=5V RL=10Ω VO=1VRMS SE 1 0.1 AV=2.5 THD+N (%) THD+N (%) 1 AV=1 0.1 fin=20kHz fin=1kHz AV=5 0.01 20 fin=20Hz 100 1k 0.01 100m 20k 500m Frequency (Hz) +0 VDD=5V RL=8Ω PO=1.0W AV=2 BTL -20 VDD=5V RL=32Ω PO=75mW AV=1 SE -40 Crosstalk (dB) Crosstalk (dB) -40 -60 R-ch to L-ch -100 -80 1k -120 20 20k 100 1k 20k Frequency (Hz) Frequency (Hz) Copyright ANPEC Electronics Corp. Rev. A.4 - Jul., 2013 L-ch to R-ch -100 -120 100 -60 R-ch to L-ch L-ch to R-ch 20 3 Crosstalk vs. Frequency +0 -80 2 Output Swing (VRMS) Crosstalk vs. Frequency -20 1 8 www.anpec.com.tw APA2120/2121 Typical Operating Characteristics (Cont.) Noise Floor vs. Frequency Noise Floor vs. Frequency 100µ 100µ 50µ 50µ VDD=5V RL=32Ω AV=1 SE Noise Floor (µVRMS) Noise Floor (µVRMS) No Filter 20µ A-Weighting 10µ 5µ VDD=5V RL=8Ω AV=2 BTL 2µ 100 1k No Filter 10µ A-Weighting 5µ 2µ 1µ 20 20µ 1µ 20 20k 100 Power Dissipation vs. Output Power Noise Floor vs. Frequency 100µ 0.18 0.16 Power Dissipation (W) Noise Floor (µVRMS) 0.2 VDD=5V RL=10kΩ AV=1 SE No Filter 20µ 10µ A-Weighting 5µ 0.14 RL=8Ω 0.12 0.1 RL=16Ω 0.08 0.06 RL=32Ω 0.04 2µ 1µ 20 20k Frequency (Hz) Frequency (Hz) 50µ 1k VDD=5V AV=1 SE 0.02 0 100 1k 0 20k 0.2 0.25 0.3 0.35 0.4 Output Power (W) Frequency (Hz) Copyright ANPEC Electronics Corp. Rev. A.4 - Jul., 2013 0.05 0.1 0.15 9 www.anpec.com.tw APA2120/2121 Typical Operating Characteristics (Cont.) Power Dissipation vs. Output Power Supply Current vs. Supply Voltage 20 1.8 1.6 17.5 RL=3Ω 15 Suuply Current (mA) Power Dissipation (W) 1.4 1.2 1 RL=4Ω 0.8 0.6 RL=8Ω 0.4 VDD=5V AV=2 BTL 0.2 BTL 12.5 10 SE 7.5 5 2.5 No Load 0 0 2.0 0.5 1 1.5 2 2.5 1 2 2.5 3 3.5 4 4.5 5 5.5 Output Power (W) Supply Voltage (V) Output Power vs. Supply Voltage Output Power vs. Supply Voltage 160 RL=8Ω AV=2 BTL 1.8 1.5 RL=32Ω AV=1 SE 140 1.6 Output Power (mW) Output Power (W) 120 1.4 THD+N=10% 1.2 1.0 0.8 THD+N=1% 0.6 100 THD+N=10% 80 60 THD+N=1% 40 0.4 20 0.2 0 0 2.5 3 3.5 4 4.5 5 5.5 2.5 Supply Voltage (V) Copyright ANPEC Electronics Corp. Rev. A.4 - Jul., 2013 3 3.5 4 4.5 5 5.5 Supply Voltage (V) 10 www.anpec.com.tw APA2120/2121 Typical Operating Characteristics (Cont.) Output Power vs. Load Resistance Output Power vs. Load Resistance 0.7 3 VDD=5V AV=2 BTL 0.6 Output Power (W) Output Power (W) 2.5 2 1.5 1 THD+N=10% 0.5 0.5 0.4 0.3 0.2 0.1 THD+N=1% VDD=5V AV=1 SE THD+N=10% THD+N=1% 0 0 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60 64 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60 64 Load Resistance (Ω) Load Resistance (Ω) Close Loop Response Close Loop Response +6 +12 +10 VDD=5V RL=8Ω AV=2 BTL CO=330µF +4 +6 Loop Gain (dB) Loop Gain (dB) +8 AV=2 AV=5 AV=10 +4 +2 +0 AV=1 AV=2.5 AV=5 -2 -4 +2 -0 20 VDD=5V RL=32Ω AV=1 SE CO=330µF 100 1k -6 20 20k 1k 20k Frequency (Hz) Frequency (Hz) Copyright ANPEC Electronics Corp. Rev. A.4 - Jul., 2013 100 11 www.anpec.com.tw APA2120/2121 Typical Operating Characteristics (Cont.) PSRR vs. Frequency +0 Ripple Rejection Ratio (dB) -20 TT VDD=5V Vin=100mVRMS RL=8Ω Cbypass=2.2µF BTL -40 SE -60 -80 20 100 1k 20k Frequency (Hz) Pin Description PIN I/O/P NAME NO. FUNCTION GND 1,12,13,24 PCBEN 2 I/P BEEP mode control input, active H, for APA2120 only Ground connection, Connected to the thermal pad. HP/LINE 2 I/P Multi-input selection input, headphone mode when held high, line-in mode when held low for APA2121 only. VOLUME 3 LOUT+ 4 O/P Left channel positive output in BTL mode and SE mode. LLINEIN 5 I/P Left channel line input terminal, selected when HP/LINE is held low. LHPIN 6 O/P Left channel headphone input terminal, selected when HP/LINE is held high. PVDD 7,18 RBYPASS 8 I/P Right channel bypass voltage. LOUT- 9 O/P Left channel negative output in BTL mode and high impedance in SE mode. LBYPASS 10 I/P Left channel bias voltage generator. Input signal for internal volume gain setting. Supply voltage only for power amplifier. BYPASS 11 PC_BEEP 14 Bias voltage generator SE/BTL ROUTCLK 17 Clock signal generator VDD 19 Supply voltage for internal circuit excepting power amplifier. I/P PCBEP signal input 15 I/P Output mode control input, high for SE output mode and low for BTL mode. 16 O/P Right channel negative output in BTL mode and high impedance in SE mode. Copyright ANPEC Electronics Corp. Rev. A.4 - Jul., 2013 12 www.anpec.com.tw APA2120/2121 Pin Description (Cont.) PIN I/O/P NAME NO. FUNCTION RHPIN 20 I/P Right channel headphone input terminal, selected when HP/LINE is held high. ROUT+ 21 O/P Right channel positive output in BTL mode and SE mode. SHUTDOWN 22 I/P It will be into shutdown mode when pull low. RLINEIN 23 I/P Right channel line input terminal, selected when HP/LINE is held low. Block Diagram LLINEIN LHPIN RLINEIN RHPIN LOUT+ MUX LOUT- Volume Control LBYPASS MUX VOLUME BYPASS BYPASS ROUT+ HP/LINE SE/BTL HP/LINE ROUT- SE/BTL RBYPASS SHUTDOWN PCBEEP Shutdown ckt PC-BEEP ckt Clock Gen CLK For APA2121 Copyright ANPEC Electronics Corp. Rev. A.4 - Jul., 2013 13 www.anpec.com.tw APA2120/2121 Typical Application Circuits APA2120 VDD 0Ω 0.1µF VDD 1µF LLINEIN LHPIN L-LINE L-HP GND PVDD LOUT+ 220µF MUX 1kΩ 1µF 1µF RHPIN LOUT- Volume Control RLINEIN R-LINE R-HP 100µF 4Ω Control Ring Pin LBYPASS MUX SE/BTL 2.2µF 1µF VDD BYPASS VOLUME 50kΩ Sleeve Tip Headphone Jack BYPASS ROUT+ 220µF 1kΩ VDD 100kΩ 100kΩ SE/BTL 4Ω ROUT- SE/BTL RBYPASS SHUTDOWN Shutdown Signal BEEP Signal 0.47µF PCBEN Signal Shutdown ckt PCBEEP PCBEN Copyright ANPEC Electronics Corp. Rev. A.4 - Jul., 2013 Clock Gen PC-BEEP ckt 14 CLK 47nF www.anpec.com.tw APA2120/2121 Typical Application Circuits (Cont.) APA2121 VDD 0Ω 0.1µF VDD 1µF PVDD LOUT+ LLINEIN LHPIN L-LINE 100µF GND 220µF MUX 1kΩ 1µF L-HP 1µF R-LINE SE/BTL Sleeve Tip Headphone Jack BYPASS BYPASS VOLUME 50kΩ Control Ring Pin 2.2µF VDD 1µF 4Ω LBYPASS MUX RHPIN R-HP LOUT- Volume Control RLINEIN ROUT+ 220µF HP/LINE Signal 100kΩ 1kΩ HP/LINE HP/LINE VDD 100kΩ 4Ω SE/BTL ROUT- SE/BTL RBYPASS Shutdown Signal BEEP Signal SHUTDOWN Shutdown ckt PCBEEP PC-BEEP ckt 0.47µF CLK Clock Gen 47nF Control Input Table For APA2120 SE/BTL X SHUTDOWN PC-BEEP Operating Mode L Disable Shutdown mode L H Disable Line input, BTL out H H Disable HP input, SE out X X Enable PCBEEP input, BTL out For APA2121 SE/BTL HP/LINE SHUTDOWN PC-BEEP Operating Mode X X L Disable Shutdown mode Line input, BTL out L L H Disable L H H Disable HP input, BTL out H L H Disable Line input, SE out H H H Disable HP input, BTL out X X X Enable PCBEEP input, BTL out Copyright ANPEC Electronics Corp. Rev. A.4 - Jul., 2013 15 www.anpec.com.tw APA2120/2121 Volume Control Table_BTL Mode Supply Voltage Vdd=5V Gain(dB) High(V) Low(V) 20 0.12 0.00 Hysteresis(mV) Recommended Voltage(V) 18 16 0.23 0.34 0.17 0.28 52 51 0.20 0.31 14 12 0.46 0.39 50 0.43 0.57 0.51 49 0.54 10 0.69 0.62 47 0.65 8 0.80 0.73 46 0.77 6 4 0.91 1.03 0.84 0.96 45 44 0.88 0.99 2 1.14 1.07 43 1.10 0 1.25 1.18 41 1.22 -2 1.37 1.29 40 1.33 -4 1.48 1.41 39 1.44 -6 -8 1.59 1.71 1.52 1.63 38 37 1.56 1.67 -10 1.82 1.74 35 1.78 -12 1.93 1.85 34 1.89 -14 2.05 1.97 33 2.01 -16 2.16 2.08 32 2.12 -18 -20 2.28 2.39 2.19 2.30 30 29 2.23 2.35 -22 2.50 2.42 28 2.46 -24 2.62 2.53 27 2.57 -26 2.73 2.64 26 2.69 -28 2.84 2.75 24 2.80 -30 -32 2.96 3.07 2.87 2.98 23 22 2.91 3.02 -34 3.18 3.09 21 3.14 -36 3.30 3.20 20 3.25 -38 3.41 3.32 18 3.36 -40 3.52 3.43 17 3.48 -80 5.00 3.54 16 5 Copyright ANPEC Electronics Corp. Rev. A.4 - Jul., 2013 0 16 www.anpec.com.tw APA2120/2121 Application Information BTL Operation The APA2120/1 output stage (power amplifier) has two Single-Ended Operation Consider the single-supply SE configuration shown Application Circuit. A coupling capacitor is required to block pairs of operational amplifiers internally, allowed for different amplifier configurations. the DC offset voltage from reaching the load. These capacitors can be quite large (approximately 33µF to 1000µF) so they tend to be expensive, occupied valuable PCB area, and have the additional drawback of limiting low- OUT+ Volume Control amplifier output signal frequency performance of the system (refer to the Output Coupling Capacitor).The rules described still hold with OP1 RL Vbias Circuit the addition of the following relationship: 1 ≤ 1 << 1 Cbypass x 125kΩ RiCi RLCC OUT- (1) OP2 Output SE/BTL Operation The best cost saving feature of APA2120/1 is that they can Figure 1 : APA2120/1 Internal Configuration. (each channel) The power amplifier’s OP1 gain is setting by internal unity- be switched easily between BTL and SE modes. This feature eliminates the requirement for an additional head- gain and the input audio signal comes from the internal volume control amplifier while the second amplifier OP2 phone amplifier in applications where internal stereo speakers are driven in the BTL mode but external head- is internally fixed in a unity-gain, inverting configuration. Figure 1 shows that the output of OP1 is connected to the phone or speakers must be accommodated. Internal to the APA2120/1, two separate amplifiers drive OUT+ and OUT- (see Figure 1). The SE/BTL input controls the operation of the follower amplifier that drives input to OP2, which results in the output signals of both amplifiers with identical in magnitude, but out of phase LOUT- and ROUT-. • When SE/BTL is held low, the OP2 is turned on and 180°. Consequently, the differential gain for each channel is 2 x (Gain of SE mode). the APA2120/1 is in the BTL mode. • When SE/BTL is held high, the OP2 is in a high output By driving the load differentially through outputs OUT+ and OUT-, an amplifier configuration commonly referred to bridged mode is established. The BTL mode opera- impedance state, which configures the APA2120/1 as SE driver from OUT+. IDD is reduced by approximately one- tion is different from the classical single-ended SE amplifier configuration where one side of its load is con- half in SE mode. The control of the SE/BTL input can be a logic-level TTL source, a resistor divider network, or the stereo head- nected to the ground. A BTL amplifier design has a few distinct advantages over phone jack with switch pin as shown in the Application Circuit. the SE configuration, as it provides differential drive to the load, thus doubling the output swing for a specified supply voltage. When placed under the same conditions, a BTL amplifier 1kΩ has four times the output power of a SE amplifier. A BTL configuration, such as the one used in APA2120/1, also VDD 100kΩ creates a second advantage over SE amplifiers. Since the differential outputs, ROUT+, ROUT-, LOUT+, and Ring SE/BTL LOUT-, are biased at half-supply, it’s not necessary for DC voltage to be across the load. This eliminates the Tip need for an output coupling capacitor which is required in a single supply, SE configuration. Copyright ANPEC Electronics Corp. Rev. A.4 - Jul., 2013 Control Pin Sleeve Headphone Jack Figure 2 : SE/BTL Input Selection by Phonejack Plug. 17 www.anpec.com.tw APA2120/2121 Application Information (Cont.) Output SE/BTL Operation (Cont.) In Figure 2, input SE/BTL operates as below : When the phonejack plug is inserted, the 1kΩ resistor is For the highest accuracy, the voltage is shown in the ‘recommended voltage’ column of the table and used to se- disconnected and the SE/BTL input is pulled high and enables the SE mode. When the input goes to a high lect a desired gain. This recommended voltage is exactly halfway between the two nearest transitions. The gain level, the OUT- amplifier is shutdown which causes the speaker to mute. Then, the OUT+ amplifier drives through levels are 2dB/step from 20dB to -40dB in BTL mode, and the last step at -80dB as mute mode. the output capacitor (CC) into the headphone jack. When there is no headphone plugged into the system, the con- Input Resistance, Ri tact pin of the headphone jack is connected from the signal pin, and the voltage divider set up by resistors 100kΩ The gain for each audio input of the APA2120/1 is set by the internal resistors (Ri and Rf) of volume control ampli- and 1kΩ. Resistor 1kΩ then pulls low the SE/BTL pin, enabling the BTL function. fier in inverting configuration. SE Gain = AV = - Volume Control Function APA2120/1 have an internal stereo volume control that setting is the function of the DC voltage applied to the BTL Gain = -2 x RF Ri (2) RF Ri (3) VOLUME input pin. The APA2120/1 volume control consists of 32 steps that are individually selected by a vari- BTL mode operation brings the factor of 2 in the gain able DC voltage level on the VOLUME control pin. The range of the steps, controlled by the DC voltage, are from equation due to the inverting amplifier mirroring the voltage swing across the load. For the varying gain setting, 20dB to -80dB. Each gain step corresponds to a specific APA2120/1 generate each input resistance on the figure 4. The input resistance will affect the low frequency per- input voltage range as shown in table. To minimize the effect of noise on the volume control pin, which can affect formance of audio signal. The minmum input resistance is 10kΩ when gain setting is 20dB, and the resistance the selected gain level, hysteresis and clock delay are implemented. The amount of hysteresis corresponds to will ramp up when close loop gain below 20dB. The input resistance has wide variation (+/-10%) caused by the pro- half of the step width is shown in the volume control graph. cess variation. Gain_BTL mode APA2021 volume control curve Forward Backward 20 Ri(kΩ) 16 Ri vs Gain(BTL) 120 12 8 100 4 80 0 -4 60 -8 -12 40 -16 -20 20 -24 -28 0 -32 -40 -36 -30 -20 -10 0 10 20 -40 Gain(dB) -44 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 3.8 (V) Figure 4: Input Resistance vs Gain Setting. Figure 3 : Gain setting vs VOLUME Pin Voltage. Copyright ANPEC Electronics Corp. Rev. A.4 - Jul., 2013 18 www.anpec.com.tw APA2120/2121 Application Information (Cont.) Input Capacitor, Ci In the typical application, an input capacitor, Ci, is required to allow the amplifier to bias the input signal to the proper for bypassing the supply nodes of the APA2120/1. The selection of bypass capacitors, especially Cbypass, is DC level for optimum operation. In this case, Ci and the minimum input impedance Ri (10kΩ) form a high-pass thus dependent upon desired PSRR requirements, click and pop performance. On the chip, there are three bypass pins for used, and they are tied together in the internal circuit. The effective capacitance is the Cbypass=(Cb//CLbyasss/ filter with the corner frequency determined in the following equation : FC(highpass)= 1 2πx10kΩxCi (4) /CRbypass). When absolute minimum cost and/or component space is required, one bypass capacitor can be used. To avoid the start-up pop noise, the bypass voltage should rise slower than the input bias voltage and the relation- The value of Ci is important to consider as it directly affects the low frequency performance of the circuit. Consider the example where Ri is 10kΩ and the specification ship shown in equation (6) should be maintained. calls for a flat bass response down to 100Hz. Equation is reconfigured as below : 1 Ci= 2πx10kΩxfC 1 1 << Cbypass x 125kΩ 100kΩ x Ci (5) (6) The bypass capacitor is fed from a 125kΩ resistor inside the amplifier and the 100kΩ is maximum input resistance When the input resistance variation is considered, the Ci is 0.16µF. Therefore, a value in the range of 0.22µF to of (Ri+ Rf). Bypass capacitor, Cb, values of 3.3µF to 10µF ceramic or tantalum low-ESR capacitors are recom- 1.0µF would be chosen. mended for the best THD and noise performance. A further consideration for this capacitor is the leakage path from the input source through the input network The bypass capacitance also effects to the start up time. It is determined in the following equation : (Ri+Rf, Ci) to the load. This leakage current creates a DC offset voltage at the input to the amplifier that reduces Tstart up = 5 x (Cbypass x 125kΩ) useful headroom, especially in high gain applications. For this reason, a low-leakage tantalum or ceramic ca- (7) Output Coupling Capacitor, Cc In the typical single-supply SE configuration, an output coupling capacitor (Cc) is required to block the DC bias at pacitor is the best choice. When polarized capacitors are used, the positive side of the capacitor should face the the output of the amplifier thus preventing DC currents in the load. As with the input coupling capacitor, the output amplifier input in most applications as the DC level there is held at VDD/2, which is likely higher than the source DC coupling capacitor and impedance of the load form a highpass filter governed by the following equation: level. Please note that it is important to confirm the capacitor polarity in the application. FC(highpass)= Effective Bypass Capacitor, Cbypass As other power amplifiers, proper supply bypassing is 1 2πRLCC (8) For example, a 330µF capacitor with an 8Ω speaker would critical for low noise performance and high power supply rejection. attenuate low frequencies below 60.6Hz. The main disadvantage of performance is that the load impedance is The capacitors located on both the bypass and power supply pins should be as close to the device as possible. typically small, which drives the low-frequency corner higher degrading the bass response. Large values of CC The effect of a larger bypass capacitor will improve PSRR due to increased supply stability. Typical applications em- are required to pass low frequencies into the load. ploy a 5V regulator with 1.0µF and a 0.1µF bypass capacitor as supply filtering. This does not eliminate the need Copyright ANPEC Electronics Corp. Rev. A.4 - Jul., 2013 19 www.anpec.com.tw APA2120/2121 Application Information (Cont.) Power Supply Decoupling, Cs The APA2120/1 provide PVDD and VDD two independent power inputs for used. PVDD is used for power amplifier This capacitor discharges through the internal 10kΩ resistors. Depending on the size of CC, the time constant only and VDD is used for volume control amplifier and internal circuit excepting power amplifier. The APA2120/1 are can be relatively large. To reduce transients in SE mode, an external 1kΩ resistor can be placed in parallel with the high-performance CMOS audio amplifiers that requires adequate power supply decoupling to ensure the output internal 10kΩ resistor. The tradeoff for using this resistor is an increase in quiescent current. In most cases, choos- total harmonic distortion (THD) is as low as possible. Power supply decoupling also prevents the oscillations ing a small value of Ci in the range of 0.33µF to 1µF, Cb being equal to 4.7µF and an external 1kΩ resistor should being caused by long lead length between the amplifier and the speaker. The optimum decoupling is achieved by be placed in parallel, and the internal 10kΩ resistor should produce a virtually clickless and popless turn-on. using two different types of capacitors that target on different noise on the power supply leads. For higher frequency transients, spikes, or digital hash on the line, a good low equivalent-series-resistance(ESR) A high gain amplifier intensifies the problem as the small delta in voltage is multiplied by the gain. So it is advantageous to use low-gain configurations. Shutdown Function ceramic capacitor, typically 0.1µF placed as close as possible to the device VDD and PVDD lead works the best. For In order to reduce power consumption while not in use, the APA2120/1 contain a shutdown pin to externally turn off the amplifier bias circuitry. This shutdown feature turns filtering lower-frequency noise signals, a large aluminum electrolytic capacitor of 10µF or greater placed near the audio power amplifier is recommended. the amplifier off when a logic low is placed on the SHUTDOWN pin. The trigger point between a logic high and Optimizing Depop Circuitry logic low level is typically 2.0V. It is best to switch be- Circuitry has been included in the APA2120/1 to minimize the amount of popping noise at power-up and when com- tween the ground and the supply VDD to provide maximum device performance. By switching the SHUTDOWN pin to low, the amplifier ing out of shutdown mode. Popping occurs whenever a voltage step is applied to the speaker. In order to elimi- enters a low-current state, IDD<50µA. APA2120/1 is in shutdown mode, except PC-BEEP detect circuit. Under nor- nate clicks and pops, all capacitors must be fully discharged before turn-on. Rapid on/off switching of the de- mal operation, SHUTDOWN pin pulls to high level to keep the IC out of the shutdown mode. The SHUTDOWN pin vice or the shutdown function will cause the click and pop circuitry. should be tied to a definite voltage to avoid unwanted state changing. The value of Ci will also affect turn-on pops. (Refer to Effective Bypass Capacitance) The bypass voltage should rises slower than input bias voltage. Although the bypass Input HP/LINE Operation APA2120/1 amplifiers have two separate inputs for each pin current source cannot be modified, the size of Cbypass can be changed to alter the device turn-on time and the of the left and right stereo channels. The APA2120 and APA2121 have different control input by SE/BTL and HP/ amount of clicks and pops. By increasing the value of Cbypass, turn-on pop can be reduced. However, the LINE, respectively. APA2120 internal multiplexor is selected by SE/BTL con- tradeoff for using a larger bypass capacitor is to increase the turn-on time for this device. There is a linear relation- trol input. Refer to the ‘Output SE/BTL Operation’, the voltage divider of 100kΩ and 1kΩ sets the voltage at the SE/ ship between the size of Cbypass and the turn-on time. In a SE configuration, the output coupling capacitor, CC, is BTL pin to be approximately 50mV when no phonejack plugged into the system. of particular concern. Copyright ANPEC Electronics Corp. Rev. A.4 - Jul., 2013 20 www.anpec.com.tw APA2120/2121 Application Information (Cont.) Input HP/LINE Operation (Cont.) BTL Amplifier Efficiency This logic-low voltage at the SE/BTL pin makes APA2120 into LINE input mode operation. It becomes HP input An easy-to-use equation to calculate efficiency starts out mode when phonejack plugged. as being equal to the ratio of power from the power supply to the power delivered to the load. An internal multiplexor selects the input to connect to the amplifier based on the state of the HP/LINE pin of the The following equations are the basis for calculating amplifier efficiency. APA2121. • To select the LINE inputs, set HP/LINE pin to a low • level. To enable the HP(headphone) inputs, set HP/LINE Efficiency = PO PSUP (9) Where : PO = VORMS x VORMS = VPxVP 2RL RL pin to a high level. As APA2121, HP/LINE input multiplexor and SE/BTL out- VP √2 put operating mode have independent control paths, which can be used for multiple audio input system. This VORMS = function will be the same as APA2120 when HP/LINE and SE/BTL are tied together. PSUP = VDD x IDDAVG = VDD x 2VP πRL PC-BEEP Detection (10) (11) Table 1 Calculates Efficiencies for Four Different Output Power Levels. APA2120/1 integrate a BEEP detect circuit for NOTEBOOK PC. When BEEP signal is provided on the PCBEEP input Note that the efficiency of the amplifier is quite low for pin, the BEEP mode is active. APA2120/1 will force to BTL mode and the internal gain is fixed at -10dB. The PCBEEP lower power levels and rises sharply as power to the load is increased resulting in a nearly flat internal power dissi- signal becomes the amplifier input signal and plays on pation over the normal operating range. Note that the internal dissipation at full output power is less than the the speaker without coupling capacitor. It will be out of shutdown mode whenever BEEP mode is enabled. dissipation in the half power range. Calculating the efficiency for a specific system is the key to proper power APA2120/1 will return to previous setting when it is out of BEEP mode. The input impedance is 100kΩ on the supply design. For a stereo 1W audio system with 8Ω loads and a 5V supply, the maximum draw on the power PCBEEP input pin. APA2120 provide extra PCBEN control input signal to force IC into BEEP mode. The BEEP mode will be enabled when PCBEN goes to a high level. When the BEEP mode supply is almost 3W. A final point to remember about linear amplifiers (either SE or BTL) is how to manipulate the terms in the effi- is overridden, the signal from the PCBEEP will pass to speaker directly. ciency equation to an utmost advantage when possible. Note that in equation, VDD is in the denominator. This indi- Clock Generator cates that as VDD goes down, efficiency goes up. In other words, use the efficiency analysis to choose the correct APA2120/1 integrate a clock block to avoid volume control function abnormal when VOLUME control signal with supply voltage and speaker impedance for the application. spike or noise. APA2120/1 change each step of volume gain after four clock cycles make sure control signal ready. It provides 130kHz frequency if no capacitor is placed on CLK pin to the ground. The larger capacitance will slow down the and clock frequency. A capacitor 33nF between CLK to the ground and will generate 147Hz frequency on Efficiency (%) IDD(A) VPP(V) PD (W) 0.25 31.25 0.16 2.00 0.55 0.50 47.62 0.21 2.83 0.55 1.00 66.67 0.30 4.00 0.5 1.25 78.13 0.32 4.47 0.35 **High peak voltages cause the THD to increase. the CLK pin. Copyright ANPEC Electronics Corp. Rev. A.4 - Jul., 2013 Po (W) Table 1. Efficiency Vs Output Power in 5-V/8Ω BTL Systems 21 www.anpec.com.tw APA2120/2121 Application Information (Cont.) Power Dissipation Whether the power amplifier is operated in BTL or SE modes, power dissipation is a major concern. Equation13 The thermal pad on the bottom of the APA2120/1 should be soldered down to a copper pad on the circuit board. states the maximum power dissipation point for a SE mode operating at a given supply voltage and driving a Heat can be conducted away from the thermal pad through the copper plane to ambient. If the copper plane is not on specified load. the top surface of the circuit board, 8 to 10 vias of 13 mil or smaller in diameter should be used to thermally couple SE mode : PD,MAX= VDD2 2π2RL (13) the thermal pad to the bottom plane. For good thermal conduction, the vias must be plated through and solder filled. The copper plane used to con- In BTL mode operation, the output voltage swing is doubled as in SE mode. Thus, the maximum power dis- duct heat away from the thermal pad should be as large as practical. sipation point for a BTL mode operating at the same given conditions is 4 times as in SE mode. 4VDD 2π2RL If the ambient temperature is higher than 25°C, a larger copper plane or forced-air cooling will be required to keep 2 BTL mode : PD,MAX= (14) the APA2120/1 junction temperature below the thermal shutdown temperature (150°C). In higher ambient Since the APA2120/1 are dual channel power amplifiers, the maximum internal power dissipation is 2 times that temperature, higher airflow rate and/or larger copper area will be required to keep the IC out of the thermal shutdown. both of equations depend on the mode of operation. Even this substantial increase in power dissipation, the APA2120/1 do not require extra heatsink. The power dissipation from equation14, assuming a 5V-power supply Recommended Minmum Footprint and an 8Ω load, must not be greater than the power dis- PD,MAX= TJ,MAX - TA θJA Via diameter Via diameter =0.3mm X10 sipation that results from the equation15 : =0.3mm X8 3mm 1.7mm (15) 4.7mm 1.7mm 0.35mm For TSSOP-24 package with thermal pad, the thermal resistance (θJA) is equal to 45οC/W. Since the maximum junction temperature (TJ,MAX ) of APA2120/1 are 150οC and the ambient temperature (TA) are defined by the power system design, the maximum 4.5mm power dissipation which the IC package is able to handle can be obtained from equation16. Once the power dissipation is greater than the maximum limit (P D,MAX ), either the supply voltage (V DD) must be decreased, the load impedance (RL) must be increased or the ambient temperature should be reduced. 0.65mm Thermal Pad Consideration The thermal pad must be connected to the ground. The package with thermal pad of the APA2120/1 require spe- Ground plane for ThermalPAD cial attention on thermal design. If the thermal design issues are not properly addressed, the APA2120/1 4Ω Exposed for thermal PAD connected TSSOP-24P will go into thermal shutdown when driving a 4Ω load. Copyright ANPEC Electronics Corp. Rev. A.4 - Jul., 2013 22 www.anpec.com.tw APA2120/2121 Package Information TSSOP-24P D SEE VIEW A b A VIEW A L 0 GAUGE PLANE SEATING PLANE A1 S Y M B O L 0.25 c A2 e E E2 EXPOSED PAD E1 D1 TSSOP-24P INCHES MILLIMETERS MIN. MAX. A MIN. MAX. 1.20 0.047 A1 0.05 0.15 0.002 0.006 A2 0.80 1.05 0.031 0.041 b 0.19 0.30 0.007 0.012 c 0.09 0.20 0.004 0.008 D 7.70 7.90 0.303 0.311 D1 3.50 5.00 0.138 0.197 E 6.20 6.60 0.244 0.260 E1 4.30 4.50 0.169 0.177 3.50 0.098 0.138 0.75 0.018 8o 0o E2 2.50 e L 0 0.65 BSC 0.45 0o 0.026 BSC 0.030 8o Note : 1. Followed from JEDEC MO-153 ADT. 2. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion or gate burrs shall not exceed 6 mil per side. 3. Dimension "E1" does not include inter-lead flash or protrusions. Inter-lead flash and protrusions shall not exceed 10 mil per side. Copyright ANPEC Electronics Corp. Rev. A.4 - Jul., 2013 23 www.anpec.com.tw APA2120/2121 Carrier Tape & Reel Dimensions P0 P2 P1 A B0 W F E1 OD0 K0 A0 A OD1 B B T SECTION A-A SECTION B-B H A d T1 Application TSSOP-24P A H T1 C d D W E1 F 330.0±2.00 50 MIN. 16.4+2.00 -0.00 13.0+0.50 -0.20 1.5 MIN. 20.2 MIN. 16.0±0.30 1.75±0.10 7.50±0.10 P0 P1 P2 D0 D1 T A0 B0 K0 2.00±0.10 1.5+0.10 -0.00 1.5 MIN. 0.6+0.00 -0.40 6.9±0.20 8.30.±0.20 1.50±0.20 4.00±0.10 8.00±0.10 (mm) Devices Per Unit Package Type Unit Quantity TSSOP-24P Tape & Reel 2000 Copyright ANPEC Electronics Corp. Rev. A.4 - Jul., 2013 24 www.anpec.com.tw APA2120/2121 Taping Direction Information TSSOP-24P USER DIRECTION OF FEED Classification Profile Copyright ANPEC Electronics Corp. Rev. A.4 - Jul., 2013 25 www.anpec.com.tw APA2120/2121 Classification Reflow Profiles Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly 100 °C 150 °C 60-120 seconds 150 °C 200 °C 60-120 seconds 3 °C/second max. 3°C/second max. 183 °C 60-150 seconds 217 °C 60-150 seconds See Classification Temp in table 1 See Classification Temp in table 2 Time (tP)** within 5°C of the specified classification temperature (Tc) 20** seconds 30** seconds Average ramp-down rate (Tp to Tsmax) 6 °C/second max. 6 °C/second max. 6 minutes max. 8 minutes max. Preheat & Soak Temperature min (Tsmin) Temperature max (Tsmax) Time (Tsmin to Tsmax) (ts) Average ramp-up rate (Tsmax to TP) Liquidous temperature (TL) Time at liquidous (tL) Peak (Tp)* package body Temperature Time 25°C to peak temperature * Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum. ** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum. Table 1. SnPb Eutectic Process – Classification Temperatures (Tc) 3 Package Thickness <2.5 mm Volume mm <350 235 °C Volume mm ≥350 220 °C ≥2.5 mm 220 °C 220 °C 3 Table 2. Pb-free Process – Classification Temperatures (Tc) Package Thickness <1.6 mm 1.6 mm – 2.5 mm ≥2.5 mm Volume mm <350 260 °C 260 °C 250 °C 3 Volume mm 350-2000 260 °C 250 °C 245 °C 3 Volume mm >2000 260 °C 245 °C 245 °C 3 Reliability Test Program Test item SOLDERABILITY HOLT PCT TCT HBM MM Latch-Up Copyright ANPEC Electronics Corp. Rev. A.4 - Jul., 2013 Method JESD-22, B102 JESD-22, A108 JESD-22, A102 JESD-22, A104 MIL-STD-883-3015.7 JESD-22, A115 JESD 78 26 Description 5 Sec, 245°C 1000 Hrs, Bias @ 125°C 168 Hrs, 100%RH, 2atm, 121°C 500 Cycles, -65°C~150°C VHBM≧2KV VMM≧200V 10ms, 1tr≧100mA www.anpec.com.tw APA2120/2121 Customer Service Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 2F, No. 11, Lane 218, Sec 2 Jhongsing Rd., Sindian City, Taipei County 23146, Taiwan Tel : 886-2-2910-3838 Fax : 886-2-2917-3838 Copyright ANPEC Electronics Corp. Rev. A.4 - Jul., 2013 27 www.anpec.com.tw