BB ADC674ASH

®
ADC674A
Microprocessor-Compatible
ANALOG-TO-DIGITAL CONVERTER
FEATURES
DESCRIPTION
● COMPLETE 12-BIT A/D CONVERTER
WITH REFERENCE, CLOCK, AND 8-, 12-,
OR 16-BIT MICROPROCESSOR BUS
INTERFACE
● IMPROVED PERFORMANCE SECOND
SOURCE FOR ADC574A/674A-TYPE A/D
CONVERTERS
Conversion Time: 15µs max
Bus Access Time:150ns max
A0 Input: Bus Contention During Read
Operation Eliminated
The ADC674A is a 12-bit successive approximation
analog-to-digital converter, utilizing state-of-the-art
CMOS and laser-trimmed bipolar die custom-designed
for freedom from latch-up and for optimum AC performance. It is complete with a self-contained +10V
reference, internal clock, digital interface for microprocessor control, and three-state outputs.
The reference circuit, containing a buried zener, is
laser-trimmed for minimum temperature coefficient.
The clock oscillator is current-controlled for excellent stability over temperature. Full-scale and offset
errors may be externally trimmed to zero. Internal
scaling resistors are provided for the selection of
analog input signal ranges of 0V to +10V, 0V to
+20V, ±5V, and ±10V.
● FULLY SPECIFIED FOR OPERATION ON
±12V OR ±15V SUPPLIES
● NO MISSING CODES OVER
TEMPERATURE:
0°C to +75°C ADC674AJH, KH, JP, KP
Grades
–55°C to +125°C (ADC674ASH, TH Grades)
The converter may be externally programmed to
provide 8- or 12-bit resolution. The conversion time
for 12 bits is factory set for 15µs maximum.
Output data are available in a parallel format from
TTL-compatible three-state output buffers. Output data
are coded in straight binary for unipolar input signals
and bipolar offset binary for bipolar input signals.
The ADC674A, available in both industrial and
military temperature ranges, requires supply voltages
of +5V and ±12V or ±15V. It is packaged in a 28-pin
plastic DIP, or hermetic side-brazed ceramic DIP.
Control
Inputs
10V Range
Comparator
12-Bit D/A
Converter
Reference
Input
Reference
Output
Three-State Buffers
Clock
20V Range
Status
Successive
Approximation
Register
Bipolar
Offset
Control
Logic
Parallel
Data
Output
10V
Reference
International Airport Industrial Park • Mailing Address: PO Box 11400 • Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd. • Tucson, AZ 85706
Tel: (520) 746-1111 • Twx: 910-952-1111 • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
©
1984 Burr-Brown Corporation
PDS-551D
Printed in U.S.A. October, 1993
SPECIFICATIONS
ELECTRICAL
At TA = +25°C, VCC = ±12V or +15V, VEE = –12V or –15VDC, and VLOGIC = +5V, unless otherwise noted.
ADC674AJP, JH, SH
PARAMETER
MIN
TYP
ADC674AKP, KH, TH
MAX
RESOULUTION
MIN
TYP
12
ANALOG INPUTS
Voltage Ranges: Unipolar
Bipolar
Impedance: 0 to +10V, ±5V
±10V, 0V to +20V
4.7
9.4
DIGITAL INPUTS (CE, CS, R/C, AO, 12/8)
Over Temperature Range
Voltages: Logic 1
Logic 0
Current
Capacitiance
+2
–0.5
–5
TRANSFER CHARACTERISTICS
ACCURACY
At +25°C
Linearity Error
Unipolar Offset Error (adjustable to zero)
Bipolar Offset Error (adjustable to zero)
Full-Scale Calibration Error(1) (adjustable to zero)
No Missing Codes Resolution (differential linearity)
Inherent Quantization Error
TMIN to TMAX
Linearity Error: J, K Grades
S, T Grades
Full-Scale Calibration Error
Without Initial Adjustmen(1): J, K Grades
S, T Grades
Adjusted to zero at +25°C: J, K Grades
S, T Grades
No Missing Codes Resolution (differential linearity)
TEMPERATURE COEFFICIENTS (TMIN to TMAX
Unipolar Offset: J, K Grades
S, T Grades
Max Change: All Grades
Bipolar Offset: All Grades
Max Change: J, K Grades
S, T Grades
Full-Scale Calibration: J, K Grades
S, T Grades
Max Change: J, K Grades
S, T Grades
0 to +10, 0 to +20
±5, ±10
5
10
0.2
5
DIGITAL OUTPUT (DB11—DB0, Status)
(Over Temperature Range)
Outputs Codes: Unipolar
Bipolar
Logic Levels: Logic 0 (ISINK = 1.6mA)
Logic 1 (ISOURCE = 500µA)
Leakage, Data Bits Only , High-Z State
Capacitance
INTERNAL REFERENCE VOLTAGE
Voltage
Source Current Available for External Loads(5)
11
±1/2
±5.5
±0.8
±5
*
*
*
UNITS
*
Bits
*
*
V
V
kΩ
kΩ
*
*
*
V
V
µA
pF
±1/2
*
±4
LSB
LSB
LSB
*
% of FS(2)
Bits
LSB
±1
±1
±1/2
±3/4
LSB
LSB
±0.47
±0.75
±0.22
±0.5
±0.37
±0.5
±0.12
±0.25
% of FS
% of FS
% of FS
% of FS
Bits
±10
±5
±2
±10
±2
±4
±45
±50
±9
±20
±5
±2.5
±1
±5
±1
±2
±25
±25
±5
±10
ppm/°C
ppm/°C
LSB
ppm/°C
LSB
LSB
ppm/°C
ppm/°C
LSB
LSB
±2
±2
±1/2
±1
±1
*
LSB
LSB
LSB
*
*
µs
µs
*
V
V
µA
pF
*
*
±0.25
12
*
11
12
)(3)
6
9
+2.4
–5
+9.9
2
8
12
0.1
5
±10
®
ADC674A
*
*
±1
±2
±10
POWER SENSITIVITY
Change in Full-Scale Calibration
+13.5V < VCC < +16.5V or +11.4V < VCC < +12.6V
+16.5V < VEE < +13.5V or –12.6V < VEE < –11.4V
+4.5V < VLOGIC < +5.5V
CONVERSION TIME(4)
8-Bit Cycle
12-Bit Cycle
5.3
10.6
*
*
*
*
MAX
2
10
15
*
*
Unipolar Straight Binary (USB)
* (BOB)
Bipolar Offset Binary
+0.4
*
+5
*
±10.1
*
*
*
*
*
*
*
*
*
V
mA
SPECIFICATIONS
(CONT)
ELECTRICAL
At TA = +25°C, VCC = ±12V or +15V, VEE = –12V or –15VDC, and VLOGIC = +5V, unless otherwise noted.
ADC674AJP, AJH, ASH
PARAMETER
MIN
POWER SUPPLY REQUIREMENTS
Voltage: VCC
+11.4
VEE
VLOGIC
Current: ICC
IEE
ILOGIC
Power Dissipation (±15V Supplies)
TYP
MAX
+16.5
*
–16.5
+5.5
5
20
15
450
–11.4
+4.5
3.5
15
9
325
TEMPERATURE RANGE (Ambient: TMIN, TMAX)
Specification: K, J Grades
S, T Grades
Storage
0
–55
–65
+75
+125
+150
ADC674AKP, AKH, ATH
MIN
TYP
MAX
UNITS
*
V
*
*
*
*
*
*
V
V
mA
mA
mA
mW
*
*
*
°C
°C
°C
*
*
*
*
*
*
*
*
*
* Specifications same as ADC674AJP, AJH, ASH.
NOTES: (1) With fixed 50Ω resistor from REF OUT to REF IN. This parameter is also adjustable to zero at +25°C (see Optional External Full Scale and Offset
Adjustments section). (2) FS in this specification table means Full Scale Range. That is, for a ±10V input range, FS means 20 V; for a 0 to +10V range, FS means
10V. The term Full Scale for these specifications instead of Full-Scale Range is used to be consistent with other vendor’s 674A type specification tables. (3) Using
internal reference. (4) See Controlling the ADC674A section for detailed information concerning digital timing. (5) External loading must be constant during
conversion. The reference output requires no buffer amplifier with either ±12V or ±15V power supplies.
BURN-IN SCREENING
Burn-in screening is available for both plastic and ceramic
package ADC674As. Burn-in duration is 160 hours at the
temperature (or equivalent combination of time and temperature) indicated below:
Plastic “-BI” models: +85°C
Ceramic “-BI” models: +125°C
ABSOLUTE MAXIMUM RATINGS
VCC to Digital Common .......................................................... 0 to +16.5V
VEE to Digital Common ........................................................... 0 to –16.5V
VLOGIC to Digital Common ........................................................... 0 to +7V
Analog Common to Digital Common .................................................. ±1V
Control Inputs (CE, CS, AO, 12/8, R/C)
to Digital Common ............................................. –0.5V to VLOGIC +0.5V
Analog Inputs REF IN, BIP. OFF., 10VIN)
to Analog Common ...................................................................... ±16.5V
20VIN to Analog Common ................................................................. ±24V
REF OUT ...................................................... Indefinite Short to Common,
Momentary Short to VCC
Max Junction Temperature ............................................................ +165°C
Power Dissipation ........................................................................ 1000mW
Lead Temperature (soldering, 10s) ............................................... +300°C
Thermal Resistance, θJA: Ceramic ................................................. 50°C/W
Plastic ................................................. 100°C/W
All units are 100% electrically tested after burn-in is completed. To order burn-in, add “-BI” to the base model
number (e.g., ADC674AKP-BI).
CAUTION: These devices are sensitive to electrostatic discharge.
Appropriate I.C. handling procedures should be followed.
ORDERING INFORMATION
MODEL
ADC674AJP
ADC674AKP
ADC674AJH
ADC674AKH
ADC674ASH
ADC674ATH
PACKAGE INFORMATION
TEMPERATURE
LINEARITY
ERROR
PACKAGE
RANGE
max (TMIN to TMAX)
Plastic DIP
Plastic DIP
Ceramic DIP
Ceramic DIP
Ceramic DIP
Ceramic DIP
0°C to +75°C
0°C to +75°C
0°C to +75°C
0°C to +75°C
–55°C to +125°C
–55°C to +125°C
±1LSB
±1/2LSB
±1LSB
±1/2LSB
±1LSB
±3/4LSB
TEMPERATURE
BURN-IN
TEMPERATURE
PACKAGE
RANGE
(160 Hours)(1)
Plastic DIP
Plastic DIP
Ceramic DIP
Ceramic DIP
Ceramic DIP
Ceramic DIP
0°C to +75°C
0°C to +75°C
0°C to +75°C
0°C to +75°C
–55°C to +125°C
–55°C to +125°C
+85°C
+85°C
+125°C
+125°C
+125°C
+125°C
BURN-IN SCREENING OPTION
See text for details.
MODEL
ADC674AJP-BI
ADC674AKP-BI
ADC674AJH-BI
ADC674AKH-BI
ADC674ASH-BI
ADC674ATH-BI
PACKAGE
PACKAGE DRAWING
NUMBER(1)
ADC674AJP
ADC674AKP
ADC674AJH
ADC674AKH
ADC674ASH
ADC674ATH
Plastic DIP
Plastic DIP
Ceramic DIP
Ceramic DIP
Ceramic DIP
Ceramic DIP
215
215
149
149
149
149
ADC674AJP-BI
ADC674AKP-BI
ADC674AJH-BI
ADC674AKH-BI
ADC674ASH-BI
ADC674ATH-BI
Plastic DIP
Plastic DIP
Ceramic DIP
Ceramic DIP
Ceramic DIP
Ceramic DIP
215
215
149
149
149
149
MODEL
NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix D of Burr-Brown IC Data Book.
NOTE: (1) Or equivalent combination of time and temperature.
®
3
ADC674A
PIN CONFIGURATION
3
AO
4
R/C
5
CE
6
+V CC
7
Ref Out
8
Analog Common
9
Ref In
10
Clock
10V
Reference
12 Bits
12-Bit
D/A
Converter
Comparator
V EE
11
Bipolar Offset
12
10kΩ
12 Bits
Nibble A
CS
Control
Logic
Nibble B
2
Nibble C
12/8
Power-up Reset
Three-State Buffers and Control
1
Successive Approximation Register
+5VDC Supply (VLOGIC )
28
Status
27
DB11 (MSB)
26
DB10
25
DB9
24
DB8
23
DB7
22
DB6
21
DB5
20
DB4
19
DB3
18
DB2
17
DB1
16
DB0 (LSB)
15
Digital Common
5kΩ
10V Range
13
20V Range
14
5kΩ
CONTROLLING THE ADC674A
The Burr-Brown ADC674A can be easily interfaced to most
microprocessor systems and other digital systems. The microprocessor may take full control of each conversion, or the
converter may operate in a stand-alone mode, controlled
only by the R/C input. Full control consists of selecting an
8- or 112-bit conversion cycle, initiating the conversion, and
the output data when ready—choosing either 12 bits all at
once, or 8 bits followed by 4 bits in a left-justified format.
The five control inputs (12/8, CS, AO, R/C, and CE) are all
TTL-/CMOS-compatible. The functions of the control inputs are described in Table I. The control function truth table
is listed in Table II.
CE
CS
R/C
12/8
AO
0
X
X
X
X
OPERATION
X
1
X
X
X
None
↑
0
0
X
0
Initiate 12-bit conversion
↑
0
0
X
1
Initiate 8-bit conversion
1
↓
0
X
0
Initiate 12-bit conversion
1
↓
0
X
1
Initiate 8-bit conversion
1
0
↓
X
0
Initiate 12-bit conversion
1
0
↓
X
1
Initiate 8-bit conversion
1
0
1
1
X
Enable 12-bit output
1
0
1
0
0
Enable 8 MSBs only
1
0
1
0
1
Enable 4 LSBs plus 4
trailing zeros
None
TABLE II. Control Input Truth Table.
PIN
DESIGNATION
DEFINITION
FUNCTION
CE (Pin 6)
Chip Enable
(active high)
Must be high (“1”) to either initiate a conversion or read output data. 0-1 edge may be used to initiate a
conversion.
CS (Pin 3)
Chip Select
(active low)
Must be low (“0”) ot either initiate a conversion or read output data. 1-0 edge may be used to initiate a conversion.
R/C (Pin 5)
Read/Convert
(“1” = read)
(“0” = convert)
Must be low (“0”) to initiate either 8- or 12-bit conversions. 1-0 edge may be used to initiate a conversion. Must be high
(“1”) to read output data. 0-1 edge may be used to initiate a read operation.
AO (Pin 4)
Byte Address
Short Cycle
In the start-convert mode, A O selects 8-bit (A O = “1”) or 12-bit (AO = “0”) conversion mode. When reading output
data in two 8-bit bytes, AO = “0” accesses ±8MSBs (high byte) and AO = “1” accesses 4LSBs and trailing “0s” (low
byte).
12/8 (Pin 2)
Data Mode Select
(“1” = 12-bits)
When reading output data. 12/8 = “1” enables all 12 output bits simultaneously. 12/8 = “0” will enable the MSBs
or LSBs as determined by the AO line.
(“0” = 8-bits)
TABLE I. ADC674A Control Line Functions.
®
ADC674A
4
STAND-ALONE OPERATION
For stand-alone operation, control of the converter is accomplished by a single control line connected to R/C. In this
mode CS and AO are connected to digital common and CE
and 12/8 are connected to VLOGIC (+5V). The output data are
presented as 12-bit words. The stand-alone mode is used in
systems containing dedicated input ports which do not
require full bus interface capability.
tDS
STS Delay from R/C
tHDR
Data Valid After R/C Low
TYP
MAX
ns
200
25
tHS
STS Delay After Data Valid
300
tHRH
High R/C Pulse Width
150
tDDR
Data Access Time
UNITS
ns
ns
400
1000
ns
ns
150
ns
The converter is commanded to initiate conversion by a
transition occurring on any of three logic inputs (CE, CS,
and R/C) as shown in Table II. Conversion is initiated by the
last of the three to reach the required state and thus all three
may be dynamically controlled. If necessary, all three may
change states simultaneously, and the nominal delay time is
the same regardless of which input actually starts conversion. If it is desired that a particular input establish the actual
start of conversion, the other two should be stable a minimum of 50ns prior to the transition of that input. Timing
relationships for start of conversion timing are illustrated in
Figure 3. The specifications for timing are contained in
Table IV.
tDS
DB11-DB0
50
CONVERSION START
tHRL
tC
tHDR
MIN
Low R/C Pulse Width
FULLY CONTROLLED OPERATION
Conversion Length
Conversion length (8-bit or 12-bit) is determined by the state
of the AO input, which is latched upon receipt of a conversion start transition (described below). If AO is latched high,
the conversion continues for 8 bits. The full 12-bit conversion will occur if AO is low. If all 12 bits are read following
an 8-bit conversion the 3LSBs (DB0 - DB2) will be low
(logic 0) and DB3 will be high (logic 1). A O
is latched because it is also involved in enabling the output
buffers. No other control inputs are latched.
Figure 1 illustrates timing when conversion is initiated by an
R/C pulse which goes low and returns to the high state
during the conversion. In this case, the three-state outputs go
to the high-impedance state in response to the falling edge of
R/C and are enabled for external access of the data after
completion of the conversion. Figure 2 illustrates the timing
when conversion is initiated by a positive R/C pulse. In this
mode, the output data from the previous conversion is
enabled during the positive portion of R/C. A new conversion is started on the falling edge of R/C, and the three-state
outputs return to the high impedance state until the next
occurrence of a high R/C pulse. Timing specifications for
stand-alone operation are listed in Table III.
STATUS
PARAMETER
tHRL
TABLE III. Stand-Alone Mode Timing.
Conversion is initiated by a high-to-low transition of R/C.
The three-state data output buffers are enabled when R/C is
high and STATUS is low. Thus, there are two possible
modes of operation; conversion can be initiated with either
positive or negative pulses. In either case, the R/C pulse
must remain low for a minimum of 50ns.
R/C
SYMBOL
tHS
High-Z State
Data Valid
Data Valid
CE
FIGURE 1. R/C Pulse Low—Outputs Enabled After Conversions.
tHEC
tSSC
CS
tSRC
tHSC
R/C
R/C
tHRH
tDS
tHRC
AO
STATUS
tDDR
High-Z
tHDR
Data Valid
tC
tSAC
High-Z State
tHAC
DB11-DB0
STATUS
tDSC
FIGURE 2. R/C Pulse High—Outputs Enabled Only While
R/C is High.
DB11-DB0
tC
High Impedance
FIGURE 3. Conversion Cycle Timing.
®
5
ADC674A
SYMBOL
PARAMETER
MIN
TYP
MAX
UNITS
60
200
ns
Convert Mode
tDSC
STS Delay from CE
tHEC
CE Pulse Width
50
30
ns
tSSC
CS to CE Setup
50
20
ns
tHSC
CS Low During CE High
50
20
ns
tSRC
R/C to CE Setup
50
0
ns
tHRC
R/C Low During CE High
50
20
tSAC
AO To CE Setup
0
tHAC
AO Valid During CE high
50
20
Conversion Time, 12 Bit Cycle
9
12
15
µs
6
8
10
µs
75
150
25
35
tC
8 Bit Cycle
Read Mode
tDD
Access Time From CE
tHD
Data Valid After CE Low
ns
ns
ns
ns
ns
tHL
Output Float Delay
tSSR
CS to CE Setup
100
tSRR
R/C to CE Setup
0
tSAR
AO to CE Setup
50
tHSR
CS Valid After CE Low
tHRR
R/C high After CE Low
0
ns
tHAR
AO Valid After CE Low
50
ns
tHS
STS delay After Data Valid
50
150
ns
0
ns
ns
100
25
ns
0
ns
300
600
ns
NOTE: Specifications are at + 25°C and measured at 50% level of transitions.
TABLE IV. Timing Specifications
The STATUS output indicates the current state of the converter by being in a high state only during conversion.
During this time the three state output buffers remain in a
high-impedance state, and therefore data cannot be read
during conversion. During this period additional transitions
of the three digital inputs which control conversion will be
ignored, so that conversion cannot be prematurely terminated or restarted. However, if AO changes state after the
beginning of conversion, any additional start conversion
transition will latch the new state of AO, possibly resulting
in an incorrect conversion length (8 bits vs 12 bits) for that
conversion.
CE
tSSR
tHSR
CS
tHRR
R/C
tSRR
AO
tSAR
READING OUTPUT DATA
After conversion is initiated, the output data buffers remain
in a high-impedance state until the following four logic
conditions are simultaneously met: R/C high, STATUS low,
CE high, and CS low. Upon satisfaction of these conditions
the data lines are enabled according to the state of inputs
12/8 and AO. See Figure 4 and Table IV for timing relationships and specifications.
tHAR
STATUS
tHS
DB11-DB0
High-Z
tDD
tHD
Data Valid
tHL
FIGURE 4. Read Cycle Timing.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN
assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject
to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not
authorize or warrant any BURR-BROWN product for use in life support devices and/or systems.
®
ADC674A
6