® DAC7528 CMOS Dual 8-Bit Buffered Multiplying DIGITAL-TO-ANALOG CONVERTER FEATURES DESCRIPTION ● DOUBLE BUFFERED DATA LATCHES The DAC7528 contains two, 8-bit multiplying digitalto-analog converters (DACs). Separate on-chip latches hold the input data for each DAC to allow easy interface to microprocessors. ● SINGLE 5V SUPPLY OPERATION ● ±1/2 LSB LINEARITY ● FOUR-QUADRANT MULTIPLICATION ● DACs MATCHED TO 1% APPLICATIONS ● DIGITALLY CONTROLLED FILTERS Each DAC operates independently with separate reference input pins and internal feedback resistors. Excellent converter-to-converter matching is maintained. The DAC7528 operates from a single +5V power supply. The inputs are TTL-compatible. Package options include 20-pin plastic DIP and SOIC. ● DISK DRIVES ● AUTO CALIBRATION ● MOTOR CONTROL SYSTEMS ● PROGRAMMABLE GAIN/ATTENUATION ● X-Y GRAPHICS VREF A 4 VDD 17 Data DB0 (LSB) 14 Inputs DB7 (MSB) 7 3 RFB A 2 OUT A Input Buffer Latch DAC A 1 AGND DAC7528 DAC A/ DAC B 6 CS 15 WR 16 19 RFB B Control Logic 20 OUT B Latch DAC B DGND 5 18 VREF B International Airport Industrial Park • Mailing Address: PO Box 11400 • Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd. • Tucson, AZ 85706 Tel: (520) 746-1111 • Twx: 910-952-1111 • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 © 1993 Burr-Brown Corporation PDS-1219A Printed in U.S.A. June, 1994 SPECIFICATIONS ELECTRICAL At VDD = +5V; VREFA, B = + 10V; IOUT = GND = 0V: T = Full Temperature Range specification under Absolute Maximum Ratings unless otherwise noted. DAC7528P, U PARAMETER SYMBOL CONDITIONS MIN DAC7528PB, UB TYP MAX ±2 0.001 0.001 ±1 ±1 ±2 ±4 ±35 0.01 0.01 ±50 ±200 ±50 ±200 MIN TYP MAX UNITS – – – ±1/2 ±1/2 ±1 ±2 – – – – – – – Bits LSB LSB LSB LSB ppm/°C %FSR/% %FSR/% nA nA nA nA – – kΩ % – – – – (1) DC ACCURACY Resolution Relative Accuracy Differential Nonlinearity FS Gain Error (2) Gain Tempco (2)(3) Supply Rejection N INL DNL PSR Output Leakage Current (OUTA) Output Leakage Current (OUTB) REFERENCE INPUT Input Resistance Input Resistance Match 10 15 ±1 – COUTB DIGITAL INPUTS Input High Voltage Input Low Voltage Input Current VIH VIL IIN CIN IDD – 180 200 80 100 –90 – ns ns ns ns nVs dB dB dB dB dB –90 – dB 30 –85 – – nVs dB 125 OUTB capacitance (4) 8 VREFA = 20Vpp Sinewave, TA = +25°C 100kHz,VREFB = 0V, TA = TMIN to TMAX VREFA = 20Vpp Sinewave, TA = +25°C 100kHz, VREFB = 0V, TA = TMIN to TMAX VREFA = 20Vpp Sinewave, 100kHz, VREFB = 0V, Both DACs = FF16 VREFB = 20Vpp Sinewave 100kHz, VREFA = 0V, Both DACs = FF16 Measured With Code Transition 0016 to FF16 THD VIN = 6Vrms at 1kHz COUTA POWER REQUIREMENTS Supply Current ∆VDD = ±5%, TA = +25°C TA = TMIN to TMAX DACA = 0016, TA = +25°C TA = TMIN to TMAX DACB = 0016, TA = +25°C TA = TMIN to TMAX 8 Enable Pins Low TA = +25°C Load = 100Ω/13pF, TA = TMIN to TMAX Enable Pins Low TA= +25°C Load = 100Ω/13pF, TA = TMIN to TMAX ANALOG OUTPUTS (4) OUTA capacitance Input Capacitance Guaranteed Monolithic Over Temp TA = +25°C TA = TMIN to TMAX (VREFA, VREFB) (VREFA, VREFB) DYNAMIC PERFORMANCE (4) Output Current Settling Time to 1/2 LSB Digital-to-Analog Propagation Delay to 90% of Output Digital-to-Analog Impulse AC Feedthrough (VREFA to OUTA) AC Feedthrough (VREFB to OUTB) Channel-to-Channel Isolation (VREFA to OUTB) Channel-to-Channel Isolation (VREFB to OUTA) Digital Crosstalk Harmonic Distortion 8 – –70 –65 –70 –65 DAC = 0016 DAC = FF16 DAC = 0016 DAC = FF16 50 120 50 120 – – – – pF pF pF pF TA = +25°C TA = TMIN to TMAX All Digital Inputs 0.8 ±1 ±10 10 – – – – V V µA µA pF Digital Inputs = VIH or VIL, TA = +25°C TA = TMIN to TMAX Digital Inputs = 0V or VDD, TA = +25°C TA = TMIN to TMAX 1 1 100 500 – – – – mA mA µA µA 2.4 SWITCHING CHARACTERISTICS (100% tested) See Timing Diagram TA = +25°C Chip Select To Write Setup Time tCS TA = TMIN to TMAX Chip Select To Write Hold Time tCH TA = +25°C TA = TMIN to TMAX DAC Select To Write Setup Time tAS TA = +25°C TA = TMIN to TMAX DAC Select To Write Hold Time tAH TA = +25°C TA = TMIN to TMAX Write Pulse Width tWR TA = +25°C TA = TMIN to TMAX Data Setup Time tDS TA = +25°C TA = TMIN to TMAX Data Hold Time tDH TA = +25°C 200 230 20 30 200 230 20 30 180 200 110 130 0 – – – – – – – – – – – – – – ns ns ns ns ns ns ns ns ns ns ns ns ns NOTES: (1) Specifications apply to both DACs. (2) Gain error is measured using internal feedback resistor. Full Scale Range (FSR) = VREF. (3) Guaranteed, but not tested. (4) These characteristics are for design guidance only and are not subject to test. ® DAC7528 2 DICE INFORMATION 8 7 6 5 4 3 PAD FUNCTION 9 2 10 1 1 2 3 4 5 6 7 21 12 13 14 15 16 17 RFB A VREF B DGND DAC A/DAC B DB7 DB6 DB5 15 16 17 18 19 20 21 DB4 DB3 DB2 DB1 DB0 CS WR MILS (0.001") MILLIMETERS 104 x 124 20 ±3 4x4 2.6 x 3.1 0.51 ±0.08 0.10 x 0.10 Die Size Die Thickness Min. Pad Size 19 18 8 9 10 11 12 13 14 MECHANICAL INFORMATION 20 11 PAD FUNCTION PAD FUNCTION VDD VREF B RFB B OUTB AGNDB AGNDA OUTA DAC7528 TOPOGRAPHY ELECTRICAL, (DICE) At VDD = +5V; VREFA, B = +10V; IOUT = GND = 0V: T = Full Temperature Range specification under Absolute Maximum Ratings unless otherwise noted. PARAMETER SYMBOL DC ACCURACY (1) Resolution Relative Accuracy Differential Nonlinearity FS Gain Error (2) N INL DNL Gain Tempco (2, 3) Supply Rejection CONDITIONS MIN DAC7528AD TYP MAX UNITS ±1 ±1 ±2 ±4 ±35 0.01 0.01 ±50 ±200 ±50 ±200 Bits LSB LSB LSB LSB ppm/°C %FSR/% %FSR/% nA nA nA nA 15 ±1 kΩ % 8 Guaranteed Monolithic Over Temp TA = +25°C TA = TMIN to TMAX ±2 0.001 0.001 ∆VDD = ±5%, TA = +25°C TA = TMIN to TMAX DACA = 0016 TA = +25°C TA = TMIN to TMAX DACB = 0016 TA = +25°C TA = TMIN to TMAX PSR Output Leakage Current (OUTA) Output Leakage Current (OUTB) REFERENCE INPUT Input Resistance Input Resistance Match (VREF A, VREF B) (VREF A, VREF B) 8 10 NOTES: (1) Specifications apply to both DACs. (2) Gain error is measured using internal feedback resistor. Full Scale Range (FSR) = VREF. (3) Guaranteed, but not tested. (4) These characteristics are for design guidance only and are not subject to test. PACKAGE INFORMATION MODEL PACKAGE DAC7528P DAC7528PB DAC7528U DAC7528UB PIN CONFIGURATION PACKAGE DRAWING NUMBER(1) 20-Pin Plastic DIP 20-Pin Plastic DIP 20-Pin SOIC 20-Pin SOIC Top View 222 222 221 221 NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix D of Burr-Brown IC Data Book. DIP/SOIC AGND 1 20 OUT B OUT A 2 19 RFB B RFB A 3 18 VREF B VREF A 4 17 VDD DGND 5 DAC A/DAC B 6 15 CS (MSB) DB7 7 14 DB0 (LSB) DB6 8 13 DB1 DB5 9 12 DB2 DB4 10 11 DB3 16 WR DAC7528 ORDERING INFORMATION MODEL DAC7528P DAC7528PB DAC7528U DAC7528UB INL PACKAGE ±1LSB ±1/2LSB ±1LSB ±1/2LSB 20-Pin Plastic DIP 20-Pin Plastic DIP 20-Pin SOIC 20-Pin SOIC TEMPERATURE RANGE –40°C –40°C –40°C –40°C to to to to +85°C +85°C +85°C +85°C ® 3 DAC7528 ABSOLUTE MAXIMUM RATINGS WRITE CYCLE TIMING DIAGRAM VDD to GND ................................................................................. 0V, +7V VREFA, B to GND ................................................................................ ±25V RFA,B to GND ................................................................................... ±25V Digital Input Voltage Range ................................................ –0.3V to VDD Output Voltage (pins 2, 20) ................................................ –0.3V to VDD Operating Temperature Range U,P ................................ –40°C to +85°C DICE ............................... 0°C to +70°C Junction Temperature .................................................................. +150°C Storage Temperature ..................................................... –60°C to +150°C Lead Temperature (soldering, 10s) ............................................. +300°C θJA U package ........................................................................ 105°C/W P package ........................................................................... 85°C/W θJC U package ......................................................................... 60°C/W P package .......................................................................... 35°C/W CS tCS tCH DAC A/DAC B tAS tAH VDD 0 VDD 0 tWR WR VDD 0 tDS Data In (DB0-DB7) NOTES: θJA is specified for worst case mounting conditions, i.e., θJA is specified for device in socket for PDIP package. CAUTION: (1) Do not apply voltages higher than VDD or less than GND potential on any terminal except VREFA, B (pins 4 and 18) and RFBA, B (pins 3 and 19). (2) The digital control inputs are zener-protected: however, permanent damage may occur on unprotected units from high-energy electrostatic fields. Keep units in conductive foam at all times until ready to use. (3) Use proper antistatic handling procedures. (4) Absolute Maximum Ratings apply to both packaged devices and DICE. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. VIH VIL tDH VDD Data In Stable 0 NOTE: All input signal rise and fall times are measured from 10% to 90% of VDD. VDD = +5V, tr = tf = 20ns; VDD = +15V, tr = tf = 40ns. Timing measurement reference level is (VIH + VIL)/2. MODE SELECTION TABLE DAC A/DAC B L H X X CS WR DAC A DAC B L L H X L L X H WRITE HOLD HOLD HOLD HOLD WRITE HOLD HOLD ELECTROSTATIC DISCHARGE SENSITIVITY Any integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. Digital Inputs: All digital inputs of the DAC7528 incorporate on-chip ESD protection circuitry. This protection is designed and has been tested to withstand five 2500V positive and negative discharges (100pF in series with 1500Ω) applied to each digital input. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet published specifications. Analog Pins: Each analog pin has been tested to BurrBrown's analog ESD test consisting of five 1000V positive and negative discharges (100pF in series with 1500Ω) applied to each pin. RFB A, VREF A, RFB B, and VREF B show some sensitivity. TYPICAL PERFORMANCE CURVES At VDD = +5V; VREFA,B = +10V; IOUT = GND = 0V: T = Full Temperature Range Specification under Absolute Maximum Ratings unless otherwise noted. SUPPLY CURRENT vs DIGITAL INPUT VOLTAGE DAC7528 GAIN TC 5 7.0 4 6.0 3 Gain TC (ppm/°C) IDD (mA) 5.0 4.0 3.0 2.0 1 0 –1 –2 –3 VDD = +5V 1.0 2 –4 –5 0 0 1.0 2.0 3.0 4.0 –40 VIN (V) 0 20 40 Temperature (°C) ® DAC7528 –20 4 60 80 100 CIRCUIT DESCRIPTION DISCUSSION OF SPECIFICATIONS Figure 1 shows a simplified schematic of one half of a DAC7528. The current from the VREF A pin is switched between IOUT A and AGND by 8 single-pole double-throw CMOS switches. This maintains a constant current in each leg of the ladder regardless of the input code. The input resistance at VREF A is therefore constant and can be driven by either a voltage or current, AC or DC, positive or negative polarity, and have a voltage range up to ±20V. RELATIVE ACCURACY This term, also known as end point linearity or integral linearity, describes the transfer function of analog output to digital input code. Relative accuracy describes the deviation from a straight line, after zero and full scale errors have been adjusted to zero. DIFFERENTIAL NONLINEARITY Differential nonlinearity is the deviation from an ideal 1LSB change in the output when the input code changes by 1LSB. A differential nonlinearity specification of 1LSB maximum guarantees monotonicity. VREF A R R 2R R 2R 2R 2R 2R R RFB A IOUT A GAIN ERROR AGND Gain error is the difference between the full-scale DAC output and the ideal value. The ideal full scale output value for the DAC7528 is –(255/256)VREF . Gain error may be adjusted to zero using external trims as shown in Figure 4. DB7 (MSB) DB6 DB5 DB0 (LSB) FIGURE 1. Equivalent Circuit for DAC A. A CMOS switch transistor, included in series with the ladder terminating resistor and in series with the feedback resistor, RFB A, compensates for the temperature drift of the ON resistance of the ladder switches. OUTPUT LEAKAGE CURRENT The current which appears at IOUT A and IOUT B with the DAC loaded with all zeros. Figure 2 shows an equivalent circuit for DAC A. COUT is the output capacitance due to the N-channel switches and varies from about 30pF to 70pF with digital input code. The current source ILKG is the combination of surface and junction leakages to the substrate. ILKG approximately doubles every 10°C. RO is the equivalent output resistance of the D/A and it varies with input code. OUTPUT CAPACITANCE The parasitic capacitance measured from IOUT A or IOUT B to AGND. CHANNEL-TO-CHANNEL ISOLATION The AC output error due to capacitive coupling from DAC A to DAC B or DAC B to DAC A. R AC FEEDTHROUGH ERROR The AC output error due to capacitive coupling from VREF to IOUT with the DAC loaded with all zeros. RFB A VREF A R DIN VREF x 256 R RO ILKG IOUT A COUT AGND OUTPUT CURRENT SETTLING TIME The time required for the output current to settle to within FIGURE 2. Simplified Circuit Diagram for DAC A. ±0.195% of final value for a full scale step. INSTALLATION DIGITAL-TO-ANALOG IMPULSE ESD PROTECTION All digital inputs of the DAC7528 incorporate on-chip ESD protection circuitry. This protection is designed to withstand 2.5kV (using the Human Body Model, 100pF and 1500Ω). However, industry standard ESD protection methods should be used when handling or storing these components. When not in use, devices should be stored in conductive foam or rails. The foam or rails should be discharged to the destination socket potential before devices are removed. The integrated area of the glitch pulse measured in nanovoltseconds. The key contributor to digital-to-analog glitch is charge injected by digital logic switching transients. DIGITAL CROSSTALK Glitch impulse measured at the output of one DAC but caused by a full scale transition on the other DAC. The integrated area of the glitch pulse is measured in nanovoltseconds. ® 5 DAC7528 POWER SUPPLY CONNECTIONS The DAC7528 is designed to operate on VDD = +5V +10%. For optimum performance and noise rejection, power supply decoupling capacitors CD should be added as shown in the application circuits. These capacitors (1µF tantalum recommended) should be located close to the D/A. AGND and DGND should be connected together at one point only, preferably at the power supply ground point. Separate returns minimize current flow in low-level signal paths if properly connected. Output op amp analog common (+ input) should be connected as near to the AGND pin of the DAC7528 as possible. VDD VREF A +5V CD 1µF VOUT = – DIN 256 RFB A IOUT A C1 10pF DAC A DAC7528 IOUT B DAC B WIRING PRECAUTIONS To minimize AC feedthrough when designing a PC board, care should be taken to minimize capacitive coupling between the VREF lines and the IOUT lines. Similarly, capacitive coupling between DACs may compromise the channel-tochannel isolation. Coupling from any of the digital control or data lines might degrade the glitch and digital crosstalk performance. Solder the DAC7528 directly into the PC board without a socket. Sockets add parasitic capacitance (which can degrade AC performance). – A1 + VOUT A – A2 + VOUT B RFB B AGND C2 10pF A1, A2 OPA602 or 1/2 OPA2107. DGND VREF B FIGURE 3. Unipolar Configuration 2 Quadrant Multiplication. amplifier. If an application requires the D/A to have zero gain error, the circuit shown in Figure 4 may be used. Resistors R2 and R4 induce a positive gain error greater than worst-case initial negative gain error. Trim resistors R1 and R3 provide a variable negative gain error and have sufficient trim range to correct for the worst-case initial positive gain error plus the error produced by R2 and R4. AMPLIFIER OFFSET VOLTAGE The output amplifier used with the DAC7528 should have low input offset voltage to preserve the transfer function linearity. The voltage output of the amplifier has an error component which is the offset voltage of the op amp multiplied by the “noise gain” of the circuit. This “noise gain” is equal to (RF / RO + 1) where RO is the output impedance of the D/A IOUT terminal and RF is the feedback network impedance. The nonlinearity occurs due to the output impedance varying with code. If the 0 code case is excluded (where RO = infinity), the RO will vary from R to 3R providing a “noise gain” variation between 4/3 and 2. In addition, the variation of RO is nonlinear with code, and the largest steps in RO occur at major code transitions where the worst differential nonlinearity is also likely to be experienced. The nonlinearity seen at the amplifier output is 2VOS – 4VOS /3 = 2VOS/3. Thus, to maintain good nonlinearity the op amp offset should be much less than 1/2LSB. BIPOLAR CONFIGURATION Figure 5 shows the DAC7528 in a typical bipolar (fourquadrant) multiplying configuration. The analog output values versus digital input code are listed in Table II. The operational amplifiers used in this circuit can be single amplifiers such as the OPA602, a dual amplifier such as the OPA2107, or a quad amplifier like the OPA404. C1 and C2 provide phase compensation to minimize settling time and overshoot when using a high speed operational amplifier. The bipolar offset resistors R1–R3 and R4–R6 should be ratio-matched to 0.195% to ensure the specified gain error performance. UNIPOLAR CONFIGURATION Figure 3 shows DAC7528 in a typical unipolar (two-quadrant) multiplying configuration. The analog output values versus digital input code are listed in Table I. The operational amplifiers used in this circuit can be single amplifiers such as the OPA602, or a dual amplifier such as the OPA2107. C1 and C2 provide phase compensation to minimize settling time and overshoot when using a high speed operational ® DAC7528 VREF + 6 APPLICATION INFORMATION + DATA INPUT R1 100Ω MSB 1111 1000 0000 0000 V REF A RFB A R2 IOUT A 47Ω C1 10pF ANALOG OUTPUT LSB 1111 0000 0001 0000 –VREF (255/256) –VREF (255/256) = –1/2VREF –VREF (1/256) 0V TABLE I. Unipolar Output Code. – A1 + DAC A → CD 1µF VIN A → VDD +5V VOUT A DATA INPUT 47Ω DAC B AGND V REF B DGND MSB 1111 1000 1000 0111 0000 C2 10pF – A2 + VOUT B → IOUT B → RFB B R4 DAC7528 ANALOG OUTPUT LSB 1111 0001 0000 1111 0000 +VREF (127/128) +VREF (1/128) 0V –VREF (1/128) –VREF (127/128) TABLE II. Bipolar Output Code. A1, A2 OPA602 or 1/2 OPA2107. R3 100Ω V IN B FIGURE 4. Unipolar Configuration with Gain Trim. R1 20k Ω +5V VDD VREF A R2 20k Ω – CD + 1µF A2 R3 10k Ω VOUT A + RFB A C1 10pF IOUT A – A1 DAC A + A1–A4, OPA602 or 1/2 OPA2107. DAC7528 RFB B C2 10pF IOUT B DAC B AGND – A3 + R5 10k Ω R6 20k Ω R4 20k Ω – DGND A4 VOUT B + VREF B FIGURE 5. Bipolar Configuration 4 Quadrant Multiplication. ® 7 DAC7528 APPLICATIONS CIRCUIT: 8-BIT PLUS SIGN DAC +15V 2 +10V 6 The DACs are loaded with same 8-bit word, except that one code is inverted first. If sign bit = 1; invert DAC B’s data. If sign bit = 0; invert DAC A’s data. REF102 +5V 4 VDD CD 1µF VREF A RFB A IOUT A C1 10pF DAC A R A1 R 2 DAC7528 IOUT B DAC B DGND VREF B 6 R RFB B ±10V 9 Bits 3 C2 10pF R A2 AGND INA105 1 A1 OPA602 or 1/2 OPA2107. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® DAC7528 8