µ SLOS270C − MARCH 2001 − REVISED DECEMBER 2003
D
D
D
D
D
D
D
D
D
D
Rail-To-Rail Input/Output
Wide Bandwidth . . . 3 MHz
High Slew Rate . . . 2.4 V/µs
Supply Voltage Range . . . 2.7 V to 16 V
Supply Current . . . 550 µA/Channel
Low Power Shutdown Mode
IDD(SHDN) . . . 25 µA/Channel
Input Noise Voltage . . . 39 nV/√Hz
Input Bias Current . . . 1 pA
Specified Temperature Range
−40°C to 125°C . . . Industrial Grade
Ultrasmall Packaging
− 5 or 6 Pin SOT-23 (TLV2370/1)
− 8 or 10 Pin MSOP (TLV2372/3)
Operational Amplifier
−
+
description
The TLV237x single supply operational amplifiers provide rail-to-rail input and output capability. The TLV237x
takes the minimum operating supply voltage down to 2.7 V over the extended industrial temperature range while
adding the rail-to-rail output swing feature. The TLV237x also provides 3-MHz bandwidth from only 550 µA. The
maximum recommended supply voltage is 16 V, which allows the devices to be operated from (±8 V supplies
down to ±1.35 V) a variety of rechargeable cells.
The CMOS inputs enable use in high-impedance sensor interfaces, with the lower voltage operation making
an ideal alternative for the TLC227x in battery-powered applications. The rail-to-rail input stage further
increases its versatility. The TLV237x is the seventh member of a rapidly growing number of RRIO products
available from TI, and it is the first to allow operation up to 16-V rails with good ac performance.
All members are available in PDIP and SOIC with the singles in the small SOT-23 package, duals in the MSOP,
and quads in the TSSOP package.
The 2.7-V operation makes the TLV237x compatible with Li-Ion powered systems and the operating supply
voltage range of many micro-power microcontrollers available today including TI’s MSP430.
SELECTION OF SIGNAL AMPLIFIER PRODUCTS†
VDD (V)
VIO
(µV)
TLV237x
2.7−16
TLC227x
4−16
DEVICE
GBW
(MHz)
SR
(V/µs)
SHUTDOWN
RAILTORAIL
SINGLES/DUALS/QUADS
1
3
2.4
Yes
I/O
S/D/Q
1
2.2
3.6
—
O
D/Q
Iq/Ch
(µA)
IIB (pA)
500
550
300
1100
TLV27x
2.7−16
500
550
1
3
2.4
—
O
S/D/Q
TLC27x
3−16
1100
675
1
1.7
3.6
—
—
S/D/Q
TLV246x
2.7−6
150
550
1300
6.4
1.6
Yes
I/O
S/D/Q
TLV247x
2.7−6
250
600
2
2.8
1.5
Yes
I/O
S/D/Q
TLV244x
2.7−10
300
† Typical values measured at 5 V, 25°C
725
1
1.8
1.4
—
O
D/Q
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2001 − 2003, Texas Instruments Incorporated
!"#$%&'(!$" !) *+%%,"( ') $# -+./!*'(!$" 0'(,1
%$0+*() *$"#$%& ($ )-,*!#!*'(!$") -,% (, (,%&) $# ,2') ")(%+&,"()
)('"0'%0 3'%%'"(41 %$0+*(!$" -%$*,))!"5 0$,) "$( ",*,))'%!/4 !"*/+0,
(,)(!"5 $# '// -'%'&,(,%)1
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1
µ SLOS270C − MARCH 2001 − REVISED DECEMBER 2003
FAMILY PACKAGE TABLE
PACKAGE TYPES
NUMBER OF
CHANNELS
PDIP
SOIC
SOT-23
TSSOP
MSOP
TLV2370
1
8
8
6
—
—
Yes
TLV2371
1
8
8
5
—
—
—
TLV2372
2
8
8
—
—
8
—
TLV2373
2
14
14
—
—
10
Yes
TLV2374
4
14
14
—
14
—
—
TLV2375
4
16
16
—
16
—
Yes
DEVICE
SHUTDOWN
UNIVERSAL
EVM BOARD
Refer to the EVM
Selection Guide
(Lit# SLOU060)
TLV2370 and TLV2371 AVAILABLE OPTIONS
PACKAGED DEVICES
VIOMAX AT
25°C
TA
−40°C to 125°C
4.5 mV
SOT-23
SMALL OUTLINE
(D)†
(DBV)‡
TLV2370ID
TLV2371ID
PLASTIC DIP
(P)
SYMBOL
TLV2370IDBV
TLV2371IDBV
VBFI
VBGI
TLV2370IP
TLV2371IP
† This package is available taped and reeled. To order this packaging option, add an R suffix to the part number (e.g., TLV2370IDR).
‡ This package is only available taped and reeled. For standard quantities (3,000 pieces per reel), add an R suffix (e.g., TLV2370IDBVR). For
smaller quantities (250 pieces per mini-reel), add a T suffix to the part number (e.g., TLV2370IDBVT).
TLV2372 AND TLV2373 AVAILABLE OPTIONS
PACKAGED DEVICES
TA
−40°C
to
125°C
VIOMAX AT
25°C
4.5 mV
SMALL
OUTLINE
(D)§
(DGK)§
SYMBOL
(DGS)§
TLV2372ID
TLV2373ID
TLV2372IDGK
—
APG
—
—
TLV2373IDGS
SYMBOL
PLASTIC
DIP
(N)
PLASTIC
DIP
(P)
—
API
—
TLV2373IN
TLV2372IP
—
MSOP
§ This package is available taped and reeled. To order this packaging option, add an R suffix to the part number (e.g., TLV2372IDR).
TLV2374 and TLV2375 AVAILABLE OPTIONS
PACKAGED DEVICES
TA
VIOMAX AT
25°C
−40°C to 125°C
4.5 mV
SMALL OUTLINE
(D)¶
PLASTIC DIP
(N)
TSSOP
(PW)¶
TLV2374ID
TLV2375ID
TLV2374IN
TLV2375IN
TLV2374IPW
TLV2375IPW
¶ This package is available taped and reeled. To order this packaging option, add an R suffix to the part number
(e.g., TLV2374IDR).
2
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•
µ SLOS270C − MARCH 2001 − REVISED DECEMBER 2003
TLV237x PACKAGE PINOUTS(1)
TLV2370
D OR P PACKAGE
(TOP VIEW)
TLV2370
DBV PACKAGE
(TOP VIEW)
OUT
1
6
VDD
GND
2
5
SHDN
IN+
3
4
IN −
TLV2371
D OR P PACKAGE
(TOP VIEW)
NC
IN −
IN +
GND
1OUT
1IN −
1IN+
GND
NC
1SHDN
NC
1
8
2
7
3
6
4
5
NC
IN −
IN +
GND
1
8
2
7
3
6
4
5
TLV2371
DBV PACKAGE
(TOP VIEW)
SHDN
VDD
OUT
NC
1OUT
1IN −
1IN +
GND
1
8
2
7
3
6
4
5
TLV2374
D, N, OR PW PACKAGE
(TOP VIEW)
(TOP VIEW)
14
13
3
12
4
5
6
7
11
10
9
8
GND
2
IN+
3
VDD
2OUT
2IN −
2IN+
NC
2SHDN
NC
1OUT
1IN −
1IN+
VDD
2IN+
2IN −
2OUT
1
14
2
13
3
12
4
11
5
10
6
9
7
8
5
VDD
4
IN −
TLV2373
DGS PACKAGE
(TOP VIEW)
VDD
2OUT
2IN −
2IN+
TLV2373
D OR N PACKAGE
2
1
TLV2372
D, DGK, OR P PACKAGE
(TOP VIEW)
NC
VDD
OUT
NC
1
OUT
1OUT
1IN −
1IN+
GND
1SHDN
1
2
3
4
5
10
9
8
7
6
VDD
2OUT
2IN −
2IN+
2SHDN
TLV2375
D, N, OR PW PACKAGE
(TOP VIEW)
4OUT
4IN −
4IN+
GND
3IN+
3IN −
3OUT
1OUT
1IN −
1IN+
VDD+
2IN+
2IN −
2OUT
1SHDN
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
4OUT
4IN −
4IN+
GND
3IN +
3IN−
3OUT
2SHDN
NC − No internal connection
(1) SOT−23 may or may not be indicated
TYPICAL PIN 1 INDICATORS
Pin 1
Printed or
Molded Dot
Pin 1
Pin 1
Bevel Edges
Stripe
Pin 1
Molded ”U” Shape
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•
3
µ SLOS270C − MARCH 2001 − REVISED DECEMBER 2003
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.5 V
Differential input voltage, VID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± VDD
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.2 V to VDD + 0.2 V
Input current range, II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 10 mA
Output current range, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 100 mA
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating free-air temperature range, TA: I suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 125°C
Maximum junction temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values, except differential voltages, are with respect to GND.
DISSIPATION RATING TABLE
PACKAGE
θJC
(°C/W)
θJA
(°C/W)
TA ≤ 25°C
POWER RATING
D (8)
38.3
176
710 mW
D (14)
26.9
122.3
1022 mW
D (16)
25.7
114.7
1090 mW
DBV (5)
55
324.1
385 mW
DBV (6)
55
294.3
425 mW
DGK (8)
54.23
259.96
481 mW
DGS (10)
54.1
257.71
485 mW
N (14, 16)
32
78
1600 mW
P (8)
41
104
1200 mW
PW (14)
29.3
173.6
720 mW
PW (16)
28.7
161.4
774 mW
recommended operating conditions
Single supply
Supply voltage, VDD
Split supply
Common-mode input voltage range, VICR
Operating free-air temperature, TA
I-suffix
MIN
MAX
2.7
16
±1.35
±8
0
VDD
125
°C
2
V
−40
Turnon voltage level, V(ON), relative to GND pin voltage
Turnoff voltage level, V(OFF), relative to GND pin voltage
4
0.8
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•
UNIT
V
V
V
µ SLOS270C − MARCH 2001 − REVISED DECEMBER 2003
electrical characteristics at specified free-air temperature, VDD = 2.7 V, 5 V, and 15 V (unless
otherwise noted)
dc performance
PARAMETER
TEST CONDITIONS
TA
MIN
25°C
VIO
Input offset voltage
αVIO
Offset voltage drift
VO = VDD/2,
VIC = VDD/2,
RS = 50 Ω
VIC = 0 to VDD−1.35V,
RS = 50 Ω
CMRR
Common-mode rejection ratio
VIC = 0 to VDD,
RS = 50 Ω,
VIC = 0 to VDD−1.35V,
RS = 50 Ω,
VIC = 0 to VDD,
RS = 50 Ω,
VIC = 0 to VDD−1.35V,
RS = 50 Ω,
VDD = 2.7 V
VDD = 5 V
VDD = 15 V
VDD = 2.7 V
AVD
Large-signal differential voltage
amplification
VO(PP) = VDD/2,
RL = 10 kkΩ
MAX
2
4.5
6
Full range
25°C
VIC = 0 to VDD,
RS = 50 Ω
TYP
50
Full range
49
25°C
56
Full range
54
25°C
55
Full range
54
25°C
67
Full range
64
25°C
64
Full range
63
25°C
67
Full range
66
25°C
98
Full range
76
25°C
100
VDD = 5 V
Full range
86
25°C
81
VDD = 15 V
Full range
79
mV
V/°C
µV/°C
2
25°C
UNIT
68
70
72
dB
80
82
84
106
110
dB
83
input characteristics
PARAMETER
IIO
TEST CONDITIONS
Input offset current
VDD = 15 V,
VO = VDD/2
IIB
VIC = VDD/2,
Differential input resistance
CIC
Common-mode input capacitance
f = 21 kHz
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MIN
TYP
1
MAX
70°C
100
1000
1
UNIT
60
125°C
25°C
Input bias current
ri(d)
TA
25°C
pA
60
70°C
100
125°C
1000
pA
25°C
1000
GΩ
25°C
8
pF
5
µ SLOS270C − MARCH 2001 − REVISED DECEMBER 2003
electrical characteristics at specified free-air temperature, VDD = 2.7 V, 5 V, and 15 V (unless
otherwise noted) (continued)
output characteristics
PARAMETER
TEST CONDITIONS
VIC = VDD/2, IOH = −1 mA
TA
MIN
TYP
25°C
2.55
2.58
VDD = 2.7 V
Full range
2.48
25°C
4.9
VDD = 5 V
Full range
4.85
25°C
14.92
Full range
14.9
25°C
1.9
Full range
1.6
25°C
4.6
VDD = 5 V
Full range
4.5
25°C
14.7
VDD = 15 V
Full range
14.6
VDD = 15 V
VOH
High-level output voltage
VDD = 2.7 V
VIC = VDD/2, IOH = −5 mA
25°C
VDD = 2.7 V
Full range
VDD = 15 V
Full range
Low-level output voltage
VDD = 5 V
0.05
IO
Output current
VDD = 5 V,
VO = 0.5 V from rail
VDD = 15 V, VO = 0.5 V from rail
0.15
0.1
0.08
0.1
0.52
Full range
0.7
V
1.1
0.28
Full range
0.4
0.5
25°C
VDD = 2.7 V, VO = 0.5 V from rail
14.8
0.15
25°C
VIC = VDD/2, IOL = 5 mA
4.68
0.22
25°C
VDD = 2.7 V
V
2
0.05
25°C
VOL
14.96
Full range
VDD = 5 V
UNIT
4.93
0.1
25°C
VIC = VDD/2, IOL = 1 mA
MAX
0.19
VDD = 15 V
Full range
Positive rail
25°C
4
Negative rail
25°C
5
Positive rail
25°C
7
Negative rail
25°C
8
Positive rail
25°C
16
Negative rail
25°C
15
0.3
0.35
mA
power supply
PARAMETER
IDD
Supply current (per channel)
TEST CONDITIONS
VDD = 2.7 V
VDD = 5 V
VO = VDD/2,
VDD = 15 V
PSRR
6
Supply voltage rejection ratio
(∆VDD /∆VIO)
VDD = 2.7 V to 15 V,
No load
VIC = VDD /2,
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•
TA
25°C
MIN
TYP
MAX
470
560
25°C
550
660
25°C
750
900
Full range
UNIT
µA
1200
25°C
70
Full range
65
80
dB
µ SLOS270C − MARCH 2001 − REVISED DECEMBER 2003
electrical characteristics at specified free-air temperature, VDD = 2.7 V, 5 V, and 15 V (unless
otherwise noted) (continued)
dynamic performance
PARAMETER
UGBW
TEST CONDITIONS
Unity gain bandwidth
RL = 2 kΩ,
CL = 10 pF
TA
2.4
VDD = 5 V to 15 V
25°C
3
25°C
φm
ts
Slew rate at unity gain
VO(PP) = VDD/2,
CL = 50 pF,
RL = 10 kΩ
TYP
25°C
VDD = 2.7 V
SR
MIN
VDD = 2.7 V
1.4
Full range
25°C
1.6
Full range
1.2
25°C
1.9
VDD = 15 V
Full range
1.4
2
V/ s
V/µs
2.4
V/ s
V/µs
2.1
V/ s
V/µs
Phase margin
RL = 2 kΩ,
CL = 100 pF
25°C
65°
Gain margin
RL = 2 kΩ,
CL = 10 pF
25°C
18
Settling time
VDD = 2.7 V,
V(STEP)PP = 1 V,
CL = 10 pF,
VDD = 5 V, 15 V,
V(STEP)PP = 1 V,
CL = 47 pF,
0.1%
AV = −1,
RL = 2 kΩ
0.1%
UNIT
MHz
1
VDD = 5 V
AV = −1,
RL = 2 kΩ
MAX
dB
2.9
µss
25°C
2
noise/distortion performance
PARAMETER
TEST CONDITIONS
VDD = 2.7 V,
VO(PP) = VDD/2 V,
RL = 2 kΩ,
k , f = 10 kHz
THD + N
Total harmonic distortion plus noise
VDD = 5 V, 15 V,
VO(PP) = VDD/2 V,
RL = 2 kΩ,
k , f = 10 kHz
AV = 1
AV = 10
TA
MIN
Equivalent input noise voltage
In
Equivalent input noise current
UNIT
0.05%
25°C
25
C
0.18%
0.02%
0.09%
25°C
25
C
0.5%
f = 1 kHz
Vn
MAX
0.02%
AV = 100
AV = 1
AV = 10
AV = 100
TYP
39
25°C
f = 10 kHz
f = 1 kHz
nV/√Hz
35
25°C
0.6
fA /√Hz
shutdown characteristics
PARAMETER
IDD(SHDN)
t(on)
t(off)
TEST CONDITIONS
VDD = 2.7 V, 5 V,
SHDN = 0 V
Supply current in shutdown mode (TLV2370,
TLV2373, TLV2375) (per channel)
VDD = 15 V,
SHDN = 0 V
Amplifier turnon time (see Note 2)
RL = 2 kΩ
Amplifier turnoff time (see Note 2)
TA
25°C
MIN
TYP
MAX
25
30
Full range
25°C
35
40
Full range
45
50
UNIT
µA
A
A
µA
25°C
0.8
µs
25°C
1
µs
NOTE 2: Disable time and enable time are defined as the interval between application of the logic signal to the SHDN terminal and the point at
which the supply current has reached one half of its final value.
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7
µ SLOS270C − MARCH 2001 − REVISED DECEMBER 2003
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
VIO
CMRR
Input offset voltage
vs Common-mode input voltage
Common-mode rejection ratio
vs Frequency
4
Input bias and offset current
vs Free-air temperature
5
VOL
VOH
Low-level output voltage
vs Low-level output current
6, 8, 10
High-level output voltage
vs High-level output current
7, 9, 11
VO(PP)
IDD
Peak-to-peak output voltage
vs Frequency
12
Supply current
vs Supply voltage
13
PSRR
Power supply rejection ratio
vs Frequency
14
AVD
Differential voltage gain & phase
vs Frequency
15
Gain-bandwidth product
vs Free-air temperature
16
vs Supply voltage
17
vs Free-air temperature
18
19
SR
Slew rate
φm
Vn
Phase margin
vs Capacitive load
Equivalent input noise voltage
vs Frequency
1, 2, 3
20
Voltage-follower large-signal pulse response
21, 22
Voltage-follower small-signal pulse response
23
Inverting large-signal response
24, 25
Inverting small-signal response
26
Crosstalk
vs Frequency
27
Shutdown forward & reverse isolation
vs Frequency
28
IDD(SHDN)
IDD(SHDN)
Shutdown supply current
vs Supply voltage
29
Shutdown pin leakage current
vs Shutdown pin voltage
IDD(SHDN)
Shutdown supply current/output voltage
vs Time
8
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30
31, 32
µ SLOS270C − MARCH 2001 − REVISED DECEMBER 2003
TYPICAL CHARACTERISTICS
INPUT OFFSET VOLTAGE
vs
COMMON-MODE INPUT VOLTAGE
INPUT OFFSET VOLTAGE
vs
COMMON-MODE INPUT VOLTAGE
1000
800
600
400
200
0
1000
VDD = 5 V
TA = 25 °C
800
600
400
200
0
−200
−200
0.4
0.8
1.2
1.6
2
0
VICR − Common-Mode Input Voltage − V
100
VDD = 5 V, 15 V
80
VDD = 2.7 V
40
20
100 k
10 k
250
200
150
100
50
0
−40 −25 −10 5
1M
TA = 70°C
TA = 25°C
0.80
TA = 0°C
0.40
0
4.50
4
3.50
1 2 3 4 5 6 7 8 9 10 11 12
IOH − High-Level Output Current − mA
Figure 7
1.60
1.20
TA = 70 °C
TA = 25 °C
0.80
0.40
TA = 125 °C
TA = 70 °C
2.50
TA = 25 °C
2
1.50
1
TA = 0 °C
TA = 40 °C
2 4 6 8 10 12 14 16 18 20 22 24
IOL − Low-Level Output Current − mA
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
5
VDD = 5 V
3
TA = 0 °C
TA = −40 °C
0.50
0
0
TA = 125 °C
Figure 6
V OH − High-Level Output Voltage − V
TA = 125°C
14 15
2
0
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
VOL − Low-Level Output Voltage − V
TA =−40°C
12
0
20 35 50 65 80 95 110 125
5
2.40
10
VDD = 2.7 V
2.40
Figure 5
VDD = 2.7 V
8
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
TA − Free-Air Temperature − °C
2.80
6
2.80
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
1.20
4
Figure 3
VDD = 2.7 V, 5 V and 15 V
VIC = VDD/2
Figure 4
1.60
2
VICR − Common-Mode Input Voltage −V
300
f − Frequency − Hz
2
0
0
−50
0
1k
200
INPUT BIAS/OFFSET CURRENT
vs
FREE-AIR TEMPERATURE
I IB / I IO − Input Bias / Offset Current − pA
120
100
400
Figure 2
COMMON-MODE REJECTION RATIO
vs
FREQUENCY
10
600
1
2
3
4
5
VICR − Common-Mode Input Voltage − V
Figure 1
60
VDD =15 V
TA = 25 °C
800
−200
2.4 2.7
VOL − Low-Level Output Voltage − V
0
CMRR − Common-Mode Rejection Ratio − dB
V IO − Input Offset Voltage − µV
VDD = 2.7 V
TA = 25°C
V IO − Input Offset Voltage − µV
V IO − Input Offset Voltage − µV
1000
V OH − High-Level Output Voltage − V
INPUT OFFSET VOLTAGE
vs
COMMON-MODE INPUT VOLTAGE
VCC = 5 V
4.50
TA = −40°C
4
TA = 0°C
3.50
3
2.50
TA = 25°C
2
1.50
TA = 70°C
1
TA = 125°C
0.50
0
0 5 10 15 20 25 30 35 40 45 50 55 60 65 70
IOL − Low-Level Output Current − mA
Figure 8
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0
5
10
15
20
25
30
35
40
45
IOH − High-Level Output Current − mA
Figure 9
9
µ SLOS270C − MARCH 2001 − REVISED DECEMBER 2003
TYPICAL CHARACTERISTICS
12
TA =70°C
10
TA =25°C
8
TA =0°C
6
TA =−40°C
4
2
15
14
VDD = 15 V
12
TA = −40°C
V O(PP) − Peak-to-Peak Output Voltage − V
VDD = 15 V
TA =125°C
V OH − High-Level Output Voltage − V
VOL − Low-Level Output Voltage − V
15
14
PEAK-TO-PEAK OUTPUT VOLTAGE
vs
FREQUENCY
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
10
TA = 0°C
8
6
TA = 25°C
4
TA = 70°C
TA = 125°C
2
0
0
0
0
20 40 60 80 100 120 140 160
IOL − Low-Level Output Current − mA
20
40
60
80
VDD = 2.7 V
100
AV = 1
VIC = VDD / 2
TA = 70°C
0.7
0.6
0.5
0.4
TA = 25°C
0.3
TA = 0°C
0.2
TA = −40°C
0.1
0
120
TA = 25°C
100
VDD = 5 V, 15 V
80
VDD = 2.7 V
60
40
20
0
10
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
VCC − Supply Voltage − V
100
1k
Phase
60
45
40
0
Gain
−45
20
−90
VDD=5 Vdc
RL=2 kΩ
CL=10 pF
TA=25°C
100
1k
Phase − °
90
−135
10 k
100 k 1 M
−180
10 M
GBWP − Gain Bandwidth Product − MHz
4
135
100
−40
10
1M
GAIN BANDWIDTH PRODUCT
vs
FREE-AIR TEMPERATURE
180
120
−20
100 k
Figure 14
DIFFERENTIAL VOLTAGE GAIN AND PHASE
vs
FREQUENCY
0
10 k
f − Frequency − Hz
Figure 13
80
10 k
POWER SUPPLY REJECTION RATIO
vs
FREQUENCY
TA = 125°C
0.8
1k
3.5
VDD = 15 V
3
2.5
2
VDD = 5 V
VDD = 2.7 V
1.5
1
0.5
0
−40 −25 −10 5
20 35 50 65 80 95 110 125
TA − Free-Air Temperature − °C
f − Frequency − Hz
Figure 16
Figure 15
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100 k
f − Frequency − Hz
Figure 12
PSRR − Power Supply Rejection Ratio − dB
I DD − Supply Current − mA/Ch
VDD = 5 V
Figure 11
1
AVD − Differential Voltage Gain − dB
AV = −10
RL = 2 kΩ
CL = 10 pF
TA = 25°C
THD = 5%
10
100 120 140 160
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
10
VDD = 15 V
IOH − High-Level Output Current − mA
Figure 10
0.9
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1M
10 M
µ SLOS270C − MARCH 2001 − REVISED DECEMBER 2003
TYPICAL CHARACTERISTICS
SLEW RATE
vs
FREE-AIR TEMPERATURE
3.5
3
100
SR−
SR+
1
AV = 1
RL = 10 kΩ
CL = 50 pF
TA = 25°C
0.5
8.5
10.5
12.5
1.5
VDD = 5 V
AV = 1
RL = 10 kΩ
CL = 50 pF
VI = 3 V
1
0
−40 −25 −10 5
14.5
50
40
Rnull = 0
30
Rnull = 50
20
10
0
20 35 50 65 80 95 110 125
10
100
CL − Capacitive Load − pF
Figure 18
Figure 17
1000
Figure 19
EQUIVALENT INPUT NOISE VOLTAGE
vs
FREQUENCY
VOLTAGE-FOLLOWER LARGE-SIGNAL
PULSE RESPONSE
100
V − Input Voltage − V
I
Hz
Rnull = 100
60
TA − Free-Air Temperature − °C
VCC − Supply Voltage −V
VDD = 2.7, 5, 15 V
TA = 25°C
90
70
80
70
60
50
4
3
2
1
VDD = 5 V
AV = 1
RL = 2 kΩ
CL = 10 pF
VI = 3 VPP
TA = 25°C
VI
0
4
40
3
30
2
20
1
VO
10
0
0
10
100
1k
10 k
f − Frequency − Hz
100 k
0
2
VOLTAGE-FOLLOWER LARGE-SIGNAL
PULSE RESPONSE
0
VI
12
9
6
3
VO
0
0
2
4
6
8
10 12 14 16 18
V − Input Voltage − mV
I
9
VDD = 15 V
AV = 1
RL = 2 kΩ
CL = 10 pF
VI = 9 VPP
TA = 25°C
8
10 12 14 16 18
VOLTAGE-FOLLOWER SMALL-SIGNAL
PULSE RESPONSE
12
3
6
Figure 21
Figure 20
6
4
t − Time − µs
0.12
0.08
0.04
0
VI
VDD = 5 V
AV = 1
RL = 2 kΩ
CL = 10 pF
VI = 100 mVPP
TA = 25°C
0.12
0.08
0.04
VO
0
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8
t − Time − µs
t − Time − µs
Figure 22
Figure 23
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V − Output Voltage − mV
O
6.5
SR+
V − Output Voltage − V
O
4.5
V n − Equivalent Input Noise Voltage − nV/
2.5
2
0.5
0
80
SR−
2.5
Phase Margin − °
SR − Slew Rate − V/ µs
1.5
V − Input Voltage − V
I
SR − Slew Rate − V/ µs
2
VDD = 5 V
RL= 2 kΩ
TA = 25°C
AV = Open Loop
90
3
2.5
PHASE MARGIN
vs
CAPACITIVE LOAD
V − Output Voltage − V
O
SLEW RATE
vs
SUPPLY VOLTAGE
11
µ SLOS270C − MARCH 2001 − REVISED DECEMBER 2003
TYPICAL CHARACTERISTICS
INVERTING LARGE-SIGNAL RESPONSE
VI
3
VDD = 5 V
AV = 1
RL = 2 kΩ
CL = 10 pF
VI = 3 VPP
TA = 25°C
2
1
0
3
2
1
0
VO
0
2
4
6
8
10
12
14
12
9
VDD = 15 V
AV = −1
RL = 2 kΩ
CL = 10 pF
VI = 9 Vpp
TA = 25°C
6
3
0
0
16
0
2
4
VDD = 5 V
AV = −1
RL = 2 kΩ
CL = 10 pF
VI = 100 mVpp
TA = 25°C
16
0.1
VO
0.5 1 1.5 2 2.5 3 3.5 4 4.5
−60
−80
Crosstalk in Shutdown
−100
−120
Crosstalk
−140
10
I DD − Shutdown Supply Current − µ A/Ch
160
VDD = 2.7 V, 5 V & 15 V
VI = VDD /2
RL = 2 kΩ
CL= 10 pF
AV = 1
TA = 25°C
80
60
40
20
1k
10 k 100 k 1 M
f − Frequency − Hz
Figure 28
1M
SHUTDOWN PIN LEAKAGE CURRENT
vs
SHUTDOWN PIN VOLTAGE
SHUTDOWN SUPPLY CURRENT
vs
SUPPLY VOLTAGE
50
45
40
SHDN = 0 V
VI = VDD/2
AV = 1
TA = 125°C
35
30
TA = 70°C
25
TA = 25°C
20
15
10
TA = 0°C
TA = −40°C
5
0
0
100 k
Figure 27
Figure 26
SHUTDOWN FORWARD AND
REVERSE ISOLATION
vs
FREQUENCY
100
1k
10 k
f − Frequency −Hz
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
VDD − Supply Voltage − V
Figure 29
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I DD − Shutdown Pin Leakage Current − pA
0
−40
VI
Crosstalk − dB
0.05
V O − Output Voltage − V
V I − Input Voltage − V
14
VDD = 2.7, 5, & 15 V
VI = VDD/2
AV = 1
RL = 2 kΩ
TA = 25°C
−20
t − Time − µs
Shutdown Forward and Reverse Isolation − dB
12
CROSSTALK
vs
FREQUENCY
0.10
0
12
10
0
0
100
8
Figure 25
0.05
10
6
t − Time − µs
INVERTING SMALL-SIGNAL RESPONSE
100
6
3
Figure 24
120
9
VO
t − Time − µs
140
VI
V O − Output Voltage − V
V I − Input Voltage − V
4
VO − Output Voltage − V
V − Input Voltage − V
I
INVERTING LARGE-SIGNAL RESPONSE
250
TA = 125°C
200
150
100
50
0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Shutdown Pin Voltage − V
Figure 30
µ SLOS270C − MARCH 2001 − REVISED DECEMBER 2003
SHUTDOWN SUPPLY CURRENT/OUTPUT VOLTAGE
vs
TIME
SHUTDOWN SUPPLY CURRENT/OUTPUT VOLTAGE
vs
TIME
10
6
VDD = 15 V
AV = 1
RL = 2 kΩ
CL = 10 pF
VI = VDD/2
TA = 25° C
8
6
4
SHDN − Shutdown Pulse − V
SHDN − Shutdown Pulse − V
TYPICAL CHARACTERISTICS
SHDN
2
0
5
VDD = 5 V
AV = 1
RL = 2 kΩ
CL = 10 pF
VI = VDD/2
TA = 25° C
4
3
2
SHDN
1
0
V O − Output Voltage − V
6
4.5
VO
3
1.5
0
I DD − Supply Current − mA/Ch
I DD − Supply Current − mA/Ch
V O − Output Voltage − V
7.5
−1.5
1
0.75
IDD(SHDN = 0)
0.50
0.25
0
−0.25
−40
−20
0
20
40
60
80
100
120
140
2.5
1.5
1
0.5
0
−0.5
−1.0
1
0.75
0.50
IDD(SHDN = 0)
0.25
0
−0.25
−2
160
VO
2
−1
0
1
2
3
4
5
6
7
8
9
10
t − Time − µs
t − Time − µs
Figure 32
Figure 31
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µ SLOS270C − MARCH 2001 − REVISED DECEMBER 2003
APPLICATION INFORMATION
rail-to-rail input operation
The TLV237x input stage consists of two differential transistor pairs, NMOS and PMOS, that operate together
to achieve rail-to-rail input operation. The transition point between these two pairs can be seen in Figures 1,
2, and 3 for a 2.7-V, 5-V, and 15-V supply. As the common-mode input voltage approaches the positive supply
rail, the input pair switches from the PMOS differential pair to the NMOS differential pair. This transition occurs
approximately 1.35 V from the positive rail and results in a change in offset voltage due to different device
characteristics between the NMOS and PMOS pairs. If the input signal to the device is large enough to swing
between both rails, this transition results in a reduction in common-mode rejection ratio (CMRR). If the input
signal does not swing between both rails, it is best to bias the signal in the region where only one input pair is
active. This is the region in Figures 1 through 3 where the offset voltage varies slightly across the input range
and optimal CMRR can be achieved. This has the greatest impact when operating from a 2.7-V supply voltage.
driving a capacitive load
When the amplifier is configured in this manner, capacitive loading directly on the output decreases the device’s
phase margin leading to high frequency ringing or oscillations. Therefore, for capacitive loads of greater than
10 pF, it is recommended that a resistor be placed in series (RNULL) with the output of the amplifier, as shown
in Figure 33. A minimum value of 20 Ω should work well for most applications.
RF
RG
RNULL
−
Input
Output
+
CLOAD
VDD/2
Figure 33. Driving a Capacitive Load
offset voltage
The output offset voltage, (VOO) is the sum of the input offset voltage (VIO) and both input bias currents (IIB) times
the corresponding gains. The following schematic and formula can be used to calculate the output offset
voltage:
RF
IIB−
RG
+
−
VI
IIB+
V
OO
+V
IO
ǒ ǒ ǓǓ
1)
R
R
F
VO
+
RS
"I
G
IB)
R
S
ǒ ǒ ǓǓ
1)
R
R
F
G
"I
IB–
Figure 34. Output Offset Voltage Model
14
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F
µ SLOS270C − MARCH 2001 − REVISED DECEMBER 2003
APPLICATION INFORMATION
general configurations
When receiving low-level signals, limiting the bandwidth of the incoming signals into the system is often
required. The simplest way to accomplish this is to place an RC filter at the noninverting terminal of the amplifier
(see Figure 35).
RG
RF
VDD/2
−
VO
+
VI
R1
C1
f
V
O +
V
I
ǒ
1)
R
R
F
G
–3dB
Ǔǒ
+
1
2pR1C1
Ǔ
1
1 ) sR1C1
Figure 35. Single-Pole Low-Pass Filter
If even more attenuation is needed, a multiple pole filter is required. The Sallen-Key filter can be used for this
task. For best results, the amplifier should have a bandwidth that is 8 to 10 times the filter frequency bandwidth.
Failure to do this can result in phase shift of the amplifier.
C1
+
_
VI
R1
R1 = R2 = R
C1 = C2 = C
Q = Peaking Factor
(Butterworth Q = 0.707)
R2
f
C2
RG
RF
–3dB
RG =
+
(
1
2pRC
RF
1
2−
Q
)
VDD/2
Figure 36. 2-Pole Low-Pass Sallen-Key Filter
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µ SLOS270C − MARCH 2001 − REVISED DECEMBER 2003
APPLICATION INFORMATION
circuit layout considerations
To achieve the levels of high performance of the TLV237x, follow proper printed-circuit board design techniques.
A general set of guidelines is given in the following.
D Ground planes—It is highly recommended that a ground plane be used on the board to provide all
components with a low inductive ground connection. However, in the areas of the amplifier inputs and
output, the ground plane can be removed to minimize the stray capacitance.
D Proper power supply decoupling—Use a 6.8-µF tantalum capacitor in parallel with a 0.1-µF ceramic
capacitor on each supply terminal. It may be possible to share the tantalum among several amplifiers
depending on the application, but a 0.1-µF ceramic capacitor should always be used on the supply terminal
of every amplifier. In addition, the 0.1-µF capacitor should be placed as close as possible to the supply
terminal. As this distance increases, the inductance in the connecting trace makes the capacitor less
effective. The designer should strive for distances of less than 0.1 inches between the device power
terminals and the ceramic capacitors.
D Sockets—Sockets can be used but are not recommended. The additional lead inductance in the socket pins
will often lead to stability problems. Surface-mount packages soldered directly to the printed-circuit board
is the best implementation.
D Short trace runs/compact part placements—Optimum high performance is achieved when stray series
inductance has been minimized. To realize this, the circuit layout should be made as compact as possible,
thereby minimizing the length of all trace runs. Particular attention should be paid to the inverting input of
the amplifier. Its length should be kept as short as possible. This helps to minimize stray capacitance at the
input of the amplifier.
D Surface-mount passive components—Using surface-mount passive components is recommended for high
performance amplifier circuits for several reasons. First, because of the extremely low lead inductance of
surface-mount components, the problem with stray series inductance is greatly reduced. Second, the small
size of surface-mount components naturally leads to a more compact layout thereby minimizing both stray
inductance and capacitance. If leaded components are used, it is recommended that the lead lengths be
kept as short as possible.
shutdown function
Three members of the TLV237x family (TLV2370/3/5) have a shutdown terminal for conserving battery life in
portable applications. When the shutdown terminal is tied low, the supply current is reduced to 25 µA/channel,
the amplifier is disabled, and the outputs are placed in a high impedance mode. To enable the amplifier, the
shutdown terminal can either be left floating or pulled high. When the shutdown terminal is left floating, care
should be taken to ensure that parasitic leakage current at the shutdown terminal does not inadvertently place
the operational amplifier into shutdown.
16
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APPLICATION INFORMATION
general power dissipation considerations
For a given θJA, the maximum power dissipation is shown in Figure 37 and is calculated by the following formula:
P
D
+
Where:
ǒ
T
Ǔ
–T
MAX A
q
JA
PD = Maximum power dissipation of TLV237x IC (watts)
TMAX = Absolute maximum junction temperature (150°C)
TA
= Free-ambient air temperature (°C)
θJA = θJC + θCA
θJC = Thermal coefficient from junction to case
θCA = Thermal coefficient from case to ambient air (°C/W)
MAXIMUM POWER DISSIPATION
vs
FREE-AIR TEMPERATURE
2
Maximum Power Dissipation − W
1.75
PDIP Package
Low-K Test PCB
θJA = 104°C/W
1.5
1.25
TJ = 150°C
MSOP Package
Low-K Test PCB
θJA = 260°C/W
SOIC Package
Low-K Test PCB
θJA = 176°C/W
1
0.75
0.5
0.25
SOT-23 Package
Low-K Test PCB
θJA = 324°C/W
0
−55 −40 −25 −10 5
20 35 50 65 80 95 110 125
TA − Free-Air Temperature − °C
NOTE A: Results are with no air flow and using JEDEC Standard Low-K test PCB.
Figure 37. Maximum Power Dissipation vs Free-Air Temperature
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17
MECHANICAL DATA
MPDI001A – JANUARY 1995 – REVISED JUNE 1999
P (R-PDIP-T8)
PLASTIC DUAL-IN-LINE
0.400 (10,60)
0.355 (9,02)
8
5
0.260 (6,60)
0.240 (6,10)
1
4
0.070 (1,78) MAX
0.325 (8,26)
0.300 (7,62)
0.020 (0,51) MIN
0.015 (0,38)
Gage Plane
0.200 (5,08) MAX
Seating Plane
0.010 (0,25) NOM
0.125 (3,18) MIN
0.100 (2,54)
0.021 (0,53)
0.015 (0,38)
0.430 (10,92)
MAX
0.010 (0,25) M
4040082/D 05/98
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001
For the latest package information, go to http://www.ti.com/sc/docs/package/pkg_info.htm
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MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
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