TLC080-Q1, TLC081-Q1 TLC082-Q1, TLC083-Q1 TLC084-Q1, TLC085-Q1 SLOS510B – SEPTEMBER 2006 – REVISED MAY 2011 www.ti.com WIDE-BANDWIDTH HIGH-OUTPUT-DRIVE SINGLE-SUPPLY OPERATIONAL AMPLIFIERS Check for Samples: TLC080-Q1, TLC081-Q1, TLC082-Q1, TLC083-Q1, TLC084-Q1, TLC085-Q1 FEATURES • • • 1 • • 23 • • • • Wide Bandwidth...10 MHz High Output Drive – IOH...57 mA at VDD –1.5 V – IOL...55 mA at 0.5 V High Slew Rate – SR+...16 V/μs – SR−...19 V/μs Wide Supply Range...4.5 V to 16 V Supply Current...1.9 mA/Channel Ultralow-Power Shutdown Mode IDD...125 μ/Channel Low Input Noise Voltage...8.5 nV√Hz Input Offset Voltage...60 μV Ultra-Small Packages 8- or 10-Pin MSOP (TLC080/081/082/083) (1) Operational Amplifier − + (1) TLC080/081/083 in Product Preview DESCRIPTION The first members of TI’s new BiMOS general-purpose operational amplifier family are the TLC08x. The BiMOS family concept is simple—provide an upgrade path for BiFET users who are moving away from dual-supply to single-supply systems and demand higher ac and dc performance. With performance rated from 4.5 V to 16 V across an automotive temperature range (–40°C to 125°C), BiMOS suits a wide range of audio, automotive, industrial, and instrumentation applications. Familiar features, such as offset nulling pins, and new features, such as MSOP PowerPAD™ packages and shutdown modes, enable higher levels of performance in a variety of applications. Developed in TI’s patented LBC3 BiCMOS process, the new BiMOS amplifiers combine a very high input impedance, low-noise CMOS front end with a high-drive bipolar output stage, thus providing the optimum performance features of both. AC performance improvements over the TL08x BiFET predecessors include a bandwidth of 10 MHz (an increase of 300%) and voltage noise of 8.5 nV/√Hz (an improvement of 60%). DC improvements include an ensured VICR that includes ground, a factor of 4 reduction in input offset voltage down to 1.5 mV (maximum), and a power-supply rejection improvement of greater than 40 dB to 130 dB. Added to this list of impressive features is the ability to drive ±50-mA loads comfortably from an ultra-small-footprint MSOP PowerPAD package, which positions the TLC08x as the ideal high-performance general-purpose operational amplifier family. Table 1. FAMILY PACKAGES (1) DEVICE NO. OF CHANNELS TLC080 (1) TLC081 (1) PACKAGE SHUTDOWN MSOP SOIC TSSOP 1 8 8 — Yes 1 8 8 — — TLC082 2 8 8 — — TLC083 (1) 2 10 14 — Yes TLC084 4 — 14 20 — TLC085 (1) 4 — 16 20 Yes UNIVERSAL EVM BOARD Refer to the EVM Selection Guide (literature number SLOU060) Product Preview 1 2 3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments. Parts, PSpice are trademarks of MicroSim Corporation. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2006–2011, Texas Instruments Incorporated TLC080-Q1, TLC081-Q1 TLC082-Q1, TLC083-Q1 TLC084-Q1, TLC085-Q1 SLOS510B – SEPTEMBER 2006 – REVISED MAY 2011 www.ti.com Table 2. TLC080 and TLC081 AVAILABLE OPTIONS (1) (2) PACKAGED DEVICES TA –40°C to 125°C (1) (2) (3) SMALL OUTLINE (D) (3) SMALL OUTLINE (DGN) (3) TLC080QDRQ1 TLC081QDRQ1 TLC080QDGNRQ1 TLC081QDGNRQ1 Product Preview For the most current package and ordering information, see the Package Option Addendum at the end of this data sheet, or see the TI web site at www.ti.com. This package is available taped and reeled. Table 3. TLC082 and TLC083 AVAILABLE OPTIONS (1) PACKAGED DEVICES TA –40°C to 125°C (1) (2) (3) SMALL OUTLINE (D) (2) MSOP (DGN) (2) MSOP (DGQ) (2) TLC082QDRQ1 (3) TLC083QDRQ1 (3) TLC082QDGNRQ1 TLC083QDGQRQ1 (3) For the most current package and ordering information, see the Package Option Addendum at the end of this data sheet, or see the TI web site at www.ti.com. This package is available taped and reeled. Product Preview Table 4. TLC084 and TLC085 AVAILABLE OPTIONS (1) PACKAGED DEVICES TA –40°C to 125°C (1) (2) (3) 2 SMALL OUTLINE (D) (2) TSSOP (PWP) (2) TLC084QDRQ1 (3) TLC085QDRQ1 (3) TLC084QPWPRQ1 TLC085QPWPRQ1 (3) For the most current package and ordering information, see the Package Option Addendum at the end of this data sheet, or see the TI web site at www.ti.com. This package is available taped and reeled. Product Preview Copyright © 2006–2011, Texas Instruments Incorporated TLC080-Q1, TLC081-Q1 TLC082-Q1, TLC083-Q1 TLC084-Q1, TLC085-Q1 SLOS510B – SEPTEMBER 2006 – REVISED MAY 2011 www.ti.com Figure 1. TLC08x PACKAGE PINOUTS TLC080 D OR DGN PACKAGE (TOP VIEW) NULL IN− IN+ GND 1 8 2 7 3 6 4 5 TLC081 D OR DGN PACKAGE (TOP VIEW) SHDN VDD OUT NULL NULL IN− IN+ GND 1 2 3 4 5 10 9 8 7 6 1OUT 1IN− 1IN+ GND NC 1SHDN NC VDD 2OUT 2IN− 2IN+ 2SHDN 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 7 3 6 4 5 1 14 2 13 3 12 4 11 5 10 6 9 7 TLC084 PWP PACKAGE (TOP VIEW) 1OUT 1IN− 1IN+ VDD 2IN+ 2IN− 2OUT NC NC NC 8 2 NC VDD OUT NULL 1OUT 1IN− 1IN+ GND 8 1OUT 1IN− 1IN+ VDD 2IN+ 2IN− 2OUT VDD 2OUT 2IN− 2IN+ NC 2SHDN NC 1OUT 1IN− 1IN+ VDD 2IN+ 2IN− 2OUT 1/2SHDN 1 16 2 15 3 14 4 13 5 12 6 7 8 11 10 9 8 2 7 3 6 4 5 VDD 2OUT 2IN− 2IN+ 1 14 2 13 3 12 4 11 5 10 6 9 7 8 4OUT 4IN− 4IN+ GND 3IN+ 3IN− 3OUT TLC085 PWP PACKAGE (TOP VIEW) TLC085 D PACKAGE (TOP VIEW) 4OUT 4IN− 4IN+ GND 3IN+ 3IN− 3OUT NC NC NC 1 TLC084 D PACKAGE (TOP VIEW) TLC083 D PACKAGE (TOP VIEW) TLC083 DGQ PACKAGE (TOP VIEW) 1OUT 1IN− 1IN+ GND 1SHDN 1 TLC082 D OR DGN PACKAGE (TOP VIEW) 4OUT 4IN− 4IN+ GND 3IN+ 3IN− 3OUT 3/4SHDN 1OUT 1IN− 1IN+ VDD 2IN+ 2IN− 2OUT 1/2SHDN NC NC 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 4OUT 4IN− 4IN+ GND 3IN+ 3IN− 3OUT 3/4SHDN NC NC NC − No internal connection Figure 2. Typical Pin 1 Indicators Pin 1 Printed or Molded Dot Copyright © 2006–2011, Texas Instruments Incorporated Pin 1 Stripe Pin 1 Bevel Edges Pin 1 Molded ”U” Shape 3 TLC080-Q1, TLC081-Q1 TLC082-Q1, TLC083-Q1 TLC084-Q1, TLC085-Q1 SLOS510B – SEPTEMBER 2006 – REVISED MAY 2011 www.ti.com Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN (2) VDD Supply voltage VID Differential input voltage MAX UNIT 17 V ±VDD V See Dissipation Rating Table Continuous total power dissipation TJ Operating junction temperature range –40 125 °C TA Operating ambient temperature range –40 125 °C TJ(max) Maximum junction temperature 150 °C Lead temperature 1,6 mm (1/16 in) from case for 10 s 260 °C (1) (2) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values, except differential voltages, are with respect to GND . Dissipation Ratings PACKAGE θJC (°C/W) θJA (°C/W) TA ≤ 25°C POWER RATING D (8) 38.3 176 710 mW D (14) 26.9 122.3 1022 mW D (16) 25.7 114.7 1090 mW DGN (8) 4.7 52.7 2.37 W DGQ (10) 4.7 52.3 2.39 W PWP (20) 1.4 26.1 4.79 W Recommended Operating Conditions VDD Supply voltage VICR Common-mode input voltage Shutdown on/off voltage level (1) TJ (1) 4 Operating junction temperature Single supply Split supply VIH MIN MAX 4.5 16 ±2.25 ±8 GND VDD – 2 2 VIL 0.8 –40 125 UNIT V V V °C Relative to the voltage on the GND terminal of the device Copyright © 2006–2011, Texas Instruments Incorporated TLC080-Q1, TLC081-Q1 TLC082-Q1, TLC083-Q1 TLC084-Q1, TLC085-Q1 SLOS510B – SEPTEMBER 2006 – REVISED MAY 2011 www.ti.com Electrical Characteristics VDD = 5 V (unless otherwise noted) PARAMETER TEST CONDITIONS VIO Input offset voltage VDD = 5 V, VIC = 2.5 V, VO = 2.5 V, RS = 50 Ω αVIO Temperature coefficient of input offset voltage VDD = 5 V, VIC = 2.5 V, VO = 2.5 V, RS = 50 Ω IIO Input offset current VDD = 5 V, VIC = 2.5 V, VO = 2.5 V, RS = 50 Ω IIB Input bias current VDD = 5 V, VIC = 2.5 V, VO = 2.5 V, RS = 50 Ω VICR Common-mode input voltage RS = 50 Ω IOH = –1 mA IOH = –20 mA VOH High-level output voltage VIC = 2.5 V IOH = –35 mA IOH = –50 mA IOL = 1 mA IOL = 20 mA VOL Low-level output voltage VIC = 2.5 V IOL = 35 mA IOL = 50 mA Sourcing TJ (1) MIN 25°C TYP MAX 390 1900 Full range 3300 25°C 1.9 3 Full range 50 700 25°C 0 to 3 0 to 3.5 Full range 0 to 3 0 to 3.5 25°C 4.1 4.3 Full range 3.9 25°C 3.7 Full range 3.5 25°C 3.4 Full range 3.2 25°C 3.2 Full range 50 700 25°C μV μV/°C 1.2 Full range UNIT pA pA V 4 V 3.8 3.6 3 25°C 0.18 Full range 0.25 0.35 25°C 0.35 Full range 0.39 0.45 25°C 0.43 Full range 0.55 V 0.7 25°C 0.45 Full range 0.63 0.7 100 IOS Short-circuit output current IO Output current AVD Large-signal differential voltage amplification rj(d) Differential input resistance 25°C 1000 GΩ CIC Common-mode input capacitance f = 10 kHz 25°C 22.9 pF ZO Closed-loop output impedance f = 10 kHz, AV = 10 25°C 0.25 Ω Sinking VOH = 1.5 V from positive rail VOL = 0.5 V from negative rail VO(PP) = 3 V, RL = 10 kΩ CMRR Common-mode rejection ratio VIC = 0 to 3 V, RS = 50 Ω kSVR Supply voltage rejection ratio (ΔVDD/ΔVIO) VDD = 4.5 V to 16 V, VIC = VDD/2, No load IDD Supply current (per channel) VO = 2.5 V, No load Supply current in shutdown mode IDD(SHDN) (per channel) (TLC080, TLC083, TLC085) (1) 25°C 100 Full range 100 25°C 70 Full range 70 25°C 80 Full range 80 120 dB 110 dB 100 1.8 Full range Full range mA 55 25°C 25°C SHDN ≤ 0.8 V 57 25°C 25°C mA 100 dB 2.5 3.5 125 mA 200 250 μA Full range is –40°C to 125°C. Copyright © 2006–2011, Texas Instruments Incorporated 5 TLC080-Q1, TLC081-Q1 TLC082-Q1, TLC083-Q1 TLC084-Q1, TLC085-Q1 SLOS510B – SEPTEMBER 2006 – REVISED MAY 2011 www.ti.com Operating Characteristics VDD = 5 V (unless otherwise noted) PARAMETER TEST CONDITIONS SR+ Positive slew rate at unity gain VO(PP) = 0.8 V, CL = 50 pF, RL = 10 kΩ SR– Negative slew rate at unity gain VO(PP) = 0.8 V, CL = 50 pF, RL = 10 kΩ Vn Equivalent input noise voltage In Equivalent input noise current f = 1 kHz THD+N VO(PP) = 3 V, Total harmonic distortion plus RL = 10 kΩ and 250 Ω, noise f = 1 kHz f = 100 Hz (1) MIN TYP 25°C 10 16 Full range 9 TJ 25°C 11 Full range 8.5 25°C f = 1 kHz 25°C AV = 1 AV = 10 19 12 8.5 0.6 MAX UNIT V/μs V/μs nV/√Hz fA/√Hz 0.002 25°C AV = 100 0.012 % 0.085 t(on) Amplifier turn-on time (2) RL = 10 kΩ 25°C 0.15 t(off) Amplifier turn-off time (2) RL = 10 kΩ 25°C 1.3 μs Gain-bandwidth product f = 10 kHz, RL = 10 kΩ 25°C 10 MHz ts φm (1) (2) 6 V(STEP)PP = 1 V, AV = –1, CL = 10 pF, RL = 10 kΩ 0.1% V(STEP)PP = 1 V, AV = –1, CL = 47 pF, RL = 10 kΩ 0.1% Settling time Phase margin RL = 10 kΩ Gain margin RL = 10 kΩ 0.01% 0.18 25°C 0.01% CL = 50 pF CL = 0 pF CL = 50 pF CL = 0 pF μs 0.39 0.18 μs 0.39 25°C 25°C 32 40 2.2 3.3 deg dB Full range is –40°C to 125°C. Disable time and enable time are defined as the interval between application of the logic signal to SHDN and the point at which the supply current has reached half its final value. Copyright © 2006–2011, Texas Instruments Incorporated TLC080-Q1, TLC081-Q1 TLC082-Q1, TLC083-Q1 TLC084-Q1, TLC085-Q1 SLOS510B – SEPTEMBER 2006 – REVISED MAY 2011 www.ti.com Electrical Characteristics VDD = 12 V (unless otherwise noted) PARAMETER TEST CONDITIONS VIO Input offset voltage VDD = 12 V, VIC = 6 V, VO = 6 V, RS = 50 Ω αVIO Temperature coefficient of input offset voltage VDD = 12 V, VIC = 6 V, VO = 6 V, RS = 50 Ω IIO Input offset current VDD = 12 V, VIC = 6 V, VO = 6 V, RS = 50 Ω IIB Input bias current VDD = 12 V, VIC = 6 V, VO = 6 V, RS = 50 Ω VICR Common-mode input voltage RS = 50 Ω IOH = –1 mA IOH = –20 mA VOH High-level output voltage VIC = 6 V IOH = –35 mA IOH = –50 mA IOL = 1 mA IOL = 20 mA VOL Low-level output voltage VIC = 6 V IOL = 35 mA IOL = 50 mA Sourcing TJ (1) MIN 25°C TYP MAX 390 1900 Full range 3300 25°C 1.5 3 Full range 25°C 0 to 10 0 to 10.5 0 to 10 0 to 10.5 Full range 50 700 Full range 25°C 50 700 25°C 11.1 μV μV/°C 1.2 Full range UNIT pA pA V 11.2 11 25°C 10.8 Full range 10.7 25°C 10.6 Full range 10.3 25°C 10.3 Full range 10.1 25°C 11 V 10.7 10.5 0.17 Full range 0.25 0.35 25°C 0.35 Full range 0.45 0.55 25°C 0.4 Full range 0.52 V 0.6 25°C 0.45 Full range 0.6 0.7 150 IOS Short-circuit output current IO Output current AVD Large-signal differential voltage amplification rj(d) Differential input resistance 25°C 1000 GΩ CIC Common-mode input capacitance f = 10 kHz 25°C 21.6 pF ZO Closed-loop output impedance f = 10 kHz, AV = 10 25°C 0.25 Ω Sinking VOH = 1.5 V from positive rail VOL = 0.5 V from negative rail VO(PP) = 8 V, RL = 10 kΩ CMRR Common-mode rejection ratio VIC = 0 to 10 V, RS = 50 Ω kSVR Supply voltage rejection ratio (ΔVDD/ΔVIO) VDD = 4.5 V to 16 V, VIC = VDD/2, No load IDD Supply current (per channel) VO = 7.5 V, No load Supply current in shutdown mode IDD(SHDN) (per channel) (TLC080, TLC083, TLC085) (1) 25°C 110 Full range 110 25°C 80 Full range 80 25°C 80 Full range 80 130 dB 110 dB 100 1.9 Full range Full range mA 55 25°C 25°C SHDN ≤ 0.8 V 57 25°C 25°C mA 150 dB 2.9 3.5 125 mA 200 250 μA Full range is –40°C to 125°C. Copyright © 2006–2011, Texas Instruments Incorporated 7 TLC080-Q1, TLC081-Q1 TLC082-Q1, TLC083-Q1 TLC084-Q1, TLC085-Q1 SLOS510B – SEPTEMBER 2006 – REVISED MAY 2011 www.ti.com Operating Characteristics VDD = 12 V (unless otherwise noted) PARAMETER TEST CONDITIONS SR+ Positive slew rate at unity gain VO(PP) = 2 V, CL = 50 pF, RL = 10 kΩ SR– Negative slew rate at unity gain VO(PP) = 2 V, CL = 50 pF, RL = 10 kΩ Vn Equivalent input noise voltage In Equivalent input noise current f = 1 kHz THD+N VO(PP) = 8 V, Total harmonic distortion plus RL = 10 kΩ and 250 Ω, noise f = 1 kHz f = 100 Hz TJ (1) 16 25°C 10 9.5 25°C 12.5 Full range 25°C AV = 1 AV = 10 TYP Full range 25°C f = 1 kHz MIN 19 10 14 8.5 0.6 MAX UNIT V/μs V/μs nV/√Hz fA/√Hz 0.002 25°C AV = 100 0.005 % 0.022 t(on) Amplifier turn-on time (2) RL = 10 kΩ 25°C 0.47 t(off) Amplifier turn-off time (2) RL = 10 kΩ 25°C 2.5 μs Gain-bandwidth product f = 10 kHz, RL = 10 kΩ 25°C 10 MHz ts φm (1) (2) 8 V(STEP)PP = 1 V, AV = –1, CL = 10 pF, RL = 10 kΩ 0.1% V(STEP)PP = 1 V, AV = –1, CL = 47 pF, RL = 10 kΩ 0.1% Settling time Phase margin RL = 10 kΩ Gain margin RL = 10 kΩ 0.01% 0.17 25°C 0.01% CL = 50 pF CL = 0 pF CL = 50 pF CL = 0 pF μs 0.22 0.17 μs 0.29 25°C 25°C 37 42 3.1 4 deg dB Full range is –40°C to 125°C. Disable time and enable time are defined as the interval between application of the logic signal to SHDN and the point at which the supply current has reached half its final value. Copyright © 2006–2011, Texas Instruments Incorporated TLC080-Q1, TLC081-Q1 TLC082-Q1, TLC083-Q1 TLC084-Q1, TLC085-Q1 SLOS510B – SEPTEMBER 2006 – REVISED MAY 2011 www.ti.com TYPICAL CHARACTERISTICS Table 5. Table of Graphs FIGURE VIO Input offset voltage vs Common-mode input voltage 1, 2 IIO Input offset current vs Free-air temperature 3, 4 IIB Input bias current vs Free-air temperature 3, 4 VOH High-level output voltage vs High-level output current 5, 7 VOL Low-level output voltage vs Low-level output current 6, 8 ZO Output impedance vs Frequency 9 IDD Supply current vs Supply voltage 10 PSRR Power supply rejection ratio vs Frequency 11 CMRR Common-mode rejection ratio vs Frequency 12 Vn Equivalent input noise voltage vs Frequency 13 VO(PP) Peak-to-peak output voltage vs Frequency 14, 15 Crosstalk vs Frequency 16 Differential voltage gain vs Frequency 17, 18 Phase vs Frequency 17, 18 Phase margin vs Load capacitance 19, 20 Gain margin vs Load capacitance 21, 22 Gain-bandwidth product vs Supply voltage φm SR Slew rate THD+N Total harmonic distortion plus noise vs Supply voltage 23 24 vs Free-air temperature 25, 26 vs Frequency 27, 28 vs Peak-to-peak output voltage 29, 30 Large-signal follower pulse response 31, 32 Small-signal follower pulse response 33 Large-signal inverting pulse response 34, 35 Small-signal inverting pulse response 36 Shutdown forward isolation vs Frequency 37, 38 Shutdown reverse isolation vs Frequency 39, 40 Shutdown supply current Shutdown pulse Copyright © 2006–2011, Texas Instruments Incorporated vs Supply voltage 41 vs Free-air temperature 42 43, 44 9 TLC080-Q1, TLC081-Q1 TLC082-Q1, TLC083-Q1 TLC084-Q1, TLC085-Q1 SLOS510B – SEPTEMBER 2006 – REVISED MAY 2011 www.ti.com INPUT OFFSET VOLTAGE vs COMMON-MODE INPUT VOLTAGE VDD = 12 V TA = 25° C 1300 V IO − Input Offset Voltage − µ V 400 200 0 −200 −400 1100 900 700 500 300 100 −100 −300 −600 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 −500 0 1 2 3 4 IIO −20 −40 −60 −80 −100 IIB −120 VDD = 12 V −140 9 10 11 12 IIB 50 0 IIO −50 −100 −55 −40 −25 −10 5 20 35 50 65 80 95 110 125 Figure 5. HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT 1.0 VDD = 5 V 4.5 TA = 70°C TA = 25°C 4.0 TA = −40°C 3.5 TA = 125°C 3.0 2.5 2.0 −160 −55 −40 −25 −10 5 20 35 50 65 80 95 110 125 VDD = 5 V 0.9 0.8 0.7 TA = 125°C 0.6 TA = 70°C TA = 25°C 0.5 0.4 0.3 TA = −40°C 0.2 0.1 0.0 0 5 10 15 20 25 30 35 40 45 50 IOH - High-Level Output Current - mA 0 5 10 15 20 25 30 35 40 45 50 IOL - Low-Level Output Current - mA Figure 6. Figure 7. Figure 8. HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT OUTPUT IMPEDANCE vs FREQUENCY 12.0 1000 1.0 TA = 125°C TA = 70°C 11.5 11.0 10.5 TA = −40°C TA = 25°C 10.0 9.5 VDD = 12 V 9.0 VOL − Low-Level Output Voltage − V V OH − High-Level Output Voltage − V 8 100 Figure 4. TA − Free-Air Temperature − °C 0.9 0.8 TA = 125°C 0.7 TA = 70°C 0.6 TA = 25°C 0.5 0.4 0.3 TA = −40°C 0.2 0.1 5 10 15 20 25 30 35 40 45 50 IOH - High-Level Output Current - mA Figure 9. 100 VDD = 5 V and 12 V TA = 25°C 10 AV = 100 1 AV = 1 0.10 AV = 10 VDD = 12 V 0.0 0 10 7 150 5.0 V OH − High-Level Output Voltage − V I IB / I IO − Input Bias and Input Offset Current − pA INPUT BIAS CURRENT AND INPUT OFFSET CURRENT vs FREE-AIR TEMPERATURE 0 6 200 TA − Free-Air Temperature − °C Figure 3. 20 5 VICR − Common-Mode Input Voltage − V VICR − Common-Mode Input Voltage − V VDD = 5 V 250 VOL − Low-Level Output Voltage − V 600 300 Z o − Output Impedance − Ω V IO − Input Offset Voltage − µ V 800 I IB / I IO − Input Bias and Input Offset Current − pA 1500 1000 VDD = 5 V TA = 25° C INPUT BIAS CURRENT AND INPUT OFFSET CURRENT vs FREE-AIR TEMPERATURE INPUT OFFSET VOLTAGE vs COMMON-MODE INPUT VOLTAGE 0 5 10 15 20 25 30 35 40 45 50 IOL - Low-Level Output Current - mA Figure 10. 0.01 100 1k 10k 100k 1M f - Frequency - Hz 10M Figure 11. Copyright © 2006–2011, Texas Instruments Incorporated TLC080-Q1, TLC081-Q1 TLC082-Q1, TLC083-Q1 TLC084-Q1, TLC085-Q1 SLOS510B – SEPTEMBER 2006 – REVISED MAY 2011 www.ti.com POWER-SUPPLY REJECTION RATIO vs FREQUENCY 1.8 TA = 125°C 1.6 TA = 70°C 1.4 AV = 1 SHDN = VDD Per Channel 1.2 1.0 4 5 6 VDD = 12 V 100 80 60 40 VDD = 5 V 20 0 0 7 8 9 10 11 12 13 14 15 VDD − Supply Voltage - V 10 100 100k 10k 1M 10M VDD = 5 V and 12 V TA = 25°C 120 100 80 60 40 20 0 100 1k 10k 100k 1M f - Frequency - Hz Figure 14. EQUIVALENT INPUT NOISE VOLTAGE vs FREQUENCY PEAK-TO-PEAK OUTPUT VOLTAGE vs FREQUENCY PEAK-TO-PEAK OUTPUT VOLTAGE vs FREQUENCY 25 20 15 VDD = 12 V 10 VDD = 5 V 5 0 10 100 1k 10k 100k VDD = 12 V 10 8 6 VDD = 5 V 4 THD+N ≤ 5% RL = 600 Ω TA = 25°C 2 0 f − Frequency − Hz 10k 100k 1M f - Frequency - Hz Figure 15. 0 A VD − Different Voltage Gain − dB −40 VDD = 5 V and 12 V AV = 1 RL = 10 kΩ VI(PP) = 2 V For All Channels −60 −80 −100 −120 −140 −160 10 100 1k 10k 100k f − Frequency − Hz Figure 18. Copyright © 2006–2011, Texas Instruments Incorporated 10M 12 VDD = 12 V 10 8 6 VDD = 5 V 4 2 0 10k 10M THD+N ≤ 5% RL= 10 kΩ TA = 25°C 100k 1M f - Frequency - Hz Figure 16. CROSSTALK vs FREQUENCY −20 V O(PP) − Peak-to-Peak Output Voltage − V 30 12 10M Figure 17. DIFFERENTIAL VOLTAGE GAIN AND PHASE vs FREQUENCY DIFFERENTIAL VOLTAGE GAIN AND PHASE vs FREQUENCY 80 80 0 70 60 Gain −45 50 Phase 40 −90 30 20 −135 10 0 −10 −20 1k VDD = ±2.5 V RL = 10 kΩ CL = 0 pF TA = 25°C 10k −180 100k 1M 10M f − Frequency − Hz Figure 19. −225 100M Phase − ° 35 A VD − Different Voltage Gain − dB Hz Figure 13. V n − Equivalent Input Noise Voltage − nV/ Figure 12. 40 Crosstalk − dB 1k 140 f − Frequency − Hz V O(PP) − Peak-to-Peak Output Voltage − V I DD − Supply Current − mA TA = −40°C 2.0 120 0 70 Gain 60 −45 50 Phase 40 −90 30 20 −135 Phase − ° TA = 25°C 2.2 140 PSRR − Power−Supply Rejection Ratio − dB 2.4 COMMON-MODE REJECTION RATIO vs FREQUENCY CMRR − Common-Mode Rejection Ratio − dB SUPPLY CURRENT vs SUPPLY VOLTAGE 10 0 −10 −20 1k VDD = ±6 V RL = 10 kΩ CL = 0 pF TA = 25°C 10k −180 100k 1M 10M −225 100M f − Frequency − Hz Figure 20. 11 TLC080-Q1, TLC081-Q1 TLC082-Q1, TLC083-Q1 TLC084-Q1, TLC085-Q1 SLOS510B – SEPTEMBER 2006 – REVISED MAY 2011 www.ti.com PHASE MARGIN vs LOAD CAPACITANCE PHASE MARGIN vs LOAD CAPACITANCE 40° 45° Rnull = 0 Ω Rnull = 100 Ω 35° Rnull = 20 Ω 15° VDD = 5 V RL = 10 kΩ TA = 25°C 25° 20° 15° 10° 5° 0° 10 Rnull = 20 Ω GAIN MARGIN vs LOAD CAPACITANCE GBWP − Gain-Bandwidth Product − MHz Rnull = 0 Ω φ m − Phase Margin − dB 4.5 Rnull = 100 Ω 3.5 3 2.5 Rnull = 50 Ω 2 Rnull = 20 Ω 1.5 1 0.5 VDD = 12 V RL = 10 kΩ TA = 25°C Figure 23. GAIN-BANDWIDTH PRODUCT vs SUPPLY VOLTAGE SLEW RATE vs SUPPLY VOLTAGE 22 20 9.7 RL = 10 kΩ 9.6 9.5 9.4 RL = 600 Ω 9.3 9.2 17 16 13 5 6 7 8 9 12 10 11 12 13 14 15 16 Figure 25. SLEW RATE vs FREE-AIR TEMPERATURE SLEW RATE vs FREE-AIR TEMPERATURE 4 10 6 7 8 9 10 11 12 13 14 15 16 VDD - Supply Voltage - V TOTAL HARMONIC DISTORTION PLUS NOISE vs FREQUENCY 1 Slew Rate − 20 15 Slew Rate + 10 VDD = 12 V RL= 600 Ω and 10 kΩ CL = 50 pF AV = 1 5 5 0 −55 −35 −15 5 25 45 65 85 105 125 TA - Free-Air Temperature - °C 0 −55 −35 −15 5 25 45 65 85 105 125 TA - Free-Air Temperature - °C Total Harmonic Distortion + Noise − % Slew Rate + 5 Figure 26. 25 15 Slew Rate + 15 14 Figure 24. VDD = 5 V RL= 600 Ω and 10 kΩ CL = 50 pF AV = 1 Slew Rate − 18 VDD - Supply Voltage - V SR − Slew Rate − V/ µ s SR − Slew Rate − V/ µ s 19 9.1 4 25 RL = 600 Ω and 10 kΩ CL = 50 pF AV = 1 21 TA = 25°C 9.8 CL − Load Capacitance − pF 20 100 Figure 22. CL = 11 pF 9.9 Rnull = 20 Ω CL − Load Capacitance − pF 10.0 100 Slew Rate − VDD = 5 V RL = 10 kΩ TA = 25°C 0 10 9.0 0 10 1 0.5 CL − Load Capacitance − pF Figure 21. 4 Rnull = 50 Ω 1.5 100 CL − Load Capacitance − pF 5 2 VDD = 12 V RL = 10 kΩ TA = 25°C 0° 10 100 2.5 SR − Slew Rate − V/ µ s 20° Rnull = 100 Ω Rnull = 50 Ω Rnull = 100 Ω 3 G − Gain Margin − dB φ m − Phase Margin φ m − Phase Margin Rnull = 50 Ω 30° Rnull = 0 Ω 3.5 35° 25° 5° 4 Rnull = 0 Ω 40° 30° 10° GAIN MARGIN vs LOAD CAPACITANCE VDD = 5 V VO(PP) = 2 V RL = 10 kΩ 0.1 AV = 100 AV = 10 0.01 AV = 1 0.001 100 1k 10k 100k f − Frequency − Hz Figure 27. 12 Figure 28. Figure 29. Copyright © 2006–2011, Texas Instruments Incorporated TLC080-Q1, TLC081-Q1 TLC082-Q1, TLC083-Q1 TLC084-Q1, TLC085-Q1 SLOS510B – SEPTEMBER 2006 – REVISED MAY 2011 www.ti.com VDD = 12 V VO(PP) = 8 V RL = 10 kΩ Total Harmonic Distortion + Noise − % AV = 100 0.01 AV = 10 AV = 1 1k 10k 100k 10 10 1 RL = 600 Ω 0.01 0.0001 0.25 0.75 1.25 1.75 2.25 2.75 3.25 3.75 Figure 30. Figure 31. LARGE-SIGNAL FOLLOWER PULSE RESPONSE LARGE-SIGNAL FOLLOWER PULSE RESPONSE VDD = 5 V RL = 600 Ω and 10 kΩ CL = 8 pF TA = 25°C 0.2 0.4 0.6 0.8 1 RL = 250 Ω 0.1 RL = 600 Ω 0.01 0.001 1.2 1.4 1.6 1.8 2 1 4.5 6.5 8.5 VI(100mV/Div) 1.2 1.4 1.6 1.8 VO(50mV/Div) VDD = 5 V and 12 V RL = 600 Ω and 10 kΩ CL = 8 pF TA = 25°C 0 2 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 0.10 t − Time − µs t − Time − µs t − Time − µs Figure 33. Figure 34. Figure 35. LARGE-SIGNAL INVERTING PULSE RESPONSE LARGE-SIGNAL INVERTING PULSE RESPONSE SMALL-SIGNAL INVERTING PULSE RESPONSE VI (5 V/div) V O − Output Voltage − V VI (2 V/div) VDD = 5 V RL = 600 Ω and 10 kΩ CL = 8 pF TA = 25°C 10.5 SMALL-SIGNAL FOLLOWER PULSE RESPONSE VDD = 12 V RL = 600 Ω and 10 kΩ CL = 8 pF TA = 25°C 0.2 0.4 0.6 0.8 2.5 VO(PP) − Peak-to-Peak Output Voltage − V Figure 32. VO (2 V/Div) 0 RL = 10 kΩ 0.0001 0.5 VI (5 V/Div) VO (500 mV/Div) VDD = 12 V AV = 1 f = 1 kHz 1 VO(PP) − Peak-to-Peak Output Voltage − V V O − Output Voltage − V V O − Output Voltage − V RL = 10 kΩ 0.001 VI (1 V/Div) V O − Output Voltage − V RL = 250 Ω 0.1 f − Frequency − Hz 0 VDD = 5 V AV = 1 f = 1 kHz V O − Output Voltage − V 0.001 100 TOTAL HARMONIC DISTORTION PLUS NOISE vs PEAK-TO-PEAK OUTPUT VOLTAGE VI (100 mV/div) V O − Output Voltage − V Total Harmonic Distortion + Noise − % 0.1 TOTAL HARMONIC DISTORTION PLUS NOISE vs PEAK-TO-PEAK OUTPUT VOLTAGE Total Harmonic Distortion + Noise − % TOTAL HARMONIC DISTORTION PLUS NOISE vs FREQUENCY VDD = 12 V RL = 600 Ω and 10 kΩ CL = 8 pF TA = 25°C VDD = 5 V and 12 V RL = 600 Ω and 10 kΩ CL = 8 pF TA = 25°C VO (50 mV/Div) VO (2 V/Div) VO (500 mV/Div) 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 t − Time − µs t − Time − µs t − Time − µs Figure 36. Figure 37. Figure 38. Copyright © 2006–2011, Texas Instruments Incorporated 1 13 TLC080-Q1, TLC081-Q1 TLC082-Q1, TLC083-Q1 TLC084-Q1, TLC085-Q1 SLOS510B – SEPTEMBER 2006 – REVISED MAY 2011 www.ti.com SHUTDOWN FORWARD ISOLATION vs FREQUENCY SHUTDOWN FORWARD ISOLATION vs FREQUENCY 140 120 100 RL = 600 Ω 80 60 RL = 10 kΩ 40 120 100 80 40 10k 100k 1M f - Frequency - Hz 10M 80 RL = 600 Ω 60 RL = 10 kΩ 40 1k 10k 100k 1M f - Frequency - Hz 10M 100 100M 1k 10k 100k 1M f - Frequency - Hz 10M 100M Figure 39. Figure 40. Figure 41. SHUTDOWN REVERSE ISOLATION vs FREQUENCY SHUTDOWN SUPPLY CURRENT vs SUPPLY VOLTAGE SHUTDOWN SUPPLY CURRENT 100 RL = 600 Ω 80 60 RL = 10 kΩ 40 Shutdown On RL = open VIN = VDD/2 134 132 130 128 126 124 122 120 118 4 1k 10k 100k 1M f - Frequency - Hz 10M 100M Figure 42. 5 6 7 8 9 10 11 12 13 14 15 16 VDD - Supply Voltage - V 2 VDD = 5 V CL= 8 pF TA = 25°C 0 IDD RL = 10 kΩ −2 1.5 IDD RL = 600 Ω 1.0 −4 0.5 I DD − Supply Current − mA 4 Shutdown Pulse 4.5 2.0 80 60 −55 −25 5 35 65 95 TA - Free-Air Temperature - °C 125 6 5.5 SD Off 2.5 VDD = 5 V 100 SHUTDOWN PULSE Shutdown Pulse - V I DD − Supply Current − mA 5.5 3.0 VDD = 12 V 120 6.0 6 3.5 140 Figure 44. SHUTDOWN PULSE 4.0 AV = 1 VIN = VDD/2 160 Figure 43. 6.0 5.0 180 SD Off 5.0 Shutdown Pulse 4 VDD = 12 V CL= 8 pF TA = 25°C 2 4.5 4.0 3.5 3.0 2.5 0 IDD RL = 10 kΩ 2.0 −2 1.5 IDD RL = 600 Ω 1.0 Shutdown Pulse - V 120 I DD(SHDN) − Shutdown Supply Current - µ A VDD = 12 V CL= 0 pF TA = 25°C VI(PP) = 0.1, 8, 12 V vs FREE-AIR TEMPERATURE 136 20 −4 0.5 0.0 −6 0 10 20 30 40 50 t - Time - µs Figure 45. 14 100 20 100 100M I DD(SHDN) − Shutdown Supply Current - µ A Sutdown Reverse Isolation - dB RL = 10 kΩ VDD = 5 V CL= 0 pF TA = 25°C VI(PP) = 0.1, 2.5, and 5 V 120 20 1k 140 100 RL = 600 Ω 60 20 100 140 VDD = 12 V CL= 0 pF TA = 25°C VI(PP) = 0.1, 8, 12 V Sutdown Reverse Isolation - dB VDD = 5 V CL= 0 pF TA = 25°C VI(PP) = 0.1, 2.5, and 5 V Sutdown Forward Isolation - dB Sutdown Forward Isolation - dB 140 SHUTDOWN REVERSE ISOLATION vs FREQUENCY 60 70 80 0.0 −6 0 10 20 30 40 50 t - Time - µs 60 70 80 Figure 46. Copyright © 2006–2011, Texas Instruments Incorporated TLC080-Q1, TLC081-Q1 TLC082-Q1, TLC083-Q1 TLC084-Q1, TLC085-Q1 SLOS510B – SEPTEMBER 2006 – REVISED MAY 2011 www.ti.com PARAMETER MEASUREMENT INFORMATION _ Rnull + RL CL Figure 47. Copyright © 2006–2011, Texas Instruments Incorporated 15 TLC080-Q1, TLC081-Q1 TLC082-Q1, TLC083-Q1 TLC084-Q1, TLC085-Q1 SLOS510B – SEPTEMBER 2006 – REVISED MAY 2011 www.ti.com APPLICATION INFORMATION Input Offset Voltage Null Circuit The TLC080 and TLC081 have an input offset nulling function (see Figure 48). − IN − OUT N2 + IN + N1 100 kΩ R1 VDD − A. R1 = 5.6 kΩ for offset voltage adjustment of ±10 mV R1 = 20 kΩ for offset voltage adjustment of ±3 mV Figure 48. Input Offset Voltage Null Circuit Driving a Capacitive Load When the amplifier is configured in this manner, capacitive loading directly on the output decreases the device phase margin, leading to high-frequency ringing or oscillations. Therefore, for capacitive loads of greater than 10 pF, it is recommended that a resistor be placed in series (RNULL) with the output of the amplifier, as shown in Figure 49. A minimum value of 20 Ω should work well for most applications. RF RG _ Input RNULL Output + CLOAD Figure 49. Driving a Capacitive Load Offset Voltage The output offset voltage, (VOO) is the sum of the input offset voltage (VIO) and both input bias currents (IIB) times the corresponding gains. The schematic and formula in Figure 50 can be used to calculate the output offset voltage. RF RG IIB− + VI RS − VO + IIB+ ǒ ǒ ǓǓ VOO + VIO 1 ) R F RG " IIB) RS ǒ ǒ ǓǓ 1) R F RG " IIB– RF Figure 50. Output Offset Voltage Model 16 Copyright © 2006–2011, Texas Instruments Incorporated TLC080-Q1, TLC081-Q1 TLC082-Q1, TLC083-Q1 TLC084-Q1, TLC085-Q1 SLOS510B – SEPTEMBER 2006 – REVISED MAY 2011 www.ti.com High-Speed CMOS Input Amplifiers The TLC08x is a family of high-speed low-noise CMOS input operational amplifiers that has an input capacitance on the order of 20 pF. Any resistor used in the feedback path adds a pole in the transfer function equivalent to the input capacitance multiplied by the combination of source resistance and feedback resistance. For example, a gain of –10, a source resistance of 1 kΩ, and a feedback resistance of 10 kΩ add an additional pole at approximately 8 MHz. This is more apparent with CMOS amplifiers than bipolar amplifiers due to their greater input capacitance. This is of little consequence on slower CMOS amplifiers, as this pole normally occurs at frequencies above their unity-gain bandwidth. However, the TLC08x with its 10-MHz bandwidth means that this pole normally occurs at frequencies where there is on the order of 5-dB gain left and the phase shift adds considerably. The effect of this pole is the strongest with large feedback resistances at small closed loop gains. As the feedback resistance is increased, the gain peaking increases at a lower frequency and the 180° phase shift crossover point also moves down in frequency, decreasing the phase margin. For the TLC08x, the maximum feedback resistor recommended is 5 kΩ; larger resistances can be used but a capacitor in parallel with the feedback resistor is recommended to counter the effects of the input capacitance pole. The TLC083 with a 1-V step response has an 80% overshoot with a natural frequency of 3.5 MHz when configured as a unity gain buffer and with a 10-kΩ feedback resistor. By adding a 10-pF capacitor in parallel with the feedback resistor, the overshoot is reduced to 40% and eliminates the natural frequency, resulting in a much faster settling time (see Figure 51). The 10-pF capacitor was chosen for convenience only. 2 VIN V O − Output Voltage − V 1 0 With CF = 10 pF −1 1.5 V I − Input Voltage − V Load capacitance had little effect on these measurements due to the excellent output drive capability of the TLC08x. 10 pF 10 kΩ _ 1 0.5 VOUT 0 IN VDD = ±5 V AV = +1 RF = 10 kΩ RL = 600 Ω CL = 22 pF + 50 Ω 600 Ω 22 pF −0.5 0 0.2 0.4 0.6 0.8 t - Time - µs 1 1.2 1.4 1.6 Figure 51. 1-V Step Response Copyright © 2006–2011, Texas Instruments Incorporated 17 TLC080-Q1, TLC081-Q1 TLC082-Q1, TLC083-Q1 TLC084-Q1, TLC085-Q1 SLOS510B – SEPTEMBER 2006 – REVISED MAY 2011 www.ti.com General Configurations When receiving low-level signals, limiting the bandwidth of the incoming signals into the system is often required. The simplest way to accomplish this is to place an RC filter at the noninverting terminal of the amplifier (see Figure 52). RG RF − VO + VI R1 C1 f V O + V I ǒ R 1) R F G Ǔǒ –3dB + 1 2pR1C1 Ǔ 1 1 ) sR1C1 Figure 52. Single-Pole Low-Pass Filter If even more attenuation is needed, a multiple pole filter is required. The Sallen-Key filter can be used for this task. For best results, the amplifier should have a bandwidth that is eight to ten times the filter frequency bandwidth. Failure to do this can result in phase shift of the amplifier. C1 + _ VI R1 R1 = R2 = R C1 = C2 = C Q = Peaking Factor (Butterworth Q = 0.707) R2 f C2 RG RF –3dB RG = + ( 1 2pRC RF 1 2− Q ) Figure 53. 2-Pole Low-Pass Sallen-Key Filter Shutdown Function Three members of the TLC08x family (TLC080/3/5) have a shutdown (SHDN) terminal for conserving battery life in portable applications. When SHDN is tied low, the supply current is reduced to 125 μA/channel, the amplifier is disabled, and the outputs are placed in a high-impedance mode. To enable the amplifier, SHDN can either be left floating or pulled high. When SHDN is left floating, care should be taken to ensure that parasitic leakage current at SHDN does not inadvertently place the operational amplifier into shutdown. SHDN threshold is always referenced to the voltage on the GND terminal of the device. Therefore, when operating the device with split supply voltages (e.g. ±2.5 V), SHDN needs to be pulled to VDD– (not system ground) to disable the operational amplifier. The amplifier’s output with a shutdown pulse is shown in Figure 45 and Figure 46. The amplifier is powered with a single 5-V supply and is configured as noninverting with a gain of 5. The amplifier turn-on and turn-off times are measured from the 50% point of the shutdown pulse to the 50% point of the output waveform. The times for the single, dual, and quad are listed in the data tables. Figure 39 through Figure 42 show the amplifier’s forward and reverse isolation in shutdown. The operational amplifier is configured as a voltage follower (AV = 1). The isolation performance is plotted across frequency using 0.1-VPP, 2.5-VPP, and 5-VPP input signals at ±2.5-V supplies and 0.1-VPP, 8-VPP, and 12-VPP input signals at ±6-V supplies. 18 Copyright © 2006–2011, Texas Instruments Incorporated TLC080-Q1, TLC081-Q1 TLC082-Q1, TLC083-Q1 TLC084-Q1, TLC085-Q1 SLOS510B – SEPTEMBER 2006 – REVISED MAY 2011 www.ti.com Circuit Layout Considerations To achieve the levels of high performance of the TLC08x, follow proper printed circuit board (PCB) design techniques. A general set of guidelines is given in the following. • Ground planes – It is highly recommended that a ground plane be used on the board to provide all components with a low inductive ground connection. However, in the areas of the amplifier inputs and output, the ground plane can be removed to minimize the stray capacitance. • Proper power-supply decoupling – Use a 6.8-μF tantalum capacitor in parallel with a 0.1-μF ceramic capacitor on each supply terminal. It may be possible to share the tantalum among several amplifiers depending on the application, but a 0.1-μF ceramic capacitor should always be used on the supply terminal of every amplifier. In addition, the 0.1-μF capacitor should be placed as close as possible to the supply terminal. As this distance increases, the inductance in the connecting trace makes the capacitor less effective. The designer should strive for distances of less than 0.1 inches between the device power terminals and the ceramic capacitors. • Sockets – Sockets can be used but are not recommended. The additional lead inductance in the socket pins will often lead to stability problems. Surface-mount packages soldered directly to the PCB is the best implementation. • Short trace runs/compact part placements – Optimum high performance is achieved when stray series inductance has been minimized. To realize this, the circuit layout should be made as compact as possible, thereby minimizing the length of all trace runs. Particular attention should be paid to the inverting input of the amplifier. Its length should be kept as short as possible. This helps minimize stray capacitance at the input of the amplifier. • Surface-mount passive components – Using surface-mount passive components is recommended for high-performance amplifier circuits for several reasons. First, because of the extremely low lead inductance of surface-mount components, the problem with stray series inductance is greatly reduced. Second, the small size of surface-mount components naturally leads to a more compact layout thereby minimizing both stray inductance and capacitance. If leaded components are used, it is recommended that the lead lengths be kept as short as possible. General PowerPAD Design Considerations The TLC08x is available in a thermally-enhanced PowerPAD family of packages. These packages are constructed using a downset leadframe upon which the die is mounted [see Figure 54(a) and Figure 54(b)]. This arrangement results in the lead frame being exposed as a thermal pad on the underside of the package [see Figure 54(c)]. Because this thermal pad has direct thermal contact with the die, excellent thermal performance can be achieved by providing a good thermal path away from the thermal pad. DIE Side View (a) Thermal Pad DIE End View (b) Bottom View (c) NOTE A: The thermal pad is electrically isolated from all terminals in the package. Figure 54. Views of Thermally-Enhanced DGN Package The PowerPAD package allows for both assembly and thermal management in one manufacturing operation. During the surface-mount solder operation (when the leads are being soldered), the thermal pad must be soldered to a copper area underneath the package. Through the use of thermal paths within this copper area, heat can be conducted away from the package into either a ground plane or other heat dissipating device. Soldering the PowerPAD to the PCB is always required, even with applications that have low power dissipation. This soldering provides the necessary thermal and mechanical connection between the lead frame die pad and the PCB. Although there are many ways to properly heatsink the PowerPAD package, the following steps list the recommended approach. Copyright © 2006–2011, Texas Instruments Incorporated 19 TLC080-Q1, TLC081-Q1 TLC082-Q1, TLC083-Q1 TLC084-Q1, TLC085-Q1 SLOS510B – SEPTEMBER 2006 – REVISED MAY 2011 www.ti.com The PowerPAD must be connected to the most negative supply voltage (GND pin potential) of the device. 1. Prepare the PCB with a top-side etch pattern (see the landing patterns at the end of this data sheet). There should be etch for the leads, as well as etch for the thermal pad. 2. Place five holes (dual) or nine holes (quad) in the area of the thermal pad. These holes should be 13 mils in diameter. Keep them small so that solder wicking through the holes is not a problem during reflow. 3. Additional vias may be placed anywhere along the thermal plane outside of the thermal pad area. This helps dissipate the heat generated by the TLC08x IC. These additional vias may be larger than the 13-mil diameter vias directly under the thermal pad. They can be larger because they are not in the thermal-pad area to be soldered, so that wicking is not a problem. 4. Connect all holes to the internal plane that is at the same potential as the ground pin of the device. 5. When connecting these holes to this internal plane, do not use the typical web or spoke via connection methodology. Web connections have a high thermal resistance connection that is useful for slowing the heat transfer during soldering operations. This makes the soldering of vias that have plane connections easier. In this application, however, low thermal resistance is desired for the most efficient heat transfer. Therefore, the holes under the TLC08x PowerPAD package should make their connection to the internal ground plane with a complete connection around the entire circumference of the plated-through hole. 6. The top-side solder mask should leave the terminals of the package and the thermal-pad area with its five holes (dual) or nine holes (quad) exposed. The bottom-side solder mask should cover the five or nine holes of the thermal-pad area. This prevents solder from being pulled away from the thermal-pad area during the reflow process. 7. Apply solder paste to the exposed thermal-pad area and all of the IC terminals. 8. With these preparatory steps in place, the TLC08x IC is simply placed in position and run through the solder reflow operation as any standard surface-mount component. This results in a part that is properly installed. For a given θJA, the maximum power dissipation is shown in Figure 55 and is calculated by the following formula: T MAX * T A PD + q JA Ǔ ǒ Where: PD TMAX TA θJA = Maximum power dissipation of TLC08x IC (watts) = Absolute maximum junction temperature (150°C) = Free-ambient air temperature (°C) = θJC + θCA θJC = Thermal coefficient from junction to case θCA = Thermal coefficient from case to ambient air (°C/W) (1) 20 Copyright © 2006–2011, Texas Instruments Incorporated TLC080-Q1, TLC081-Q1 TLC082-Q1, TLC083-Q1 TLC084-Q1, TLC085-Q1 SLOS510B – SEPTEMBER 2006 – REVISED MAY 2011 www.ti.com MAXIMUM POWER DISSIPATION vs FREE-AIR TEMPERATURE 7 PWP Package Low-K Test PCB θJA = 29.7°C/W Maximum Power Dissipation − W 6 5 DGN Package Low-K Test PCB θJA = 52.3°C/W 4 3 2 TJ = 150°C SOT-23 Package Low-K Test PCB θJA = 324°C/W SOIC Package Low-K Test PCB θJA = 176°C/W PDIP Package Low-K Test PCB θJA = 104°C/W 1 0 −55 −40 −25 −10 5 20 35 50 65 80 95 110 125 TA − Free-Air Temperature − °C A. Results are with no airflow and using JEDEC Standard Low-K test PCB. Figure 55. Maximum Power Dissipation vs Free-Air Temperature The next consideration is the package constraints. The two sources of heat within an amplifier are quiescent power and output power. The designer should never forget about the quiescent heat generated within the device, especially multi-amplifier devices. Because these devices have linear output stages (Class A-B), most of the heat dissipation is at low output voltages with high output currents. The other key factor when dealing with power dissipation is how the devices are mounted on the PCB. The PowerPAD devices are extremely useful for heat dissipation. But, the device should always be soldered to a copper plane to fully use the heat dissipation properties of the PowerPAD. The SOIC package, on the other hand, is highly dependent on how it is mounted on the PCB. As more trace and copper area is placed around the device, θJA decreases and the heat dissipation capability increases. The currents and voltages shown in Typical Characteristics are for the total package. For the dual or quad amplifier packages, the sum of the RMS output currents and voltages should be used to choose the proper package. Macromodel Information Macromodel information provided was derived using Microsim Parts™, the model generation software used with Microsim PSpice™. The Boyle macromodel (1) and subcircuit in Figure 56 are generated using the TLC08x typical electrical and operating characteristics at TA = 25°C. Using this information, output simulations of the following key parameters can be generated to a tolerance of 20% (in most cases): (1) • • • • • • G. R. Boyle, B. M. Cohn, D. O. Pederson, and J. E. Solomon, "Macromodeling of Integrated Circuit Operational Amplifiers," IEEE Journal of Solid-State Circuits, SC-9, 353 (1974). Maximum positive output voltage swing Maximum negative output voltage swing Slew rate Quiescent power dissipation Input bias current Open-loop voltage amplification Copyright © 2006–2011, Texas Instruments Incorporated • • • • • • Unity-gain frequency Common-mode rejection ratio Phase margin DC output resistance AC output resistance Short-circuit output current limit 21 TLC080-Q1, TLC081-Q1 TLC082-Q1, TLC083-Q1 TLC084-Q1, TLC085-Q1 SLOS510B – SEPTEMBER 2006 – REVISED MAY 2011 www.ti.com 99 3 VDD 9 RSS 92 FB 10 J1 DP VC J2 IN + 11 RD1 VAD DC 12 C1 R2 − 53 − C2 6 91 + VLP − − + VLN + GA GCM VLIM 8 − RD2 RO1 DE 5 54 4 DLP 7 60 + − + HLIM − + 90 RO2 VB IN − GND − + ISS RP 2 1 DLN EGND + − + VE *DEVICE=TLC08X_5V, OPAMP, PJF, INT * TLC08X_5V − 5V operational amplifier ”macromodel” subcircuit * created using Parts release 8.0 on 12/16/99 at 14:03 * Parts is a MicroSim product. * * connections: non-inverting input * inverting input * positive power supply * negative power supply * output * .subckt TLC08X_5V 1 2 3 4 5 * c1 11 12 4.6015E−12 c2 6 7 8.0000E−12 css 10 99 986.29E−15 dc 5 53 dy de 54 5 dy dlp 90 91 dx dln 92 90 dx dp 4 3 dx egnd 99 0 poly(2) (3,0) (4,0) 0 .5 .5 fb 7 99 poly(5) vb vc ve vlp vln 0 13.984E6 −1E3 1E3 14E6 −14E6 OUT ga gcm ioff iss hlim j1 j2 r2 rd1 rd2 ro1 ro2 rp rss vb vc ve vlim vlp vln .model .model .model .model .ends 6 0 0 3 90 11 12 6 4 4 8 7 3 10 9 3 54 7 91 0 dx dy jx1 jx2 0 11 12 402.12E−6 6 10 99 1.5735E−6 6 dc 1.212E−6 10 dc 130.40E−6 0 vlim 1K 2 10 jx1 1 10 jx2 9 100.00E3 11 2.4868E3 12 2.4868E3 5 10 99 10 4 2.8249E3 99 1.5337E6 0 dc 0 53 dc 1.5537 4 dc .84373 8 dc 0 0 dc 117.60 92 dc 117.60 D(Is=800.00E−18) D(Is=800.00E−18 Rs=1m Cjo=10p) PJF(Is=80.000E−15 Beta=1.2401E−3 Vto=−1) PJF(Is=80.000E−15 Beta=1.2401E−3 Vto=−1) Figure 56. Boyle Macromodel and Subcircuit 22 Copyright © 2006–2011, Texas Instruments Incorporated PACKAGE OPTION ADDENDUM www.ti.com 2-Jun-2011 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) TLC082QDGNRQ1 ACTIVE MSOPPowerPAD DGN 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR TLC084QPWPRQ1 ACTIVE HTSSOP PWP 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR Samples (Requires Login) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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OTHER QUALIFIED VERSIONS OF TLC082-Q1, TLC084-Q1 : • Catalog: TLC082, TLC084 NOTE: Qualified Version Definitions: Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 2-Jun-2011 • Catalog - TI's standard catalog product Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 1-Jun-2011 TAPE AND REEL INFORMATION *All dimensions are nominal Device TLC082QDGNRQ1 Package Package Pins Type Drawing MSOPPower PAD DGN 8 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2500 330.0 12.4 Pack Materials-Page 1 5.3 B0 (mm) K0 (mm) P1 (mm) 3.4 1.4 8.0 W Pin1 (mm) Quadrant 12.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 1-Jun-2011 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLC082QDGNRQ1 MSOP-PowerPAD DGN 8 2500 358.0 335.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. 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