CDC337 CLOCK DRIVER WITH 3-STATE OUTPUTS SCAS330B – DECEMBER 1990 – REVISED OCTOBER 1998 D D D D D D D DW PACKAGE (TOP VIEW) Low Output Skew, Low Pulse Skew for Clock-Distribution and Clock-Generation Applications TTL-Compatible Inputs and CMOS-Compatible Outputs Distributes One Clock Input to Eight Outputs – Four Same-Frequency Outputs – Four Half-Frequency Outputs Distributed VCC and Ground Pins Reduce Switching Noise High-Drive Outputs (– 48-mA IOH, 48-mA IOL) State-of-the-Art EPIC-ΙΙB BiCMOS Design Significantly Reduces Power Dissipation Package Options Include Plastic Small-Outline (DW) Y3 GND Y4 VCC OE CLR VCC Q4 GND Q3 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 Y2 GND Y1 VCC CLK GND VCC Q1 GND Q2 description The CDC337 is a high-performance, low-skew clock driver. It is specifically designed for applications requiring synchronized output signals at both the clock frequency and one-half the clock frequency. The four Y outputs switch in phase and at the same frequency as the clock (CLK) input. The four Q outputs switch at one-half the frequency of CLK. When the output-enable (OE) input is low and the clear (CLR) input is high, the Y outputs follow CLK and the Q outputs toggle on low-to-high transitions at CLK. Taking CLR low asynchronously resets the Q outputs to the low level. When OE is high, the outputs are in the high-impedance state. The CDC337 is characterized for operation from – 40°C to 85°C. FUNCTION TABLE INPUTS OUTPUTS OE CLR CLK Y1–Y4 Q1– Q4 H X X Z Z L L L L L L L H H L H L L L Q0† Q0† L H ↑ H † The level of the Q outputs before the indicated steady-state input conditions were established Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC-ΙΙB is a trademark of Texas Instruments Incorporated. Copyright 1998, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 CDC337 CLOCK DRIVER WITH 3-STATE OUTPUTS SCAS330B – DECEMBER 1990 – REVISED OCTOBER 1998 logic symbol† 5 OE logic diagram (positive logic) OE EN 18 18 20 CLK 1 16 3 13 T CLR 5 6 R 11 10 8 Y1 Y1 Y2 20 Y3 Y2 Y4 1 Q1 Y3 Q2 Q3 3 Q4 CLK † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. T CLR Y4 16 6 13 R 11 10 8 Q1 Q2 Q3 Q4 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡ Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V Voltage range applied to any output in the high state or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 0.5 V Current into any output in the low state, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 mA Maximum power dissipation at TA = 55°C (in still air) (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.6 W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C ĕ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils. For more information, refer to the Package Thermal Considerations application note in the 1994 ABT Advanced BiCMOS Technology Data Book, literature number SCBD002B. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 CDC337 CLOCK DRIVER WITH 3-STATE OUTPUTS SCAS330B – DECEMBER 1990 – REVISED OCTOBER 1998 recommended operating conditions (see Note 3) MIN MAX UNIT 4.75 5.25 V VCC VIH Supply voltage VIL VI Low-level input voltage IOH IOL High-level output current VCC – 48 mA Low-level output current 48 mA fclock TA Input clock frequency 80 MHz 85 °C High-level input voltage 2 V 0.8 Input voltage 0 Operating free-air temperature – 40 V V NOTE 3: Unused pins (input or I/O) must be held high or low to prevent them from floating. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT –1.2 V VIK VOH VCC = 4.75 V, VCC = 4.75 V, II = –18 mA IOH = – 32 mA VOL IIH VCC = 4.75 V, VCC = 5.25 V, IOL = 32 mA VI = 2.7 V 0.55 V 50 µA IIL IOZ VCC = 5.25 V, VCC = 5.25 V, VI = 0.5 V VO = VCC or GND – 50 µA ± 50 µA ICC Ci VCC = 5.25 V, VI = VCC or GND, 3.75 IO = 0 V Outputs high 70 Outputs low 85 Outputs disabled 70 VI = 2.5 V or 0.5 V VO = VCC or GND Co † All typical values are at VCC = 5 V, TA = 25°C. mA 3 pF 10 pF timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) MIN fclock Clock frequency tw Pulse duration tsu Setup time, CLR inactive before CLK↑ CLR low 4 CLK low 4 CLK high 4 MAX UNIT 80 MHz ns 2 Clock duty cycle 40% POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 ns 60% 3 CDC337 CLOCK DRIVER WITH 3-STATE OUTPUTS SCAS330B – DECEMBER 1990 – REVISED OCTOBER 1998 switching characteristics over recommended ranges of supply voltage and operating free-air temperature, CL = 50 pF (unless otherwise noted) (see Note 4 and Figures 1 and 2) PARAMETER fmax tPLH tPHL tPHL FROM (INPUT) TO (OUTPUT) TYP† MAX 80 CLK Any Y or Q CLR Any Q 9 4 9 4 10 3 7 3 7 2 7 2 7 OE Any Y or Q tPHZ tPLZ OE Any Y or Q Y↑ 0.75 tsk(o) ( ) CLK↑ ↑ Q↑ 0.9 Y↑ and Q↑ 0.9 † All typical values are at VCC = 5 V, TA = 25°C. NOTE 4: All specifications are valid only for all outputs switching. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 UNIT MHz 4 tPZH tPZL tr tf 4 MIN ns ns ns ns ns 0.9 ns 0.7 ns CDC337 CLOCK DRIVER WITH 3-STATE OUTPUTS SCAS330B – DECEMBER 1990 – REVISED OCTOBER 1998 PARAMETER MEASUREMENT INFORMATION 2 × VCC S1 500 Ω From Output Under Test TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open GND CL = 50 pF (see Note A) S1 Open 2 × VCC Open 500 Ω tw LOAD CIRCUIT 3V Input 3V 1.5 V 1.5 V 0V 1.5 V Timing Input 0V tsu VOLTAGE WAVEFORMS th 3V 1.5 V Data Input 1.5 V 0V VOLTAGE WAVEFORMS 1.5 V 0V tPHL 2V 0.8 V tr 1.5 V 0V tPLZ 1.5 V tPLH Output 1.5 V tPZL 3V Input 3V Output Control (low-level enabling) 50% VCC VOH 2V 0.8 V VOL tf ≈ VCC Output Waveform 1 S1 at 2 × VCC (see Note C) Output Waveform 2 S1 at Open (see Note C) 50% VCC VOL + 0.3 V VOL tPHZ tPZH VOLTAGE WAVEFORMS VOH 50% VCC VOH – 0.3 V ≈0V VOLTAGE WAVEFORMS NOTES: A. CL includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. D. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 CDC337 CLOCK DRIVER WITH 3-STATE OUTPUTS SCAS330B – DECEMBER 1990 – REVISED OCTOBER 1998 PARAMETER MEASUREMENT INFORMATION CLK Y1 tPLH1 tPLH9 tPLH2 tPLH10 tPLH3 tPLH11 tPLH4 tPLH12 Y2 Y3 Y4 Q1 tPLH5 Q2 tPLH6 Q3 tPLH7 Q4 tPLH8 NOTES: A. Output skew, tsk(o), from CLK↑ to Y↑, is calculated as the greater of the difference between the fastest and slowest of tPLHn (n = 1, 2, 3, 4) or tPLHn (n = 9, 10, 11, 12). B. Output skew, tsk(o), from CLK↑ to Q↑, is calculated as the greater of the difference between the fastest and slowest of tPLHn (n = 5, 6, 7, 8). C. Output skew, tsk(o), from CLK↑ to Y↑ and Q↑, is calculated as the greater of the difference between the fastest and slowest of tPLHn (n = 1, 2, . . . , 8). Figure 2. Waveforms for Calculation of tsk(o) 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 CDC337 CLOCK DRIVER WITH 3-STATE OUTPUTS SCAS330B – DECEMBER 1990 – REVISED OCTOBER 1998 MECHANICAL INFORMATION DW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 16 PIN SHOWN 0.050 (1,27) 0.020 (0,51) 0.014 (0,35) 16 0.010 (0,25) M 9 0.419 (10,65) 0.400 (10,15) 0.010 (0,25) NOM 0.299 (7,59) 0.293 (7,45) Gage Plane 0.010 (0,25) 1 8 0°– 8° A 0.050 (1,27) 0.016 (0,40) Seating Plane 0.104 (2,65) MAX 0.012 (0,30) 0.004 (0,10) 0.004 (0,10) PINS ** 16 20 24 A MAX 0.410 (10,41) 0.510 (12,95) 0.610 (15,49) A MIN 0.400 (10,16) 0.500 (12,70) 0.600 (15,24) DIM 4040000 / D 02/98 NOTES: A. B. C. D. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15). Falls within JEDEC MS-013 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. 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