ERICSSON PBL40309

Preliminary
PBL
4032000
09
August
PBL 403 09
3.6 V Differential Power Amplifier
for DECT Telecommunications system
Description.
Key features.
The PBL 403 09 is a differential two stage silicon MMIC power amplifier intended for
use in handheld cordless terminals in the 1900 MHz band. It can deliver more than 27
dBm at 1900 MHz into a balanced 50 Ω load using a single 3.6 V supply. The circuit has
a logic input to control transmit on/off and can be operated up to 100 % duty cycle with
minimum performance degradation. The circuit is housed in a specially designed
QSOP16 (150 mil body ) package and the implementation requires only few external
components.
25 GHz ft state-of-the-art deep trench isolated double-poly silicon bipolar process
with additional features for improved wireless performance has been used. On-chip
capacitors and inductors are used for the integrated internal matching network. Special
front-side metallized substrate contacts provide excellent ground paths from active
devices to the highly doped semiconductor substrate and package ground.
•
27 dBm output power
•
25 dB small signal gain
•
50 % Power Added Efficiency
•
Simple logic on/off power control
•
Battery charging conditions to 5.0 V
•
ESD protected
•
Excellent ruggedness
•
On-chip input and interstage
matching
•
Differential input matched to 50 Ω
•
Easy implementation with a simple
output matching network
•
Proven RF Silicon Technology
Reliability
•
Low overall solution cost
V CC
RF Out A & VCC
RF In A
Applications.
RF In B
RF Out B & VCC
•
DECT
0
3
4
0
L
B
P
PA-ON
9
Power Control
Figure 1. Block diagram.
Figure 2. Package outlook.
1
PBL 403 09
Maximum Ratings
Parameter
Supply voltage, continuous
All inputs (zener protection)
Operating case temperature
Storage temperature range
Symbol
Vcc
Min.
-
Top
TStg
Max.
5.2
6.5
+80
+100
-25
-30
Unit
V
V
°C
°C
Electrical Characteristics at room temperature
Unless otherwise stated the values below are valid for Vcc = 3.6 V, Pin = 4dBm, ZL = 50 Ω and f = 1900 MHz, pulsed mode
t = 417 µs, duty cycle 1/24. All data as measured in the recommended typical application circuit.
Parameter
Condition
Frequency range
Power output
Power Added Efficiency
Power Added Efficiency
Small signal Gain
Isolation
2 nd and 3 rd harmonics
Input VSWR
Load Mismatch
PA - ON = low
Pin = 10 dBm
Pin = 4 dBm
Pin = -10 dBm
PA - ON = high, Pin = 4 dBm
PA - ON = low, Pin < 4 dBm
Symbol
Min.
f
P
PAE
PAE
G
1880
27
45
35
Pin = 4-10 dBm, Vcc = 5.2 V,
Load VSWR = 6:1 all phases
Pin = 4-10 dBm, Vcc = 3.0-5.2 V,
Load VSWR = 5:1 all phases
No input signal present,
IDC
PA - ON = low
Pin = 4 dBm
IDC
PA - ON = high
IDC
Pout to 1dB from final value.
tr
Measure time from switch to low.
Pout to less than -20 dB measured tf
from PA - ON pulse switched to high
Stability and spurious
Supply current
Supply current
Supply current
Rise time
Fall time
MHz
dBm
%
%
dB
dB
dBc
All spurious below - 36 dBm
135
550
1
60
25
50
20
40
15
30
Pout [dBm]
10
20
Gain [dB]
0
0
5
10
15
Pin [dBm]
Figure 3. Pout, Gain and PAE vs. Pin
Vcc = 3.6 V
10
1
mA
µA
µA
2
µs
0.5
Vcc +0.5
130
V
V
µA
52
30
50
28
48
Pin = 10 dBm
46
Pin = 4 dBm
44
Pin = 10 dBm
26
10
PAE [%]
0
mA
54
Pout [dBm]
30
5
2
1930
29
50
43
25.5
-35
-30
-35
1.6:1
3:1
no damage for 10 sec.
32
Pout [dBm]
70
-5
Unit
110
35
-10
Max.
-0.5
Vcc -0.5
PAE [%]
Pout [dBm]or Gain [dB]
PA - ON = low
PA - ON = high
I ( PA - ON ) low
Typ.
42
Pin = 4 dBm
40
24
2
2.5
3
3.5
4
Vcc [V]
Figure 4. Pout vs. Vcc for Pin = 4 dBm
and 10 dBm
2
2.5
3
3.5
4
Vcc [V]
Figure 5. PAE vs.Vcc for Pin = 4 dBm
and 10 dBm
PBL 403 09
PA-ON 1
16 GND
GND 2
15 GND
14 RFoutA
RFinA 3
GND 4
13 GND
GND 5
12 GND
RFinB 6
11 RFoutB
10 GND
GND 7
Vcc 8
9
GND
Figure 6. Pin configuration.
Pin Descriptions:
Refer to pin configuration.
SO
Name
Function
SO
Name
Function
1
PA-ON
PA On/Off Control pin (active low)
9
GND
Common ground
2
GND
Common ground
10
GND
Common ground
3
RFinA
RF input
11
RFoutB
RF output
4
GND
Common ground
12
GND
Common ground
5
GND
Common ground
13
GND
Common ground
6
RFinB
RF input
14
RFoutA
RF output
7
GND
Common ground
15
GND
Common ground
8
Vcc
Supply voltage
16
GND
Common ground
Functional description.
PBL403 09 is a differential two stage integrated power amplifier intended for DECT. The circuit is manufactured in a bipolar 5.0 V
technology with additional features for improved wireless performance. Input and interstage matching is done completely on-chip,
tuned to 1.9 GHz, and only normal supply decoupling plus output matching is necessary. If the device is used in a single ended
environment, input and output transformers need to be added to the external circuitry.
PBL403 09 is optimized to work at a supply voltage of 3.6 V, but is able to operate between 2.7 and 5.2 V. At 3.6 V it can deliver up
to 31 dBm when driven into compression, while 27 dBm is guaranteed with an input power of 4 dBm. Best Power Added Efficiency
(PAE) is obtained close to maximum output power where PAE exeeds 50 %. Small signal gain is 25-26 dB. In a DECT handset with
the duty cycle 1/24, the average power dissipation in the circuit is low, normally between 30 to 40 mW. In the base station, the duty
cycle can increase and PBL403 09 can be operated at CW with a small penalty in power gain and output power (< 0.5 dB).
Operation is controlled through a power-on pin which is active low. When active, the current consumption is typically 135 mA without
any input signal present. When not active, current consumption is less than 10 µA.
3
PBL 403 09
Application information.
DECT SINGLE ENDED POWER AMPLIFIER
When used as a single ended power amplifier, please refer to fig.7 and the test board fig. 8.
The 50 Ω source impedance is converted to 50 Ω differential with an LC-CL structure. Two series capacitors AC-couples the signal
to the input of PBL403 09. Suitable value of the capacitors is 1 to 5 pF in order to compensate for series inductance of the PCB and
package. Input impedance of the PBL403 09 is 50 Ω differential.
The ideal collector load of the open collector RF output of PBL403 09 is about 11 Ω per side. A matching and combination network to
50 Ω single ended case is shown in fig. 7. A shunt capacitor (2.7 pF) transforms each output to 50 Ω. Both 50 Ω outputs are AC coupled
and then combined with an LC-CL structure to a 50 Ω single ended output.
PA-ON
Vcc
10n
100p
68
n
1.5p
3.9n
68
n
1.1p
33p
1.5p
5.6n
PBL 403 09
input
1.5p
output
33p
1.5p
3.9n
2.7p
GND
Figure 7. Evaluation setup including networks for unbalanced input/output.
Figure 8. Evaluation testboard.
4
100p
2.7p
1.1p
5.6n
PBL 403 09
DECT RADIO WITH PBL402 15 TRANSCEIVER
PBL403 09 together with the transceiver chip PBL402 15 form the base of the radio platform for DECT systems. The transmission
part of the chip PBL402 15 has a differential output which can deliver up to 7 dBm. The output power can be programmed in steps.
The outputs are of open-collector type. Suitable network between PBL402 15 and PBL403 09 is therefore shunt inductors from the
open-collectors to Vcc and series capacitors to the RF inputs of PBL403 09. Suitable value of the capacitors is 1 to 5 pF in order to
compensate for the series inductance of the PCB and package. Input impedance of the PBL403 09 is 50 Ω differential.
The ideal collector load of the open collector RF output of PBL403 09 is about 11 Ω per side. A matching and combination network to
50 Ω single ended case is shown in fig.9. A shunt capacitor (2.7 pF) transforms each output to 50 Ω. Both 50 Ω outputs are AC coupled
and then combined with an LC-CL structure to a 50 Ω single ended output.
A power control signal with active low is received from PBL402 15. This signal controls power up/down of the PBL403 09.
Supply decoupling consists of high frequency and low frequency decoupling capacitors. The high frequency decoupling capacitor
should be placed close to the Vcc pin.
25
41
PA-ON
Vcc
10n
33p
PBL 402 15
3.9n
100p
100p
3.9n
68
n
38
39
Tx-
8
1.5p
3
Tx+
6
1
PBL 403 09
68
n
1.1p
33p
5.6n
14
output
11
1.1p
33p
1.5p
2.7p
2.7p
5.6n
GND
Figure 9. DECT radio with PBL402 015 transceiver and PA.
5
PBL 403 09
Package drawing, QSOP 16
Dim.
D
e
E
H
millimeters
min.
max.
inches
min.
max.
A
1.35
1.75
0.532
0.688
A1
0.10
0.25
0.004
0.0098
0.30
0.008
0.012
0.01
B
0.20
C
0.15
0.25
0.006
D
4.80
4.98
0.189
0.i96
E
3.81
3.99
0.150
0.157
e
0.635mm
H
5.70
6.20
0.228
0.244
L
0.40
1.27
0.016
0.050
0.49
0.009
0.019
0.025 inch ref.
α = 0−8 deg.
h
Pin no 1
0.22
B
45 deg.
α
A
C
A1
L
Information given in this data sheet is believed to be accurate and reliable. However no responsibility is assumed
for the consequences of its use nor for any infringement of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Ericsson
Microelectronics AB. These products are sold only according to Ericsson Microelectronics AB's general conditions
of sale, unless otherwise confirmed in writing.
Specifications subject to change without
notice.
1522-PBL 403 09 Uen Rev.A
© Ericsson Microelectronics AB
August 2000
Ericsson Microelectronics AB
S-164 81 Kista-Stockholm, Sweden
Telephone: (08) 757 50 00
www.ericsson.se/microe
6
Ordering Information
Package
Temp. Range
Part No.
16 pin plastic QSOP
-25 to 80°C
PBL 403 09