Advance information PBL 403 10 March 2001 PBL 403 10 3.5 V GSM 900 MHz Power Amplifier Description. Key features. The PBL 40310 is a highly integrated single-ended silicon MMIC power amplifier intended for use in GSM terminals. It delivers 35 dBm at 900 MHz with 55 % power added efficiency into a 50 Ω unbalanced load using a single 3.5 V supply. The circuit has an analog ramp signal to control output power level and a logical on/ off signal for power down mode. It can be used in dual-band amplifiers using the band select logical signal. It can be operated up to 50 % duty cycle with minimum performance degradation. The circuit is housed in a specially designed QSOP16 (150 mil body) package and the implementation requires only few external components. 25 GHz ft state-of-the-art deep trench isolated double-poly silicon bipolar process with additional features for improved wireless performance has been used. On-chip capacitors and inductors are used for the integrated internal matching network. Special front-side metallized substrate contacts provide excellent ground paths from active devices to the highly doped semiconductor substrate and package ground. • 2.7 to 5.0 V single supply operation • 35 dBm output power at 3.5 V • 55 % Power Added Efficiency • Input matched to 50 Ω • Complete on chip input and interstage matching • Analog power control • Less than 10 µA current consumption in power down mode • Proven RF Silicon Technology Reliability • Minimum number of external components for low overall solution cost V CC RFin RFout B SEL Power Control Figure 1. Block diagram. BIAS TX - ON 10 L PB 3 40 Figure 2. Package outlook. 1 PBL 403 10 Maximum Ratings Parameter Symbol Min. Max. Unit Supply voltage, continuous Conditions VCC -0.5 Typ. 6.0 V Power control voltage VAPC -0.5 6.0 V Input power PIN +20 dBm Operating Case Temperature TOP -40 +85 °C Storage Temperature Range TSTORAGE -30 +100 °C Symbol Min. Max. Unit VCC 2.7 5.0 V DC Electrical Characteristics VCC = 3.5 V, TA= + 25°C unless otherwise stated. Parameter Conditions Supply voltage range Supply current VAPC= 2.5 V, no RF signal applied ICC Standby supply current VAPC<=0.5 V, TX-ON=HIGH ISTBY Power down leakage current VAPC<= 0.5 V, TX-ON=LOW ILEAK Input current, VAPC 0 < VAPC < 3.5 V Typ. 150 2.0 mA 3.0 mA 5.0 µA 3.0 mA Max. Unit AC Electrical Characteristics VCC = 3.5 V, fIN = 900 MHz, PIN = 8 dBm, VAPC = 2.5 V, TX-ON = high (VCC), BSEL = low (GND), duty cycle = 12.5 %, pulse width = 577 µs, TA = +25°C unless otherwise stated. All data measured on evaluation board. Parameter Symbol Min. Frequency range fIN 880 Input impedance ZIN 50 VSWR 2:1 Input VSWR Conditions PIN = -10 to +20 dBm Recommended input power Power gain PIN = 0 dBm PIN 8.0 Typ. 915 MHz Ω 12.0 dBm GP 30 31 dB Output power POUT 34.5 35 dBm Power added efficiency η 50 55 % 33 tbd tbd dBm dBc dBc Output power 2 nd harmonic 3 rd harmonic VCC = 2.9 V Output Noise RBW=100 kHz, f=925 to 935 MHz tbd dBm Output Noise RBW=100 kHz, f=925 to 960 MHz tbd dBm Forward isolation VAPC< 0.5 V, PIN = -10 to + 10 dBm -25 dB POUT 2 fo 3 fo Stability, load VSWR All phases, no oscillations. VSWR 6:1 Ruggedness, load VSWR All phases, no damage. VSWR 10:1 Power control for max. POUT VAPC Power control for min. POUT POUT< -30 dBm Power control slope -10 dBm < POUT< 35 dBm 2.5 V VAPC tbd 0.5 V tbd dB/V This document contains advance information of a new product. Data given in this document shall be considered as preliminary and may be changed without notice. 2 PBL 403 10 Vcc 1 16 GND Vcc 2 15 GND GND 3 14 GND RFin 4 13 RFout GND 5 12 RFout TX-ON 6 11 GND BSEL 7 10 GND VAPC 8 9 GND Figure 3. Pin configuration. Pin Descriptions: Refer to pin configuration. Function SO Name Function 1 Vcc Supply voltage 9 GND Common ground 2 Vcc Supply voltage 10 GND Common ground 3 GND Common ground 11 GND Common ground 4 RFin RF input 12 RFout RF output 5 GND Common ground 13 RFout RF output 6 TX-ON Transmit ON 14 GND Common ground 7 BSEL Band select 15 GND Common ground 8 VAPC Power control voltage 16 GND Common ground 40 80 35 70 30 60 25 50 20 40 15 V CC Eff (%) Name Pout [dBm], Gain (dB) SO 30 RFin Output power (dBm) 10 20 1 2 4 13 Gain (dB) 5 10 Efficiency (%) 0 0 -10 -5 0 5 Pin (dBm) Figure 4. RF performance. 10 RFout 12 Power Control 7 8 BIAS 6 B SEL TX-ON 15 Common ground Figure 5. Evaluation setup including network for unbalanced input/output. 3 PBL 403 10 Package drawing, QSOP 16 Dim. D e E H millimeters min. max. inches min. max. A 1.35 1.75 0.532 0.688 A1 0.10 0.25 0.004 0.0098 B 0.21 0.31 0.008 0.012 C 0.19 0.25 0.0075 0.0098 D 9.80 9.98 0.386 0.393 E 3.81 3.99 0.150 0.157 e 0.635mm H 5.70 6.20 0.2284 0.2240 L 0.41 1.27 0.016 0.050 0.025 inch ref. α = 0−8 deg. Pin no 1 B 45 deg. α A A1 C L Note: This package has been chosen as a preliminary package. It will possibly be changed to a smaller solution. This document contains advance information of a new product. Data given in this document shall be considered as preliminary and may bechanged without notice. Information given in this data sheet is believed to be accurate and reliable. However no responsibility is assumed for the consequences of its use nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Ericsson Microelectronics AB. These products are sold only according to Ericsson Microelectronics AB's general conditions of sale, unless otherwise confirmed in writing. Specifications subject to change without notice. 1522-PBL 403 10 Uen Rev.A © Ericsson Microelectronics AB March 2001 Ericsson Microelectronics AB S-164 81 Kista-Stockholm, Sweden Telephone: (08) 757 50 00 www.ericsson.se/microe 4