OP A1 41 OP A2 141 OPA141 OPA2141 OPA4141 OP A4 14 1 www.ti.com SBOS510B – MARCH 2010 – REVISED MAY 2010 Single-Supply, 10MHz, Rail-to-Rail Output, Low-Noise, JFET Amplifier Check for Samples: OPA141, OPA2141, OPA4141 FEATURES DESCRIPTION • • • • • • • • • • • • • The OPA141, OPA2141, and OPA4141 amplifier family is a series of low-power JFET input amplifiers that feature good drift and low input bias current. The rail-to-rail output swing and input range that includes V– allow designers to take advantage of the low-noise characteristics of JFET amplifiers while also interfacing to modern, single-supply, precision analog-to-digital converters (ADCs) and digital-to-analog converters (DACs). 1 2 Low Supply Current: 2.3mA max Low Offset Drift: 10mV/°C max Low Input Bias Current: 20pA max Very Low 1/f Noise: 250nVPP Low Noise: 6.5nV/√Hz Wide Bandwidth: 10MHz Slew Rate: 20V/ms Input Voltage Range Includes V– Rail-to-Rail Output Single-Supply Operation: 4.5V to 36V Dual-Supply Operation: ±2.25V to ±18V No Phase Reversal MSOP-8, TSSOP Packages APPLICATIONS • • • • • • • • Battery-Powered Instruments Industrial Controls Medical Instrumentation Photodiode Amplifiers Active Filters Data Acquisition Systems Portable Audio Automatic Test Systems 0.1Hz to 10Hz NOISE VSUPPLY = ±18V Competitor’s Device OPAx141 The OPA141 achieves 10MHz unity-gain bandwidth and 20V/ms slew rate while consuming only 1.8mA (typ) of quiescent current. It runs on a single 4.5 to 36V supply or dual ±2.25V to ±18V supplies. All versions are fully specified from –40°C to +125°C for use in the most challenging environments. The OPA141 (single) and OPA2141 (dual) versions are available in both MSOP-8 and SO-8 packages; the OPA4141 (quad) is available in the SO-14 and TSSOP-14 packages. RELATED PRODUCTS FEATURES PRODUCT Precision, Low-Power, 10MHz FET Input Industrial Op Amp OPA140(1) 2.2nV/√Hz, Low-Power, 36V Operational Amplifier in SOT-23 Package OPA209(1) Low-Noise, High-Precision, JFET-Input Operational Amplifier OPA827 Low-Noise, Low IQ Precision Operational Amplifier OPA376 High-Speed, FET-Input Operational Amplifier OPA132 200nV/div 1. Preview product; estimated availability in Q3 2010. Time (1s/div) 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2010, Texas Instruments Incorporated OPA141 OPA2141 OPA4141 SBOS510B – MARCH 2010 – REVISED MAY 2010 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ABSOLUTE MAXIMUM RATINGS (1) Over operating free-air temperature range (unless otherwise noted). VALUE UNIT ±20 V Supply Voltage Voltage Signal Input Terminals (2) (V–) –0.5 to (V+) +0.5 V ±10 mA Current (2) Output Short-Circuit (3) Continuous Operating Temperature, TA –55 to +150 °C Storage Temperature, TA –65 to +150 °C Junction Temperature, TJ +150 °C Human Body Model (HBM) 2000 V Charged Device Model (CDM) 500 V ESD Ratings (1) (2) (3) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not supported. Input terminals are diode-clamped to the power-supply rails. Input signals that can swing more than 0.5V beyond the supply rails should be current limited to 10 mA or less. Short-circuit to VS/2 (ground in symmetrical dual-supply setups), one amplifier per package. PACKAGE INFORMATION (1) PRODUCT OPA141 OPA2141 OPA4141 (1) PACKAGE-LEAD PACKAGE DESIGNATOR PACKAGE MARKING O141A SO-8 D MSOP-8 DGK 141 SO-8 D O2141A MSOP-8 DGK 2141 TSSOP-14 PW O4141A SO-14 D O4141AG4 For the most current package and ordering information see the Package Option Addendum at the end of this document, or visit the device product folder at www.ti.com. 2 Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): OPA141 OPA2141 OPA4141 OPA141 OPA2141 OPA4141 www.ti.com SBOS510B – MARCH 2010 – REVISED MAY 2010 THERMAL INFORMATION THERMAL METRIC OPA141, OPA2141 OPA141, OPA2141 D (SO) DGK (MSOP) (1) 8 8 qJA Junction-to-ambient thermal resistance (2) 160 180 qJC(top) Junction-to-case(top) thermal resistance (3) 75 55 (4) qJB Junction-to-board thermal resistance 60 130 yJT Junction-to-top characterization parameter (5) 9 n/a yJB Junction-to-board characterization parameter (6) 50 120 n/a n/a qJC(bottom) (1) (2) (3) (4) (5) (6) (7) Junction-to-case(bottom) thermal resistance (7) UNITS °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. The junction-to-top characterization parameter, yJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining qJA, using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-board characterization parameter, yJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining qJA , using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. THERMAL INFORMATION THERMAL METRIC OPA4141 OPA4141 D (SO) PW (TSSOP) (1) 14 14 qJA Junction-to-ambient thermal resistance (2) 97 135 qJC(top) Junction-to-case(top) thermal resistance (3) 56 45 qJB Junction-to-board thermal resistance (4) 53 66 19 n/a (5) yJT Junction-to-top characterization parameter yJB Junction-to-board characterization parameter (6) 46 60 qJC(bottom) Junction-to-case(bottom) thermal resistance (7) n/a n/a (1) (2) (3) (4) (5) (6) (7) UNITS °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. The junction-to-top characterization parameter, yJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining qJA, using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-board characterization parameter, yJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining qJA , using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): OPA141 OPA2141 OPA4141 3 OPA141 OPA2141 OPA4141 SBOS510B – MARCH 2010 – REVISED MAY 2010 www.ti.com ELECTRICAL CHARACTERISTICS: VS = +4.5V to +36V; ±2.25V to ±18V Boldface limits apply over the specified temperature range, TA = –40°C to +125°C. At TA = +25°C, RL = 2kΩ connected to midsupply, VCM = VOUT = midsupply, unless otherwise noted. OPA141, OPA2141, OPA4141 PARAMETER CONDITIONS MIN TYP MAX UNIT ±1 ±3.5 mV ±4.3 mV OFFSET VOLTAGE Offset Voltage, RTI VOS Over Temperature Drift vs Power Supply VS = ±18V VS = ±18V dVOS/dT PSRR xxxOver Temperature VS = ±18V ±2 ±10 mV/°C VS = ±2.25V to ±18V ±0.14 ±2 mV/V ±4 mV/V VS = ±2.25V to ±18V INPUT BIAS CURRENT Input Bias Current IB ±2 Over Temperature Input Offset Current IOS ±2 Over Temperature ±20 pA ±5 nA ±20 pA ±1 nA NOISE Input Voltage Noise f = 0.1Hz to 10Hz 250 nVPP f = 0.1Hz to 10Hz 42 nVRMS f = 10Hz 12 nV/√Hz f = 100Hz 6.5 nV/√Hz f = 1kHz 6.5 nV/√Hz 0.8 fA/√Hz Input Voltage Noise Density Input Current Noise Density en in f = 1kHz INPUT VOLTAGE RANGE Common-Mode Voltage Range Common-Mode Rejection Ratio VCM CMRR Over Temperature (V–) –0.1 VS = ±18V, VCM = (V–) –0.1V to (V+) – 3.5V 120 VS = ±18V, VCM = (V–) –0.1V to (V+) – 3.5V 120 (V+)–3.5 126 V dB dB INPUT IMPEDANCE Differential Common-Mode VCM = (V–) –0.1V to (V+) –3.5V 1013 || 8 Ω || pF 1013 || 6 Ω || pF OPEN-LOOP GAIN Open-Loop Voltage Gain AOL VO = (V–)+0.35V to (V+)–0.35V, RL = 2kΩ 114 Over Temperature VO = (V–)+0.35V to (V+)–0.35V, RL = 2kΩ 108 126 dB dB FREQUENCY RESPONSE Gain Bandwidth Product BW Slew Rate Settling Time, 12-bit (0.024) THD+N 1kHz, G = 1, VO = 3.5VRMS Overload Recovery Time 4 10 MHz 20 V/ms 880 ns 0.00005 % 600 ns Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): OPA141 OPA2141 OPA4141 OPA141 OPA2141 OPA4141 www.ti.com SBOS510B – MARCH 2010 – REVISED MAY 2010 ELECTRICAL CHARACTERISTICS: VS = +4.5V to +36V; ±2.25V to ±18V (continued) Boldface limits apply over the specified temperature range, TA = –40°C to +125°C. At TA = +25°C, RL = 2kΩ connected to midsupply, VCM = VOUT = midsupply, unless otherwise noted. OPA141, OPA2141, OPA4141 PARAMETER CONDITIONS MIN TYP MAX UNIT V OUTPUT Voltage Output Short-Circuit Current VO ISC RL = 10kΩ (V–)+0.2 (V+)–0.2 RL = 2kΩ (V–)+0.35 (V+)–0.35 Source Sink Capacitive Load Drive Open-Loop Output Impedance CLOAD RO V +36 mA –30 mA See Figure 19 and Figure 20 f = 1MHz, IO = 0 (See Figure 18) Ω 10 POWER SUPPLY Specified Voltage Range Quiescent Current (per amplifier) VS IQ ±2.25 IO = 0mA 1.8 Over Temperature ±18 V 2.3 mA 3.1 mA CHANNEL SEPARATION Channel Separation At dc 0.02 mV/V At 100kHz 10 mV/V TEMPERATURE RANGE Specified Range –40 +125 °C Operating Range –55 +150 °C Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): OPA141 OPA2141 OPA4141 5 OPA141 OPA2141 OPA4141 SBOS510B – MARCH 2010 – REVISED MAY 2010 www.ti.com PIN ASSIGNMENTS OPA141 SO-8, MSOP-8 (TOP VIEW) NC (1) -In OPA4141 SO-14, TSSOP-14 (TOP VIEW) 1 8 NC 2 7 V+ (1) Out A 1 -In A 2 A +In V- 3 6 4 5 Out NC (1) NC denotes no internal connection. OPA2141 SO-8, MSOP-8 (TOP VIEW) -In A 1 2 +In A 3 V- 4 A B Out D 13 -In D D +In A 3 12 +In D V+ 4 11 V- + In B 5 10 + In C (1) B OUT A 14 8 V+ 7 Out B 6 -In B 5 +In B C -In B 6 9 -In C Out B 7 8 Out C SIMPLIFIED BLOCK DIAGRAM V+ Pre-Output Driver IN- OUT IN+ V- Figure 1. 6 Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): OPA141 OPA2141 OPA4141 OPA141 OPA2141 OPA4141 www.ti.com SBOS510B – MARCH 2010 – REVISED MAY 2010 TYPICAL CHARACTERISTICS SUMMARY TABLE OF GRAPHS Table 1. Characteristic Performance Measurements DESCRIPTION FIGURE Offset Voltage Production Distribution Figure 2 Offset Voltage Drift Distribution Figure 3 Offset Voltage vs Common-Mode Voltage (Max Supply) Figure 4 IB and IOS vs Common-Mode Voltage Figure 5 Output Voltage Swing vs Output Current Figure 6 CMRR and PSRR vs Frequency (RTI) Figure 7 Common-Mode Rejection Ratio vs Temperature Figure 8 0.1Hz to 10Hz Noise Figure 9 Input Voltage Noise Density vs Frequency Figure 10 THD+N Ratio vs Frequency (80kHz AP Bandwidth) Figure 11 THD+N Ratio vs Output Amplitude Figure 12 Quiescent Current vs Temperature Figure 13 Quiescent Current vs Supply Voltage Figure 14 Gain and Phase vs Frequency Figure 15 Closed-Loop Gain vs Frequency Figure 16 Open-Loop Gain vs Temperature Figure 17 Open-Loop Output Impedance vs Frequency Figure 18 Small-Signal Overshoot vs Capacitive Load (G = +1) Figure 19 Small-Signal Overshoot vs Capacitive Load (G = –1) Figure 20 No Phase Reversal Figure 21 Positive Overload Recovery Figure 22 Negative Overload Recovery Figure 23 Small-Signal Step Response (G = +1) Figure 24 Small-Signal Step Response (G = –1) Figure 25 Large-Signal Step Response (G = +1) Figure 26 Large-Signal Step Response (G = –1) Figure 27 Short-Circuit Current vs Temperature Figure 28 Maximum Output Voltage vs Frequency Figure 29 Channel Separation vs Frequency Figure 30 Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): OPA141 OPA2141 OPA4141 7 OPA141 OPA2141 OPA4141 SBOS510B – MARCH 2010 – REVISED MAY 2010 www.ti.com TYPICAL CHARACTERISTICS At TA = +25°C, VS = ±18V, RL = 2kΩ connected to midsupply, VCM = VOUT = midsupply, unless otherwise noted. OFFSET VOLTAGE DRIFT DISTRIBUTION 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4 5.7 6.0 -3300 -3000 -2700 -2400 -2100 -1800 -1500 -1200 -900 -600 -300 0 300 600 900 1200 1500 1800 2100 2400 2700 3000 3300 Population Population OFFSET VOLTAGE PRODUCTION DISTRIBUTION Offset Voltage Drift (mV/°C) Offset Voltage (mV) Figure 2. Figure 3. OFFSET VOLTAGE vs COMMON-MODE VOLTAGE IB AND IOS vs COMMON-MODE VOLTAGE 10 3500 10 Typical Units Shown 8 2500 VS = ±18V 6 IB and IOS (pA) VOS (mV) 1500 500 0 -500 +IB 4 -IB 2 0 IOS -2 -4 -1500 -6 -2500 -8 -18 -12 0 -6 6 12 Common-Mode Range -10 -18 -3500 18 -12 Figure 4. 6 12 18 Figure 5. OUTPUT VOLTAGE SWING vs OUTPUT CURRENT (MAX SUPPLY) CMRR AND PSRR vs FREQUENCY (Referred to Input) 160 Common-Mode Rejection Ratio (dB) Power-Supply Rejection Ratio (dB) 18.0 17.5 17.0 Output Voltage (V) 0 -6 Common-Mode Voltage (V) VCM (V) 16.5 16.0 -40°C +25°C +85°C +125°C -16.0 -16.5 -17.0 -17.5 140 CMRR 120 100 -PSRR 80 +PSRR 60 40 20 0 -18.0 0 10 20 30 40 50 1 10 100 Output Current (mA) Figure 6. 1k 10k 100k 1M 10M 100M Frequency (Hz) Figure 7. 8 Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): OPA141 OPA2141 OPA4141 OPA141 OPA2141 OPA4141 www.ti.com SBOS510B – MARCH 2010 – REVISED MAY 2010 TYPICAL CHARACTERISTICS (continued) At TA = +25°C, VS = ±18V, RL = 2kΩ connected to midsupply, VCM = VOUT = midsupply, unless otherwise noted. COMMON-MODE REJECTION RATIO vs TEMPERATURE 0.1Hz to 10Hz NOISE 0.12 0.08 100nV/div CMRR (mV/V) 0.10 0.06 0.04 0.02 0 -75 -50 -25 0 25 75 50 100 125 Time (1s/div) 150 Temperature (°C) Figure 8. Figure 9. INPUT VOLTAGE NOISE DENSITY vs FREQUENCY THD+N RATIO vs FREQUENCY Total Harmonic Distortion + Noise (%) Voltage Noise Density (nV/ÖHz) 100 10 -100 VOUT = 3VRMS BW = 80kHz G = -1 RL = 2kW 0.0001 -120 G = +1 RL = 2kW 0.00001 -140 10 1 0.1 1 10 100 1k 10k Total Harmonic Distortion + Noise (dB) 0.001 100 100k 1k 10k 20k Frequency (Hz) Frequency (Hz) Figure 10. Figure 11. THD+N RATIO vs OUTPUT AMPLITUDE BW = 80kHz 1kHz Signal 0.001 -100 0.0001 -120 G = -1, RL = 2kW G = +1, RL = 2kW 0.00001 0.1 2.5 2.0 IQ (mA) Total Harmonic Distortion + Noise (%) QUIESCENT CURRENT vs TEMPERATURE -80 Total Harmonic Distortion + Noise (dB) 0.01 1.5 1.0 0.5 -140 1 10 Output Amplitude (VRMS) 20 0 -75 -50 -25 0 25 50 75 100 125 150 Temperature (°C) Figure 12. Figure 13. Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): OPA141 OPA2141 OPA4141 9 OPA141 OPA2141 OPA4141 SBOS510B – MARCH 2010 – REVISED MAY 2010 www.ti.com TYPICAL CHARACTERISTICS (continued) At TA = +25°C, VS = ±18V, RL = 2kΩ connected to midsupply, VCM = VOUT = midsupply, unless otherwise noted. GAIN AND PHASE vs FREQUENCY 1.75 120 1.50 100 1.25 80 Gain (dB) 140 1.00 0.75 180 Gain 135 90 60 40 Phase 45 20 0.50 0.25 0 Specified Supply-Voltage Range 0 100M -20 0 0 4 8 12 16 20 24 28 Phase (degrees) IQ (mA) QUIESCENT CURRENT vs SUPPLY VOLTAGE 2.00 32 10 36 100 1k 10k 100k 1M 10M Frequency (Hz) Supply Voltage (V) Figure 14. Figure 15. CLOSED-LOOP GAIN vs FREQUENCY OPEN-LOOP GAIN vs TEMPERATURE 30 0 10kW Load -0.2 20 -0.4 AOL (mV/V) Gain (dB) G = +10 10 G = +1 0 -0.6 2kW Load -0.8 -1.0 -10 -1.2 G = -1 -20 100k -1.4 1M 10M 100M -75 -50 -25 Frequency (Hz) 0 25 75 50 100 125 150 Temperature (°C) Figure 16. Figure 17. OPEN-LOOP OUTPUT IMPEDANCE vs FREQUENCY SMALL-SIGNAL OVERSHOOT vs CAPACITIVE LOAD (100mV Output Step) 1k 40 G = +1 +15V 35 ROUT ROUT = 0W 30 ZO (W) Overshoot (%) 100 10 OPA141 -15V RL CL 25 20 ROUT = 24W 15 ROUT = 51W 10 5 1 0 10 100 1k 10k 100k 1M 10M 100M 0 100 200 300 400 500 600 700 800 900 1000 Frequency (Hz) Capacitive Load (pF) Figure 18. Figure 19. 10 Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): OPA141 OPA2141 OPA4141 OPA141 OPA2141 OPA4141 www.ti.com SBOS510B – MARCH 2010 – REVISED MAY 2010 TYPICAL CHARACTERISTICS (continued) At TA = +25°C, VS = ±18V, RL = 2kΩ connected to midsupply, VCM = VOUT = midsupply, unless otherwise noted. SMALL-SIGNAL OVERSHOOT vs CAPACITIVE LOAD (100mV Output Step) NO PHASE REVERSAL 45 RI = 2kW 40 RF = 2kW G = -1 +15V ROUT = 0W ROUT 35 ROUT = 24W CL 30 -15V 5V/div Overshoot (%) Output OPA141 25 20 15 +18V OPA141 ROUT = 51W Output 10 -18V 37VPP Sine Wave (±18.5V) 5 0 0 Time (0.4ms/div) 100 200 300 400 500 600 700 800 900 1000 Capacitive Load (pF) Figure 20. Figure 21. POSITIVE OVERLOAD RECOVERY NEGATIVE OVERLOAD RECOVERY VOUT 5V/div 5V/div VIN 20kW 20kW 2kW VIN 2kW VOUT OPA141 OPA141 VIN VOUT G = +10 G = -10 Time (0.4ms/div) Time (0.4ms/div) Figure 22. Figure 23. SMALL-SIGNAL STEP RESPONSE (100mV) SMALL-SIGNAL STEP RESPONSE (100mV) CL = 100pF G = +1 OPA141 -15V RL 20mV/div 20mV/div CL = 100pF +15V VOUT VIN RI = 2kW RF = 2kW +15V OPA141 CL CL -15V G = -1 Time (100ns/div) Time (100ns/div) Figure 24. Figure 25. Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): OPA141 OPA2141 OPA4141 11 OPA141 OPA2141 OPA4141 SBOS510B – MARCH 2010 – REVISED MAY 2010 www.ti.com TYPICAL CHARACTERISTICS (continued) At TA = +25°C, VS = ±18V, RL = 2kΩ connected to midsupply, VCM = VOUT = midsupply, unless otherwise noted. LARGE-SIGNAL STEP RESPONSE LARGE-SIGNAL STEP RESPONSE G = +1 CL = 100pF 2V/div 2V/div G = -1 CL = 100pF Time (400ns/div) Time (400ns/div) Figure 26. Figure 27. SHORT-CIRCUIT CURRENT vs TEMPERATURE MAXIMUM OUTPUT VOLTAGE vs FREQUENCY 60 35 ISC, Source ISC, Sink Output Voltage (VPP) 50 ISC (mA) 40 30 20 10 25 20 15 VS = ±5V 10 VS = ±2.25V 5 Short-circuiting causes thermal shutdown; see Applications Information section. 0 Maximum output voltage range without slew-rate induced distortion VS = ±15V 30 0 -75 -50 -25 0 25 75 50 100 125 150 10k 100k 1M Temperature (°C) Frequency (Hz) Figure 28. Figure 29. 10M CHANNEL SEPARATION vs FREQUENCY Channel Separation (dB) -80 -90 VS = ±15V VOUT = 3VRMS G = +1 -100 RL = 600W -110 -120 RL = 2kW -130 RL = 5kW -140 10 100 1k 10k 100k Frequency (Hz) Figure 30. 12 Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): OPA141 OPA2141 OPA4141 OPA141 OPA2141 OPA4141 www.ti.com SBOS510B – MARCH 2010 – REVISED MAY 2010 APPLICATION INFORMATION OPERATING VOLTAGE The OPA141, OPA2141, and OPA4141 series of op amps can be used with single or dual supplies from an operating range of VS = +4.5V (±2.25V) and up to VS = +36V (±18V). These devices do not require symmetrical supplies; they only require a minimum supply voltage of +4.5V (±2.25V). For VS less than ±3.5V, the common-mode input range does not include midsupply. Supply voltages higher than +40V can permanently damage the device; see the Absolute Maximum Ratings table. Key parameters are specified over the operating temperature range, TA = –40°C to +125°C. Key parameters that vary over the supply voltage or temperature range are shown in the Typical Characteristics section of this data sheet. CAPACITIVE LOAD AND STABILITY The dynamic characteristics of the OPAx141 have been optimized for commonly encountered gains, loads, and operating conditions. The combination of low closed-loop gain and high capacitive loads decreases the phase margin of the amplifier and can lead to gain peaking or oscillations. As a result, heavier capacitive loads must be isolated from the output. The simplest way to achieve this isolation is to add a small resistor (ROUT equal to 50Ω, for example) in series with the output. Figure 19 and Figure 20 illustrate graphs of Small-Signal Overshoot vs Capacitive Load for several values of ROUT. Also, refer to Applications Bulletin AB-028 (literature number SBOA015, available for download from the TI web site) for details of analysis techniques and application circuits. with total circuit noise calculated. The op amp itself contributes both a voltage noise component and a current noise component. The voltage noise is commonly modeled as a time-varying component of the offset voltage. The current noise is modeled as the time-varying component of the input bias current and reacts with the source resistance to create a voltage component of noise. Therefore, the lowest noise op amp for a given application depends on the source impedance. For low source impedance, current noise is negligible, and voltage noise generally dominates. The OPA141, OPA2141, and OPA4141 family has both low voltage noise and extremely low current noise because of the FET input of the op amp. As a result, the current noise contribution of the OPAx141 series is negligible for any practical source impedance, which makes it the better choice for applications with high source impedance. The equation in Figure 31 shows the calculation of the total circuit noise, with these parameters: • en = voltage noise • In = current noise • RS = source impedance • k = Boltzmann's constant = 1.38 × 10–23 J/K • T = temperature in degrees Kelvin (K) For more details on calculating noise, see the section on Basic Noise Calculations. 10k Votlage Noise Spectral Density, EO The OPA141, OPA2141, and OPA4141 are unity-gain stable, operational amplifiers with very low noise, input bias current, and input offset voltage. Applications with noisy or high-impedance power supplies require decoupling capacitors placed close to the device pins. In most cases, 0.1mF capacitors are adequate. Figure 1 shows a simplified schematic of the OPA141. EO 1k OPA211 RS 100 OPA141 Resistor Noise 10 2 2 2 EO = en + (in RS) + 4kTRS 1 100 1k 10k 100k 1M Source Resistance, RS (W) NOISE PERFORMANCE Figure 31 shows the total circuit noise for varying source impedances with the operational amplifier in a unity-gain configuration (with no feedback resistor network and therefore no additional noise contributions). The OPA141 and OPA211 are shown Figure 31. Noise Performance of the OPA141 and OPA211 in Unity-Gain Buffer Configuration Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): OPA141 OPA2141 OPA4141 13 OPA141 OPA2141 OPA4141 SBOS510B – MARCH 2010 – REVISED MAY 2010 www.ti.com BASIC NOISE CALCULATIONS Low-noise circuit design requires careful analysis of all noise sources. External noise sources can dominate in many cases; consider the effect of source resistance on overall op amp noise performance. Total noise of the circuit is the root-sum-square combination of all noise components. The resistive portion of the source impedance produces thermal noise proportional to the square root of the resistance. This function is plotted in Figure 31. The source impedance is usually fixed; consequently, select the op amp and the feedback resistors to minimize the respective contributions to the total noise. A) Noise in Noninverting Gain Configuration Figure 32 illustrates both noninverting (A) and inverting (B) op amp circuit configurations with gain. In circuit configurations with gain, the feedback network resistors also contribute noise. In general, the current noise of the op amp reacts with the feedback resistors to create additional noise components. However, the extremely low current noise of the OPAx141 means that its current noise contribution can be neglected. The feedback resistor values can generally be chosen to make these noise sources negligible. Note that low impedance feedback resistors load the output of the amplifier. The equations for total noise are shown for both configurations. space Noise at the output: R2 2 2 O E R1 R2 = 1+ R1 2 R2 2 n e + 2 2 R1 2 e1 + e2 + 1 + R2 R1 es2 EO RS Where eS = 4kTRS = thermal noise of RS e1 = 4kTR1 = thermal noise of R1 e2 = 4kTR2 = thermal noise of R2 VS B) Noise in Inverting Gain Configuration Noise at the output: R2 2 2 EO R1 RS VS = 1+ R2 R1 + RS 2 R2 2 en + R 1 + RS 2 2 1 2 e + e2 + R2 R 1 + RS e s2 EO Where eS = 4kTRS = thermal noise of RS e1 = 4kTR1 = thermal noise of R1 e2 = 4kTR2 = thermal noise of R2 For the OPAx141 series of operational amplifiers at 1kHz, en = 6.5nV/√Hz. Figure 32. Noise Calculation in Gain Configurations 14 Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): OPA141 OPA2141 OPA4141 OPA141 OPA2141 OPA4141 www.ti.com SBOS510B – MARCH 2010 – REVISED MAY 2010 PHASE-REVERSAL PROTECTION The OPA141, OPA2141, and OPA4141 family has internal phase-reversal protection. Many FET- and bipolar-input op amps exhibit a phase reversal when the input is driven beyond its linear common-mode range. This condition is most often encountered in noninverting circuits when the input is driven beyond the specified common-mode voltage range, causing the output to reverse into the opposite rail. The input circuitry of the OPA141, OPA2141, and OPA4141 prevents phase reversal with excessive common-mode voltage; instead, the output limits into the appropriate rail (see Figure 21). OUTPUT CURRENT LIMIT The output current of the OPAx141 series is limited by internal circuitry to +36mA/–30mA (sourcing/sinking), to protect the device if the output is accidentally shorted. This short-circuit current depends on temperature, as shown in Figure 28. POWER DISSIPATION AND THERMAL PROTECTION The OPAx141 series of op amps are capable of driving 2kΩ loads with power-supply voltages of up to ±18V over the specified temperature range. In a single-supply configuration, where the load is connected to the negative supply voltage, the minimum load resistance is 2.8kΩ at a supply voltage of +36V. For lower supply voltages (either single-supply or symmetrical supplies), a lower load resistance may be used, as long as the output current does not exceed 13mA; otherwise, the device short-circuit current protection circuit may activate. Internal power dissipation increases when operating at high supply voltages. Copper leadframe construction used in the OPA141, OPA2141, and OPA4141 series devices improves heat dissipation compared to conventional materials. Printed circuit board (PCB) layout can also help reduce a possible increase in junction temperature. Wide copper traces help dissipate the heat by acting as an additional heatsink. Temperature rise can be further minimized by soldering the devices directly to the PCB rather than using a socket. Although the output current is limited by internal protection circuitry, accidental shorting of one or more output channels of a device can result in excessive heating. For instance, when an output is shorted to mid-supply, the typical short-circuit current of 36mA leads to an internal power dissipation of over 600mW at a supply of ±18V. In the case of a dual OPA2141 in an MSOP-8 package (thermal resistance qJA = 180°C/W), such power dissipation would lead the die temperature to be 220°C above ambient temperature, when both channels are shorted. This temperature increase significantly decreases the operating life of the device. In order to prevent excessive heating, the OPAx141 series has an internal thermal shutdown circuit, which shuts down the device if the die temperature exceeds approximately +180°C. Once this thermal shutdown circuit activates, a built-in hysteresis of 15°C ensures that the die temperature must drop to approximately +165°C before the device switches on again. Additional consideration should be given to the combination of maximum operating voltage, maximum operating temperature, load, and package type. Figure 33 and Figure 34 show several practical considerations when evaluating the OPA2141 (dual version) and the OPA4141 (quad version). As an example, the OPA4141 has a maximum total quiescent current of 12.4mA (3.1mA/channel) over temperature. The TSSOP-14 package has a typical thermal resistance of 135°C/W. This parameter means that because the junction temperature should not exceed 150°C in order to ensure reliable operation, either the supply voltage must be reduced, or the ambient temperature should remain low enough so that the junction temperature does not exceed 150°C. This condition is illustrated in Figure 33 for various package types. Moreover, resistive loading of the output causes additional power dissipation and thus self-heating, which also must be considered when establishing the maximum supply voltage or operating temperature. To this end, Figure 34 shows the maximum supply voltage versus temperature for a worst-case dc load resistance of 2kΩ. Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): OPA141 OPA2141 OPA4141 15 OPA141 OPA2141 OPA4141 SBOS510B – MARCH 2010 – REVISED MAY 2010 www.ti.com MAXIMUM SUPPLY VOLTAGE vs TEMPERATURE (Quiescent Condition) 20 TSSOP Quad SOIC Quad MSOP Dual SOIC Dual Maximum Supply Voltage (V) 18 16 14 12 10 8 6 4 2 0 80 90 100 110 120 130 140 150 160 Ambient Temperature (°C) Figure 33. Maximum Supply Voltage vs Temperature (OPA2141 and OPA4141), Quiescent Condition MAXIMUM SUPPLY VOLTAGE vs TEMPERATURE (Maximum DC Load on All Channels) 20 TSSOP Quad SOIC Quad MSOP Dual SOIC Dual Maximum Supply Voltage (V) 18 16 14 12 10 VCC+ 8 VS V+ 6 VS/2 V- 4 2kW VS 2 VS/2 VCC- 0 80 90 100 110 120 130 140 150 160 Ambient Temperature (°C) Figure 34. Maximum Supply Voltage vs Temperature (OPA2141 and OPA4141), Maximum DC Load ELECTRICAL OVERSTRESS Designers often ask questions about the capability of an operational amplifier to withstand electrical overstress. These questions tend to focus on the device inputs, but may involve the supply voltage pins or even the output pin. Each of these different pin functions have electrical stress limits determined by the voltage breakdown characteristics of the particular semiconductor fabrication process and specific circuits connected to the pin. Additionally, internal electrostatic discharge (ESD) protection is built into these circuits to protect them from accidental ESD events both before and during product assembly. It is helpful to have a good understanding of this basic ESD circuitry and its relevance to an electrical overstress event. See Figure 35 for an illustration of the ESD circuits contained in the OPAx141 series (indicated by the dashed line area). The ESD protection circuitry involves several current-steering diodes connected from the input and output pins and routed back to the internal power-supply lines, where they meet at an absorption device internal to the operational amplifier. This protection circuitry is intended to remain inactive during normal circuit operation. An ESD event produces a short duration, high-voltage pulse that is transformed into a short duration, high-current pulse as it discharges through a semiconductor device. The ESD protection circuits are designed to provide a current path around the operational amplifier core to prevent it from being damaged. The energy absorbed by the protection circuitry is then dissipated as heat. When an ESD voltage develops across two or more of the amplifier device pins, current flows through one or more of the steering diodes. Depending on the path that the current takes, the absorption device may activate. The absorption device has a trigger, or threshold voltage, that is above the normal operating voltage of the OPAx141 but below the device breakdown voltage level. Once this threshold is exceeded, the absorption device quickly activates and clamps the voltage across the supply rails to a safe level. When the operational amplifier connects into a circuit such as the one Figure 35 shows, the ESD protection components are intended to remain inactive and not become involved in the application circuit operation. However, circumstances may arise where an applied voltage exceeds the operating voltage range of a given pin. Should this condition occur, there is a risk that some of the internal ESD protection circuits may be biased on, and conduct current. Any such current flow occurs through steering diode paths and rarely involves the absorption device. 16 Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): OPA141 OPA2141 OPA4141 OPA141 OPA2141 OPA4141 www.ti.com SBOS510B – MARCH 2010 – REVISED MAY 2010 Figure 35 depicts a specific example where the input voltage, VIN, exceeds the positive supply voltage (+VS) by 500mV or more. Much of what happens in the circuit depends on the supply characteristics. If +VS can sink the current, one of the upper input steering diodes conducts and directs current to +VS. Excessively high current levels can flow with increasingly higher VIN. As a result, the datasheet specifications recommend that applications limit the input current to 10mA. Again, it depends on the supply characteristic while at 0V, or at a level below the input signal amplitude. If the supplies appear as high impedance, then the operational amplifier supply current may be supplied by the input source via the current steering diodes. This state is not a normal bias condition; the amplifier most likely will not operate normally. If the supplies are low impedance, then the current through the steering diodes can become quite high. The current level depends on the ability of the input source to deliver current, and any resistance in the input path. If the supply is not capable of sinking the current, VIN may begin sourcing current to the operational amplifier, and then take over as the source of positive supply voltage. The danger in this case is that the voltage can rise to levels that exceed the operational amplifier absolute maximum ratings. If there is an uncertainty about the ability of the supply to absorb this current, external zener diodes may be added to the supply pins as shown in Figure 35. The zener voltage must be selected such that the diode does not turn on during normal operation. Another common question involves what happens to the amplifier if an input signal is applied to the input while the power supplies +VS and/or –VS are at 0V. However, its zener voltage should be low enough so that the zener diode conducts if the supply pin begins to rise above the safe operating supply voltage level. (2) TVS RF +V +VS OPA141 RI ESD CurrentSteering Diodes -In (3) RS +In Op Amp Core Edge-Triggered ESD Absorption Circuit ID VIN Out RL (1) -V -VS (2) TVS (1) VIN = +VS + 500mV. (2) TVS: +VS(max) > VTVSBR (Min) > +VS (3) Suggested value approximately 1kΩ. Figure 35. Equivalent Internal ESD Circuitry and Its Relation to a Typical Circuit Application Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): OPA141 OPA2141 OPA4141 17 PACKAGE OPTION ADDENDUM www.ti.com 1-May-2010 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty Lead/Ball Finish MSL Peak Temp (3) OPA141AID PREVIEW SOIC D 8 75 TBD Call TI Call TI OPA141AIDGKR PREVIEW MSOP DGK 8 2500 TBD Call TI Call TI OPA141AIDGKT PREVIEW MSOP DGK 8 250 TBD Call TI Call TI OPA141AIDR PREVIEW SOIC D 8 2500 TBD Call TI Call TI OPA2141AID PREVIEW SOIC D 8 75 TBD Call TI Call TI OPA2141AIDGKR PREVIEW MSOP DGK 8 2500 TBD Call TI Call TI OPA2141AIDGKT PREVIEW MSOP DGK 8 250 TBD Call TI Call TI OPA2141AIDR PREVIEW SOIC D 8 2500 TBD Call TI Call TI OPA4141AID PREVIEW SOIC D 14 50 TBD Call TI Call TI OPA4141AIDR PREVIEW SOIC D 14 2500 TBD Call TI Call TI OPA4141AIPW PREVIEW TSSOP PW 14 90 TBD Call TI Call TI OPA4141AIPWR PREVIEW TSSOP PW 14 2000 TBD Call TI Call TI (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 1 MECHANICAL DATA MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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