HAF2011(L),HAF2011(S) Silicon N Channel MOS FET Series Power Switching Target specification ADE-208-738 (Z) 1st. Edition Jan. 1999 Features This FET has the over temperature shut–down capability sensing to the junction temperature. This FET has the built–in over temperature shut–down circuit in the gate area. And this circuit operation to shut–down the gate voltage in case of high junction temperature like applying over power consumption, over current etc. • • • • Logic level operation (4 to 6 V Gate drive) High endurance capability against to the short circuit Built–in the over temperature shut–down circuit Latch type shut–down operation (Need 0 voltage recovery) Outline LDPAK D 4 4 Gate resistor G Tempe– rature Sencing Circuit Latch Circuit Gate Shut– down Circuit 1 1 S 2 3 2 3 1. Gate 2. Drain 3. Source 4. Drain HAF2011(L),HAF2011(S) Absolute Maximum Ratings (Ta = 25°C) Item Symbol Ratings Unit Drain to source voltage VDSS 60 V Gate to source voltage VGSS 16 V Gate to source voltage VGSS –2.5 V Drain current ID 40 A 80 A 40 A 50 W Drain peak current I D(pulse) Body-drain diode reverse drain current I DR Note1 Note2 Channel dissipation Pch Channel temperature Tch 150 °C Storage temperature Tstg –55 to +150 °C Note: 1. PW ≤ 10µs, duty cycle ≤ 1 % 2. Value at Ta = 25°C Typical Operation Characteristics Item Symbol Min Typ Max Unit Input voltage VIH 3.5 — — V VIL — — 1.2 V Input current I IH1 — — 100 µA Vi = 8V, VDS = 0 (Gate non shut down) I IH2 — — 50 µA Vi = 3.5V, VDS = 0 I IL — — 1 µA Vi = 1.2V, VDS = 0 Input current I IH(sd)1 — 0.8 — mA Vi = 8V, VDS = 0 (Gate non shut down) I IH(sd)2 — 0.35 — mA Vi = 3.5V, VDS = 0 Shut down temperature Tsd — 175 — °C Channel temperature Gate operation voltage VOP 3.5 — 12 V 2 Test Conditions HAF2011(L),HAF2011(S) Electrical Characteristics (Ta = 25°C) Item Symbol Min Typ Max Unit Test Conditions Drain current I D1 (25) — — A VGS = 3.5V, VDS = 2V Drain current I D2 — — 10 mA VGS = 1.2V, VDS = 2V Drain to source breakdown voltage V(BR)DSS 60 — — V I D = 10mA, VGS = 0 Gate to source breakdown voltage V(BR)GSS (16) — — V I G = (300µA), VDS = 0 Gate to source breakdown voltage V(BR)GSS (–2.5) — — V I G = (–100µA), VDS = 0 Gate to source leak current I GSS1 — — 100 µA VGS = 8V, VDS = 0 I GSS2 — — 50 µA VGS = 3.5V, VDS = 0 I GSS3 — — 1 µA VGS = 1.2V, VDS = 0 I GSS4 — — –100 µA VGS = –2.4V, VDS = 0 I GS(op)1 — 0.8 — mA VGS = 8V, VDS = 0 I GS(op)2 — 0.35 — mA VGS = 3.5V, VDS = 0 I DSS — — 250 µA VDS = 50 V, VGS = 0 Gate to source cutoff voltage VGS(off) 1.0 — 2.25 V I D = 1mA, VDS = 10V Static drain to source on state RDS(on) resistance — 25 33 mΩ I D = 20A, VGS = 4V Note3 Static drain to source on state RDS(on) resistance — 15 20 mΩ I D = 20A, VGS = 10V Note3 Forward transfer admittance |yfs| 25 50 — S I D = 20A, VDS = 10V Note3 Output capacitance Coss — 940 — pF VDS = 10V , VGS = 0 f = 1 MHz Turn-on delay time t d(on) — (7.8) — µs I D = 5A, VGS = 5V Rise time tr — (64) — µs RL = 6Ω Turn-off delay time t d(off) — (19) — µs Fall time tf — (30) — µs Body–drain diode forward voltage VDF — (0.85) — V I F = 40A, VGS = 0 Body–drain diode reverse recovery time t rr — ( — ns I F = 40A, VGS = 0 Over load shut down t os1 — ( ) — ms VGS = 5V, VDD = 12V t os2 — ( ) — ms VGS = 5V, VDD = 24V Input current (shut down) Zero gate voltege drain current operation time Note: Note4 ) diF/ dt =50A/µs 3. Pulse test 4. Include the time shiff based on increasing of chennel temperature when operete under over load condition. 3 HAF2011(L),HAF2011(S) Main Characteristics Power vs. Temperature Derating Channel Dissipation Pch (W) 80 60 40 20 0 50 100 Case Temperature 4 150 Tc (°C) 200 HAF2011(L),HAF2011(S) Package Dimensions 1.2 ± 0.2 0.4 ± 0.1 2.54 ± 0.5 2.54 ± 0.5 L type 2.54 ± 0.5 (1.4) (1.5) (1.5) 1.27 ± 0.2 3.0 +0.3 –0.5 2.59 ± 0.2 4.44 ± 0.2 8.6 ± 0.3 10.0 +0.3 –0.5 10.2 ± 0.3 1.27 ± 0.2 0.76 ± 0.1 1.3 ± 0.2 11.3 ± 0.5 4.44 ± 0.2 11.0 ± 0.5 1.2 ± 0.2 0.86 +0.2 –0.1 8.6 ± 0.3 10.0 +0.3 –0.5 (1.5) 10.2 ± 0.3 (1.4) Unit: mm 1.3 ± 0.2 0.1 +0.2 –0.1 2.59 ± 0.2 0.4 ± 0.1 0.86 +0.2 –0.1 2.54 ± 0.5 S type Hitachi Code EIAJ JEDEC LDPAK — — 5 Cautions 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. 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