TI TLC5970RHPR

TLC5970
www.ti.com
SBVS140 – MARCH 2010
3-Channel, 12-Bit, PWM LED Driver with
Buck DC/DC Converter and Differential Signal Interface
Check for Samples: TLC5970
FEATURES
APPLICATIONS
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1
23
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3-Channel, Constant-Current Sink Output
Current Capability: 150 mA per channel
Grayscale (GS) Control with PWM:
12-bit (4096 steps)
Dot Correction (DC): 7-bit (128 steps)
Global Brightness Control (BC):
7-bit (128 steps)
EEPROM for Dot Correction Storage
Input Voltage: Up to 36 V
LED Supply Voltage: Up to 17 V with Auto LED
Anode Voltage Control
Constant-Current Accuracy:
– Channel-to-Channel = ±0.5% (typ)
– Device-to-Device = ±3% (typ)
Data Transfer Rate: 20 MHz
Differential Signal Interface for Long Distance
Cascading
Unlimited Device Cascading
Auto Display Repeat/Auto Data Refresh
Internal/External Selectable GS Clock
Thermal Shutdown (TSD)
Packages: HTSSOP-32 and QFN-28
•
Full-Color Static LED Displays for Building
Wall
Long Distance and Large Area Illumination
DESCRIPTION
The TLC5970 is a three-channel, constant-current
sink driver with a buck dc/dc converter and a
differential signal interface. Each channel has
individually adjustable currents with 4096 PWM
grayscale (GS) steps and 128 constant-current sink
steps for dot correction (DC). The dot correction
adjusts the brightness variations between LEDs. The
DC data can be stored in the internal EEPROM. Also,
current through all three channels can be controlled
by global brightness control (BC) data with 128 steps.
GS control, DC, and BC are accessible via a
differential signal interface. The maximum current
value for each channel is set by a single external
resistor. The TLC5970 contains a dc/dc buck
converter. The dc/dc converter improves system
efficiency, reduces system level currents, and allows
thinner gauge wiring by optimizing the LED anode
voltage to keep the LED cathode voltage to 1 V. The
TLC5970 proivdes overtemperature protection by
turning all output drivers off when the IC temperature
is too high (exceeds +138°C).
VCC
Power
Supply
GND
GND
VCC
SWOFF
0.01 mF
VREG
0.1 mF
PH
BOOT
VREGIF
FB
GND
0.01 mF
0.1 mF
IREF2
Controller
Open
SDTY
SDTZ
SDKY
SDKZ
VCC
SWOFF
0.01 mF
VREG
PH
0.01 mF
BOOT
VREGIF
FB
IREF2
IREF1
OUT2
IREF1
OUT2
IREF0
OUT1
IREF0
OUT1
VROM
OUT0
VROM
OUT0
SDTA
SDTY
SDTA
SDTY
SDTB
SDTZ
SDTB
SDTZ
SCKA
SCKY
SCKA
SCKY
SCKB
SCKZ
SCKB
SCKZ
TLC5970
Open
TLC5970
Typical Application Circuit Example
1
2
3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments Incorporated.
All other trademarks are the property of their respective owners.
UNLESS OTHERWISE NOTED this document contains
PRODUCTION DATA information current as of publication date.
Products conform to specifications per the terms of Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010, Texas Instruments Incorporated
TLC5970
SBVS140 – MARCH 2010
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION (1)
PRODUCT
PACKAGE-LEAD
HTSSOP-32 PowerPAD™ (2)
TLC5970
QFN-28 6.0 mm × 6.0 mm
(1)
(2)
ORDERING NUMBER
TRANSPORT MEDIA,
QUANTITY
TLC5970DAPR
Tape and Reel, 2000
TLC5970DAP
Tube, 46
TLC5970RHPR
Tape and Reel, 3000
TLC5970RHPT
Tape and Reel, 250
For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
Product preview device.
ABSOLUTE MAXIMUM RATINGS (1) (2)
Over operating free-air temperature range, unless otherwise noted.
VALUE
Supply voltage
Input voltage
MAX
VCC
–0.3
+40
V
BOOT
–0.3
+50
V
BOOT-PH difference
–0.3
+10
V
FB
–0.3
+18
V
IREF0 to IREF2, SWOFF
–0.3
VREG + 0.3
V
SDTA, SDTB, SCKA, SCKB
–10
+15
V
VROM
–0.3
+21
V
PH (steady-state)
–0.6
+40
V
–1.2
V
PH (transient < 10 ns)
Output voltage
OUT0 to OUT2
–0.3
+18
V
SDTY, SDTZ, SCKY, SCKZ
–10
+15
V
VREG, VREGIF
–0.3
+6
PH (dc)
Output current
–800
PH (peak)
–2
OUT0 to OUT2
SDTY, SDTZ, SCKY, SCKZ
Electrostatic discharge rating
–35
mA
mA
4
kV
Human body model (HBM) Other pins
2
kV
1000
V
Charged device model (CDM) SDTA, SDTB, SCKA, SCKB,
SDTY, SDTZ, SCKY, SCKZ
TJ
Storage temperature
Tstg
2
A
+180
+35
Charged device model (CDM) Other pins
(2)
V
mA
Human body model (HBM) SDTA, SDTB, SCKA, SCKB,
SDTY, SDTZ, SCKY, SCKZ
Operation junction temperature
(1)
UNIT
MIN
(max)
–55
500
V
+150
°C
+150
°C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground terminal.
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TLC5970
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SBVS140 – MARCH 2010
THERMAL INFORMATION
TLC5970
THERMAL METRIC (1)
RHP
UNITS
28
qJA
Junction-to-ambient thermal resistance (2)
qJC(top)
Junction-to-case(top) thermal resistance
qJB
Junction-to-board thermal resistance
26.7
(3)
11.7
(4)
5.3
(5)
yJT
Junction-to-top characterization parameter
yJB
Junction-to-board characterization parameter
qJC(bottom)
(1)
(2)
(3)
(4)
(5)
(6)
(7)
Junction-to-case(bottom) thermal resistance
0.4
(6)
°C/W
5.2
(7)
1.6
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, High-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
The junction-to-case(top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-standard
test exists, but a close description can be found in the ANSI SEMI standard G30-88.
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
The junction-to-top characterization parameter, yJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining qJA, using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-board characterization parameter, yJB estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining qJA , using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-case(bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
DISSIPATION RATINGS
(1)
(2)
(3)
(4)
PACKAGE
DERATING FACTOR
ABOVE TA = +25°C
POWER RATING
TA < +25°C
POWER RATING
TA = +70°C
POWER RATING
TA = +85°C
HTSSOP-32
with PowerPAD soldered (1) (2)
42.5 mW/°C
5318 mW
3403 mW
2765 mW
HTSSOP-32
with PowerPAD unsoldered (2) (3)
22.5 mW/°C
2820 mW
1805 mW
1466 mW
QFN-28
bottom side heat sink soldered (4)
33.2 mW/°C
4149 mW
2655 mW
2157 mW
With PowerPAD soldered onto copper area on printed circuit board (PCB); 2-oz. copper. For more information, see application report
SLMA002, PowerPAD Thermally-Enhanced Package (available for download at www.ti.com).
Product preview device.
With PowerPAD not soldered onto copper area on PCB.
The package thermal impedance is calculated in accordance with JESD51-5.
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TLC5970
SBVS140 – MARCH 2010
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RECOMMENDED OPERATING CONDITIONS
At TA = –40°C to +85°C, unless otherwise noted.
TLC5970
MIN
NOM
MAX
UNIT
DC CHARACTERISTICS
VCC
Supply voltage
VCC1
VI
VCC = SWOFF = VREG = VREFIF = FB
(no buck conver operation mode)
FB (buck converter operation mode)
VI1
Voltage at input terminal
VI2
SDTA, SDTB, SCKA, SCKB
10
36
V
4.75
5.5
V
7
17
V
–7
12
V
19.5
V
VROM for data writing
18.5
19
–12
12
V
VID
Differential voltage at input terminal (1)
SDTA-SDTB, SCKA-SCKB
VIH
High level input voltage
SWOFF
0.7 × VREG
VREG
V
VIL
Low level input voltage
SWOFF
GND
0.3 × VREG
V
VO
Voltage at output terminal
OUT0 to OUT2
17
V
IOLC
Constant output sink current
OUT0 to OUT2
150
mA
IOH
High level output current
SDTY, SDTZ, SCKY, SCKZ
IOL
Low level output current
SDTY, SDTZ, SCKY, SCKZ
TA
Operating free-air temperature
TJ
Operating junction temperature
–30
mA
30
mA
–40
+85
°C
–40
+125
°C
AC CHARACTERISTICS
fCLK
Data shift clock frequency
SCKA-SCKB
TWH/TWL
Pulse duration
SCKA-SCKB
TSU
Setup time
TH
NROM
(1)
4
20
MHz
12
ns
(SDTA-SDTB)-(SCKA-SCKB) ↑
5
ns
Hold time
(SDTA-SDTB)-(SCKA-SCKB) ↑
3
Number of EEPROM write cycles
At each address
ns
10
Times
Differential input voltage is measured at the noninverting terminal with respect to the inverting terminal.
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SBVS140 – MARCH 2010
ELECTRICAL CHARACTERISTICS
At VCC = 10 V to 36 V and TA = –40°C to +85°C. Typical values at VCC = 24 V, FB = 17 V, and TA = +25°C, unless otherwise
noted.
TLC5970
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
300
770
MΩ
BUCK DC/DC CONVERTER BLOCK
RDSON
High-side MOS switch on-resistance
At PH pin. VCC = 10 V to 36V, IO = 500mA,
VBOOT = VCC + 9 V,
PH high-side MOS switch is on
RDSOFF
High-side MOS switch off-resistance
At PH pin. VCC = 36 V, PH = 0 V,
PH high-side MOS switch is off
1
MΩ
At BOOT pin. VCC = 10 V, IBOOT = –10 mA,
PH high-side MOS switch is off
8
V
VBOOT
Boot regulator output voltage
VBOOT1
VSCP
Short-circuit protection detection
At BOOT pin. VCC = 36 V, PH = 0 V,
IBOOT = no load,
PH high-side MOS switch is off
3.75
V
V
4
4.25
IFB
At FB pin. SDTA/SCKA = 0 V, SDTB/SCKB = 3 V,
SDTY/SDTZ/SCKY/SCKZ/PH/BOOT = open,
FB = 7 V to 17 V, VOUTn = 1.0 V, GSn = 000h,
DCn = BC = 7Fh, RIREF = 15 kΩ,
internal oscillator mode, and auto repeat mode
18
29
mA
IFB1
At FB pin. SDTA/SCKA = 0 V, SDTB/SCKB = 3 V,
SDTY/SDTZ/SCKY/SCKZ/PH/BOOT = open,
FB = 7 V to 17 V, VOUTn = 1.0 V, GSn = 000h,
DCn = BC = 7Fh, RIREF = 2 kΩ,
internal oscillator mode, and auto repeat mode
19
30
mA
IFB2
At FB pin. SDTA/SDTB = 10 MHz,
SCKA/SCKB = 20 MHz with 0 V to 3 V swing,
SDTY-SDTZ/SCKY-SCKZ = RLDIF = 10 kΩ,
CLDIF = 15 pF, PH/BOOT = open, FB = 7 V to 17 V,
VOUTn = 1.0 V, GSn = FFFh, DCn = BC = 7Fh,
RIREF = 2 kΩ, internal oscillator mode,
and auto repeat mode
36
60
mA
IFB3
At FB pin. SDTA/SDTB = 10 MHz,
SCKA/SCKB = 20 MHz with 0 V to 3 V swing,
SDTY-SDTZ/SCKY-SCKZ = RLDIF = 2 × 51 Ω,
CLDIF = 50 pF, PH/BOOT = open, FB = 7 V to 17 V,
VOUTn = 1.0 V, GSn = FFFh, DCn = BC = 7Fh,
RIREF = 2 kΩ, internal oscillator mode,
and auto repeat mode
65
115
mA
IFB4
At FB pin. SDTA/SDTB = 10 MHz,
SCKA/SCKB = 20 MHz with 0 V to 3 V swing,
SDTY-SDTZ/SCKY-SCKZ = RLDIF = 2 × 51 Ω,
CLDIF = 50 pF, PH/BOOT = open, FB = 7 V to 17 V,
VOUTn = 1.0 V, GSn = FFFh, DCn = BC = 7Fh,
RIREF = 1 kΩ, internal oscillator mode,
and auto repeat mode
68
130
mA
Input current
At FB pin
10
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ELECTRICAL CHARACTERISTICS (continued)
At VCC = 10 V to 36 V and TA = –40°C to +85°C. Typical values at VCC = 24 V, FB = 17 V, and TA = +25°C, unless otherwise
noted.
TLC5970
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
136
151
166
mA
0.1
µA
LED DRIVER BLOCK
IOLC
Constant output current
At OUT0 to OUT2 pins. OUTn are on,
DCn = BC = 7Fh,
VOUT = 1 V, RIREF = 1 kΩ
IOLKG
Leakage output current
At OUT0 to OUT2 pins. OUTn are off, DCn = 7Fh,
BC = 7Fh, VOUT = 17 V, RIREF = 1 kΩ
ΔIOLC
Constant-current error
(channel-to-channel) (1)
At OUT0 to OUT2 pins. OUTn are on,
DCn = BC = 7Fh,
VOUT = 1 V, RIREF = 1 kΩ
±0.5
±3
%
ΔIOLC1
Constant-current error
(device-to-device) (2)
At OUT0 to OUT2 pins. OUTn are on,
DCn = BC = 7Fh,
VOUT = 1 V, RIREF = 1 kΩ
±3
±6
%
ΔIOLC2
Line regulation (3)
OUT0 to OUT2 are on, DCn = BCn = 7Fh,
VOUT = 1 V, RIREF = 1 kΩ, VREG = 3.3 V to 5.5 V
±0.5
±2
%/V
ΔIOLC3
Load regulation (4)
OUT0 to OUT2 are on, DCn = BCn = 7Fh,
VOUT = 1 V to 3 V, RIREF = 1 kΩ
±1
±2
%/V
VIREF
Reference voltage output
IREF0 to IREF2, RIREF = 1 kΩ
1.20
1.23
(1)
1.17
V
The deviation of each output from the average of OUT0–OUT2 constant-current. Deviation is calculated by the formula:
IOUTn
D (%) =
-1
´ 100
(IOUT0 + IOUT1 + IOUT2)
3
(2)
The deviation of the OUT0–OUT2 constant-current average from the ideal constant-current value.
Deviation is calculated by the following formula:
(IOUT0 + IOUT1 + IOUT2)
3
D (%) =
- (Ideal Output Current)
´ 100
Ideal Output Current
Ideal current is calculated by the formula:
IOUT(IDEAL) = 125 ´
(3)
1.20
RIREF
Line regulation is calculated by this equation:
D (%/V) =
(IOUTn at VREG = 5.5 V) - (IOUTn at VREG = 3 V)
(IOUTn at VREG = 3.0 V)
(4)
5.5 V - 3 V
Load regulation is calculated by the equation:
D (%/V) =
(IOUTn at VOUTn = 3 V) - (IOUTn at VOUTn = 1 V)
100
´
(IOUTn at VOUTn = 1 V)
6
100
´
3V-1V
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SBVS140 – MARCH 2010
ELECTRICAL CHARACTERISTICS (continued)
At VCC = 10 V to 36 V and TA = –40°C to +85°C. Typical values at VCC = 24 V, FB = 17 V, and TA = +25°C, unless otherwise
noted.
TLC5970
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DIFFERENTIAL INTERFACE BLOCK
VITP
Positive-going input threshold
voltage
At SDTA-SDTB or SCKA-SCKB pins. Common-mode,
VIB = 1.5 V (see Figure 4)
VITN
Negative-going input threshold
voltage
At SDTA-SDTB or SCKA-SCKB pins. Common-mode,
VIB = 1.5 V (see Figure 4)
VITHYS
Hysteresis voltage (|VITP – VITN|)
Common-mode
0.2
–0.2
V
50
110
mV
II
At SDTA/SDTB/SCKA/SCKB pins. VIH = 12 V
(other inputs at 0 V), VCC = 24 V
2
3
mA
II1
At SDTA/SDTB/SCKA/SCKB pins. VIH = 12 V
(other inputs at 0 V), VCC = 0 V
2
3
mA
Input current
30
V
II2
At SDTA/SDTB/SCKA/SCKB pins. VIH = –7 V
(other inputs at 0 V), VCC = 24 V
–3
–1.2
mA
II3
At SDTA/SDTB/SCKA/SCKB pins. VIH = –7 V
(other inputs at 0 V), VCC = 0 V
–3
–1
mA
1.8
VOD
Differential output voltage
At SDTY-SDTZ or SCKY-SCKZ pins.
1/2 × RLDIF = 51 Ω (see Figure 6)
1
ΔVOD
Change in magnitude of differential
output voltage (5)
At SDTY-SDTZ or SCKY-SCKZ pins.
1/2 × RLDIF = 51 Ω (see Figure 6)
–0.2
VOC
Steady-state common-mode output
voltage
At SDTY-SDTZ or SCKY-SCKZ pins.
1/2 × RLDIF = 51 Ω (see Figure 6)
1.5
ΔVOC
Change in magnitude of steady-state
common-mode output voltage (5)
At SDTY-SDTZ or SCKY-SCKZ pins.
1/2 × RLDIF = 51 Ω (see Figure 6)
–0.2
RINT
Internal resistor between differential
input pair
At SDTA-SDTB or SCKA-SCKB pins.
A pins = 0 V, B pins = 1.8 V
IO
Output current with power off
At SDTY-SDTZ or SCKY-SCKZ pins. VCC = 0 V,
–7 V ≤ SDTY/SDTZ/SCKY/SCKZ ≤ 12 V, 1 pin sweep,
all other outputs are open
(5)
VREG/2
3
V
0.2
V
3
V
0.2
V
10
–10
±1
kΩ
20
µA
ΔVOD and ΔVOC are the changes in the steady-state magnitude of VOD and VOC, respectively, that occur when the output data change
from a high level to a low level.
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ELECTRICAL CHARACTERISTICS (continued)
At VCC = 10 V to 36 V and TA = –40°C to +85°C. Typical values at VCC = 24 V, FB = 17 V, and TA = +25°C, unless otherwise
noted.
TLC5970
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
At VREG pin. CREG = 0.01 µF, GSn = 000h
4.75
5.0
5.25
V
At VREGIF pin. CREG1 = 0.1 µF, RLDIF = 2 × 51 Ω
4.75
5.0
5.25
V
WHOLE BLOCK
VREG
VREG1
Internal power-supply voltage
VSTR
Undervoltage lockout
At VREG pin, VREG rising
3.8
4.1
4.4
V
VHYS
Undervoltage lockout hysteresis
At VREG pin
250
350
450
mV
ICC
At VCC pin. SDTA/SCKA = 0 V, SDTB/SCKB = 3 V,
SDTY/SDTZ/SCKY/SCKZ/PH/BOOT = open,
PH not switching, VOUTn = 1.0 V, GSn = 000h,
DCn = BC = 7Fh, RIREF = 15 kΩ,
internal oscillator mode, and auto repeat mode
4.0
7.5
mA
ICC1
At VCC pin. SDTA/SCKA = 0 V, SDTB/SCKB = 3 V,
SDTY/SDTZ/SCKY/SCKZ/PH/BOOT = open,
PH not switching, VOUTn = 1.0 V, GSn = 000h,
DCn = BC = 7Fh, RIREF = 2 kΩ,
internal oscillator mode, and auto repeat mode
7.5
10
mA
ICC2
At VCC pin. SDTA/SDTB = 10 MHz,
SCKA/SCKB = 20 MHz with 0 V to 3 V swing,
SDTY-SDTZ/SCKY-SCKZ = RLDIF = 10 kΩ,
CLDIF = 15 pF, PH/BOOT = open, PH is full switching,
VOUTn = 1.0 V, GSn = FFFh, DCn = BC = 7Fh,
RIREF = 2 kΩ, internal oscillator mode,
and auto repeat mode
8.5
25
mA
ICC3
At VCC pin. SDTA/SDTB = 10 MHz,
SCKA/SCKB = 20 MHz with 0 V to 3 V swing,
SDTY-SDTZ/SCKY-SCKZ = RLDIF = 2 × 51 Ω,
CLDIF = 50 pF, PH/BOOT = open, PH is full switching,
VOUTn = 1.0 V, GSn = FFFh,
DCn = BC = 7Fh, RIREF = 2 kΩ,
internal oscillator mode, and auto repeat mode
8.5
25
mA
ICC4
At VCC pin. SDTA/SDTB = 10 MHz,
SCKA/SCKB = 20 MHz with 0 V to 3 V swing,
SDTY-SDTZ/SCKY-SCKZ = RLDIF = 2 × 51 Ω,
CLDIF = 50 pF, PH/BOOT = open, PH is full switching,
VOUTn = 1.0 V, GSn = FFFh,
DCn = BC = 7Fh, RIREF = 1 kΩ,
internal oscillator mode, and auto repeat mode
15
35
mA
Supply current
II4
Input current
II5
At SWOFF pin. VIH = +5 V, VIL = GND
TTSD
Thermal shutdown trip point
Rising junction temperature (6)
THYST
Thermal shutdown hysteresis
Junction temperature (6)
TPTD
Pre thermal shutdown trip point
Rising junction temperature
THYSP
Pre thermal shutdown hysteresis
Junction temperature (6)
(6)
8
–2
1000
µA
5
10
mA
+150
+162
+175
°C
+5
+10
+20
°C
+125
+138
+150
°C
+4
+8
+16
°C
At VROM pin. VIH = +19.0 V
(6)
Not tested, specified by design.
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SBVS140 – MARCH 2010
SWITCHING CHARACTERISTICS
At VCC = 10 V to 36 V, TA = –40°C to +85°C, RIREF = 1 kΩ, and VLED = 5.0 V. Typical values at VCC = 24 V and TA = +25°C,
unless otherwise noted.
TLC5970
PARAMETER
tR0
Rise time
TEST CONDITIONS
TYP
At SDTY, SDTZ, SCKY, or SCKZ pins. RLDIF = 2 × 51 Ω,
CLDIF = 50 pF, SDTA-SDTB = SCKA-SCKB = 20 MHz,
measured at 0.4 V differential point
(see Figure 10 and Figure 11)
tR1
At OUTn pins. DCn/BC = 7Fh, RLLED = 27 Ω, CLLED = 15 pF
(see Figure 12)
tF0
At SDTY, SDTZ, SCKY, or SCKZ pins. RLDIF = 2 × 51 Ω,
CLDIF = 50 pF, SDTA-SDTB = SCKA-SCKB = 20 MHz,
measured at 0.4 V differential point
(see Figure 10 and Figure 11)
Fall time
MIN
MAX
UNIT
15
ns
15
ns
15
ns
10
35
ns
10
tF1
At OUTn pins. DCn/BC = 7Fh, RLLED = 27 Ω, CLLED = 15 pF
(see Figure 12)
tD0
(SCKA-SCKB)↑ – (SDTY-SDTZ) , RLDIF = 2 × 51 Ω,
CLDIF = 50 pF, DSI mode = 2 (see Figure 10)
20
30
60
ns
tD0A
(SCKA-SCKB)↑ – (SDTY-SDTZ) , RLDIF = 2 × 51 Ω,
CLDIF = 50 pF, DSI mode = 1 (see Figure 10)
30
50
90
ns
tD0B
(SCKA-SCKB) ↓ – (SDTY-SDTZ) , RLDIF = 2 × 51 Ω,
CLDIF = 50 pF, DSI mode = 0 (see Figure 11)
20
30
55
ns
tD1
(SCKA-SCKB)↑ – (SCKY-SCKZ)↑, RLDIF = 2 × 51 Ω,
CLDIF = 50 pF, DSI mode = 2 (see Figure 10)
13
19
33
ns
(SCKA-SCKB)↑ – (SCKY-SCKZ)↑, RLDIF = 2 × 51 Ω,
CLDIF = 50 pF, DSI mode = 1 (see Figure 10)
13
19
33
ns
tD1B
(SCKA-SCKB)↑↓ – (SCKY-SCKZ)↑↓, RLDIF = 2 × 51 Ω,
CLDIF = 50 pF, DSI mode = 0 (see Figure 11)
13
20
30
ns
tD2 (1)
(SCKY-SCKZ)↑ – (SDTY-SDTZ), RLDIF = 2 × 51 Ω,
CLDIF = 50 pF, DSI mode = 2
5
11
30
ns
tD2A (1)
(SCKY-SCKZ)↑ – (SDTY-SDTZ), RLDIF = 2 × 51 Ω,
CLDIF = 50 pF, DSI mode = 1
15
31
60
ns
tD3
(SCKA-SCKB) ↑ – OUT0 turns on/off (see Figure 12)
12
30
60
ns
tD4
(SCKA-SCKB) ↑ – OUT1 turns on/off (see Figure 12)
35
70
140
ns
tD5
(SCKA-SCKB) ↑ – OUT2 turns on/off (see Figure 12)
55
110
220
ns
tW
Shift clock output
one pulse width
(SCKY-SCKZ)↑ – (SCKY-SCKZ) ↓ with DSI mode 1 or mode 2
(see Figure 10)
12
25
35
ns
tW_ERR
Shift clock output
pulse width error
High-level pulse width of (SCKA-SCKB) – high-level pulse
width of (SCKY-SCKZ) with DSI mode 0 (see Figure 11)
10
ns
fOSC
Internal oscillator frequency
fSW
High-side MOS switching
maximum frequency
tD1A
Propagation delay time
tDTY0
tDTY1
tSCP
(1)
On-duty cycle
Short-circuit detection time
–10
8
10
12
MHz
1
1.25
1.5
MHz
At PH pin. EEPROM data = 7h
83
86
90
%
At PH pin. EEPROM data = 0h
15
18
21
%
2.4
4.0
µs
At PH pin
VFB < VSCP
The propagation delays are calculated by tD2 = tD0 – tD1, tD2A = tD0A – tD1A.
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FUNCTIONAL BLOCK DIAGRAM
VCC
VCC
FB
OVP/SCP
FB
VREG
BOOT
Voltage
Reference
Voltage Control
with Soft-Start,
Overvoltage Protection,
and Short-Circuit Protection
SWOFF
Switch
Timing
Control
FB
5-V
Regulator
PH
PH
High-Side
MOS SW
10-MHz
OSC
VREG
OUT 0
1/2
CLK
SEL
Display
Timing
Control
VREG
OUT 1
Constant-Current
Control
OUT 2
CLKSEL
UVLO
DSPRST
36
AUTORPT
Thermal
Detector
7
21
BC Data
LSB
VROM
IREF0
MSB
ROM Write
Control
LSB
7
IREF1
DC
Data
7-Bit Brightness
Control Second Latch
3
IREF2
GS
Data
MSB
12-Bit Function Control
Data Latch
8
EEPROM
(36-Bit)
29
0
LSB
13
DC
Loadcnt
11
MSB
VCC FB
21-Bit Dot Correction
Data Latch
TIMESEL
0
Latch
Pulse Gen
LSB
20
21
Select
Switch
MSB
36-Bit Grayscale
Second Data Latch
Address/Command
0
36
LSB
Differential
Line Receiver
0
SCKB
3
MSB
40-Bit Common Shift Register
SDTB
SCKA
Differential
Line Driver
35
LSB
Clock
Timing
Adjust
0
VREGIF
MSB
36-Bit Grayscale
First Data Latch
19
SDTA
5-V
Regulator
35
SDTY
SDTZ
39
SCKY
SCKZ
GND
10
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PIN CONFIGURATIONS
DAP PACKAGE
HTSSOP-32 PowerPAD
(TOP VIEW)
VCC
NC
PH
24
23
22
(1)
GND
26
NC
SWOFF
27
25
VREG
28
RHP PACKAGE
QFN-28
(TOP VIEW)
GND
1
32
VCC
SWOFF
2
31
NC
VREG
3
30
PH
VREGIF
4
29
BOOT
VREGIF
1
21
BOOT
(1)
5
28
NC
IREF2
2
20
FB
IREF2
6
27
FB
IREF1
3
19
OUT2
IREF1
7
26
NC
IREF0
4
18
OUT1
IREF0
8
25
OUT2
VROM
5
17
OUT0
NC
9
24
OUT1
SDTA
6
16
SDTY
VROM
10
23
OUT0
SDTB
7
15
SDTZ
NC
11
22
NC
SDTA
12
21
SDTY
SDTB
13
20
SDTZ
NC
14
19
NC
SCKA
15
18
SCKY
SCKB
16
17
SCKZ
8
9
10
11
12
13
14
SCKA
SCKB
NC
SCKZ
SCKY
NC
Thermal Pad
(Bottom Side)
Thermal Pad
(Bottom Side)
NC
NC
(1) NC = not connected
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TERMINAL FUNCTIONS
TERMINAL
NAME
DAP
RHP
I/O
SDTA
12
6
I
Noninverting serial data input
DESCRIPTION
SDTB
13
7
I
Inverting serial data input
SCKA
15
9
I
Noninverting data shift clock input. All data in the Common Shift Register are shifted to the
MSB side by 1 bit and synchronized to the rising edge of the differential clock generated by
SCKA and SCKB. The differential data made by SDTA and SDTB are shifted into the
Common Shift Register LSB at the same time.
SCKB
16
10
I
Inverting data shift clock input. All data in the shift register are shifted to the MSB side by 1 bit
synchronized to the rising edge of the differential clock generated by SCKA and SCKB. The
differential data made by SDTA and SDTB are shifted into the Common Shift Register LSB at
the same time.
SDTY
21
16
O
Noninverting serial data output
SDTZ
20
15
O
Inverting serial data output
SCKY
18
13
O
Noninverting serial data shift clock output
SCKZ
17
12
O
Inverting serial data shift clock output
SWOFF
2
27
I
Disable buck converter. When SWOFF is connected to VREG, the buck converter is not
operated and the OVP/SCP flag is not set even if the device is in an error condition. When
SWOFF is low, the buck converter is operated. This terminal is internally pulled down to GND
by approximately a 10 kΩ resistor.
VROM
10
5
IREF0
8
4
I/O
IREF1
7
3
I/O
EEPROM writing power supply. When this pin level is 19 V, EEPROM can be programmed for
dot correction data. This pin must be open in normal operation. This terminal is pulled down to
GND by approximately a 10 kΩ resistor internally.
The resistors connected from IREF0, IREF1, and IREF2 to GND set the maximum sink current
for OUT0, OUT1, and OUT2, respectively.
IREF2
6
2
I/O
OUT0
23
17
O
OUT1
24
18
O
OUT2
25
19
O
VREG
3
28
O
Internal regulator output. This pin requires a 0.01 µF decoupling capacitor to ground. This
output cannot be used for any other function and no current can be pulled from this output.
VREGIF
4
1
O
Internal regulator output for the differential interface circuit. This pin requires a 0.1 µF
decoupling capacitor. This output cannot be used for any other function and no current can be
pulled from this output.
FB
27
20
I
Feedback voltage input for the converter and power-supply for differential signal interface
output and LED driver. Connect this pin to the dc/dc converter output voltage. The FB pin
must not be opened, otherwise higher voltage than the absolute maximum voltage is
generated.
PH
30
22
O
Source of the high-side power MOSFET. Connected to an external inductor and diode.
BOOT
29
21
I/O
Boost capacitor for the high-side power MOSFET gate driver. A capacitor is connected
between BOOT and PH.
VCC
32
24
—
Power-supply voltage
GND
1
26
—
Power ground
5, 9, 11, 14,
8, 11, 14,
19, 22, 26,
23, 25
28, 31
NC
Thermal
pad
12
—
—
Constant-current sink output. Multiple outputs can be tied together to increase the
constant-current capability.
No internal connection. These pins are not electrically connected to the IC. They should be
soldered to the PCB. Connecting these pins to ground provides improved thermal
performance.
—
The DAP package thermal pad is electrically connected to ground inside the package. This
pad should be connected to the ground plane on the PCB for best thermal performance. It
does not need to be soldered to the PCB if thermal performance is not needed. This pad
cannot be connected to any other voltage other than ground. See the mechanical drawings at
the end of this document for more information.
The RHP package thermal pad is electrically connected to ground inside the package. This
pad must be connected to the ground plane on the PCB for best thermal performance and for
mechanical reasons. This pad cannot be connected to any other voltage other than ground.
See the mechanical drawings at the end of this document for more information.
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PARAMETRIC MEASUREMENT INFORMATION
PIN EQUIVALENT INPUT/OUTPUT SCHEMATICS
VREGIF
VREGIF
R2
R1
Input
R3
Output
R7
To
B Input
Figure 1. SDTA/SCKA
Figure 3. SDTY/SCKY, SDTZ/SCKZ
VREGIF
OUTn
R5
R4
Input
GND
Figure 4. OUT0 Through OUT2
R6
R7
To
A Input
Figure 2. SDTB/SCKB
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TEST CIRCUITS
VCC
VFB
FB
xA
VCC
High or Low
xB
VIA
GND
VIB
Figure 5. Receiver Test Circuit for SDTA/B and SCKA/B
VCC
FB
xY
VFB
1/2 RLDIF
VCC
VOD
High or Low
1/2 RLDIF
xZ
VOC
GND
Figure 6. Driver VOD and VOC Test Circuit for SDTY/Z and SCKY/Z
VCC
VFB
High or Low
FB
xY
xA
VCC
Output
RLDIF
CLDIF
(1)
xB
VIA
xZ
VIB
GND
(1) CLDIF includes probe and jig capacitance.
Figure 7. Rise/Fall Time and Propagation Delay Test Circuit for SDTY/Z and SCKY/Z
14
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VFB
VCC
VCC
OUTn
IREFn
RIREF
RLLED
VFB
VLED
CLLED
GND
Figure 8. Rise/Fall Time Test Circuit for OUTn
VFB
VCC
VCC
VFB
OUTn
IREFn
RIREF
OUTn
GND
VOUTn
VOUTfix
Figure 9. Constant-Current Test Circuit for OUTn
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TIMING DIAGRAMS
TSU, TH, tD0, tD0A, tD1, tD1A, tW, tR0, tF0
1V
SDTA
0V
1V
SDTB
0V
TSU
TH
1V
SCKA
0V
1V
SCKB
0V
tD0/tD0A
tD0/tD0A
SDTY
SDTZ
Output Voltage
Difference
(SDTY - SDTZ)
0.4 V
0V
-0.4 V
tR0
tD1/tD1A
tF0
SCKY
SCKZ
tW
Output Voltage
Difference
(SCKY - SCKZ)
0.4 V
0V
-0.4 V
tR0
tF0
Figure 10. Input/Output Timing 1 (DSI Mode = 1 or 2)
16
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TSU, TH, tD0B, tD1B, tR0, tF0
1V
SDTA
0V
1V
SDTB
0V
TSU
TH
1V
SCKA
0V
tW_SCKAB
1V
SCKB
0V
SDTY
tD0B
tD0B
SDTZ
Output Voltage
Difference
(SDTY - SDTZ)
0.4 V
0V
-0.4 V
tR0
tF0
tD1B
tD1B
SCKY
tW_SCKYZ
SCKZ
Output Voltage
Difference
(SCKY - SCKZ)
0.4 V
0V
-0.4 V
tR0
tF0
(1) tW_ERR = tW_SCKYZ – tW_SCKAB.
Figure 11. Input/Output Timing 2 (DSI Mode = 0)(1)
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tR1, tF1, tD3, tD4, tD5
1V
SCKA
0V
1V
SCKB
0V
tD3
(tD4, tD5)
tD3
(tD4, tD5)
5V
90%
OUT0
(OUT1, OUT2)
50%
10%
1V
tF1
tR1
Figure 12. Output Timing
18
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TYPICAL CHARACTERISTICS
Need conditions.
REFERENCE RESISTOR vs OUTPUT CURRENT
POWER DISSIPATION vs FREE-AIR TEMPERATURE
6000
Power Dissipation Rate (mW)
RIREF, Reference Resistor (kW)
100
15
10
7.5
2.5
3.75
1.5
1
0
TLC5970RHB
4000
3000
TLC5970DAP
PowerPAD Not Soldered
2000
1000
1.25 1.072
1
1.875
TLC5970DAP
PowerPAD Soldered
5000
0
10 20 30 40 50 60 70 80 90 100 110 120 130 140 150
-40
IO = 150 mA
TA = +25°C
VCC = +24 V
BC = 7Fh
140
140
Output Current (mA)
Output Current (mA)
IO = 120 mA
120
IO = 100 mA
100
IO = 80 mA
80
IO = 60 mA
40
TA = +25°C, VCC = +24 V
DC = 7Fh, BC = 7Fh
IO = 10 mA
IO = 150 mA
120
IO = 100 mA
100
IO = 60 mA
80
60
40
IO = 10 mA
20
20
0
0
0
1.5
1.0
0.5
2.0
2.5
3.0
0
Output Voltage (V)
160
120
16
32
48
64
96
80
112
128
Dot Correction Data (dec)
Figure 15.
Figure 16.
GLOBAL BRIGHTNESS LINEARITY
CONSTANT-CURRENT OUTPUT VOLTAGE WAVEFORM
TA = +25°C
VCC = +24 V
DC = 7Fh
140
Output Current (mA)
100
DOT CORRECTION LINEARITY
160
IO = 20 mA
80
Figure 14.
OUTPUT CURRENT vs OUTPUT VOLTAGE
60
60
40
Free-Air Temperature (°C)
Figure 13.
160
20
0
-20
IOLC, Output Current (mA)
CH1-SCKA
(20 MHz)
CH1 (2 V/div)
IO = 150 mA
CH2-OUT0
CH2 (2 V/div)
IO = 100 mA
100
IO = 60 mA
80
CH3 (2 V/div)
60
40
IO = 10 mA
CH4 (2 V/div)
20
IOLCMax = 150 mA
DCn = BC = 7Fh
GSn = 001h
External GS CLK
No Buck Conv Mode
SCKA/SCKB = 20MHz
CH3-OUT1
CH4-OUT2
0
0
16
32
48
64
80
96
112
128
Time (12.5 ns/div)
Brightness Control Data (dec)
Figure 17.
Figure 18.
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APPLICATION INFORMATION
MAXIMUM CONSTANT SINK CURRENT VALUE
The TLC5970 maximum constant sink current value for each channel, IOLCMax, is determined by an external
resistor, RIREF, placed between IREFn and GND. IREFn determines the maximum current of OUTn, where n
represents outputs 0, 1, or 2. The RIREF resistor value is calculated with Equation 1:
RIREF (kW) =
VIREF (V)
´ 125
IOLCMax (mA)
Where:
VIREF = the internal reference voltage on the IREF pin (1.20 V, typically).
(1)
IOLCMax is the largest current for each output. Each output sinks the IOLCMax current when it is turned on, the dot
correction is set to the maximum value of 7Fh (127d), and global brightness control data are 7Fh (127d). Each
output sink current can be reduced by lowering the output dot correction and brightness control values.
RIREF must be between 1 kΩ (typical) and 15 kΩ (typical) to keep IOLCMax between 10 mA and 150 mA. The
output may be unstable when IOLCMax is set lower than 10 mA. Output currents lower than 10 mA can be
achieved by setting IOLCMax to 10 mA or higher and then using dot correction and global brightness control. The
constant sink current versus external resistor, RIREF, characteristics are shown in Figure 13 and Table 1.
Table 1. Maximum Constant Current versus External Resistor Value
IOLCMax (mA)
RIREF (kΩ, Typical)
150
1.00
140
1.07
120
1.25
100
1.50
80
1.88
60
2.50
40
3.75
20
7.50
10
15.0
DOT CORRECTION (DC) AND GLOBAL BRIGHTNESS CONTROL (BC) FUNCTION (CURRENT
CONTROL)
The TLC5970 has the capability to adjust the output current of each channel (OUT0 to OUT2) individually. This
function is called dot correction (DC). The DC data are seven bits long, which allows each channel output current
to be adjusted in 128 steps from 0% to 100% of the maximum output current, IOLCMax. The DC data are entered
into the TLC5970 via the serial interface and can be stored into the internal EEPROM. When the IC is powered
on, DC data are automatically loaded into the DC data latch from the EEPROM.
The TLC5970 also has the capability to adjust all output currents at the same time. This function is called global
brightness control (BC). The BC data are seven bits long, which allows all three output channel currents to be
adjusted in 128 steps from 0% to 100% of the maximum output current, IOLCMax. The BC data are entered into the
TLC5970 via the serial interface. The brightness control data cannot be stored into EEPROM. When IC is
powered on, BC data are automatically set to 7Fh (127d).
20
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Equation 2 determines each output (OUTn) sink current:
DCn
IOUTn (mA) = IOLCMax (mA) ´
127d
´
BC
127d
Where:
IOLCMax = the maximum channel current for each channel determined by RIREFn
DCn = the decimal dot correction value for each OUTn in the DC latch (DCn = 0d to 127d)
BC = the decimal brightness control value in the brightness control latch (BC = 0d to 127d)
(2)
DC, BC, and function current control data are shown in Table 2, Table 3, and Table 4, respectively.
Table 2. DC Data versus Current Ratio and Set Current Value
SET CURRENT
RATIO TO
MAXIMUM
CURRENT (%)
DC DATA
(Binary)
DC DATA
(Decimal)
DC DATA
(Hex)
BC DATA
(Hex)
150 mA IOLCMax
(mA, Typical)
10 mA IOLCMax
(mA, Typical)
000 0000
0
00
7F
0
0
0
000 0001
1
01
7F
0.8
1.18
0.08
000 0010
2
02
7F
1.6
2.36
0.16
—
—
—
—
—
—
—
111 1101
125
7D
7F
98.4
147.64
9.84
111 1110
126
7E
7F
99.2
148.82
9.92
111 1111
127
7F
7F
100.0
150.00
10.00
Table 3. BC Data versus Current Ratio and Set Current Value
SET CURRENT
RATIO TO
MAXIMUM
CURRENT (%)
BC DATA
(Binary)
BC DATA
(Decimal)
BC DATA
(Hex)
DC DATA
(Hex)
150 mA IOLCMax
(mA, Typical)
10 mA IOLCMax
(mA, Typical)
000 0000
0
00
7F
0
0
0
000 0001
1
01
7F
0.8
1.18
0.08
000 0010
2
02
7F
1.6
2.36
0.16
—
—
—
—
—
—
—
111 1101
125
7D
7F
98.4
147.64
9.84
111 1110
126
7E
7F
99.2
148.82
9.92
111 1111
127
7F
7F
100.0
150.00
10.00
Table 4. DC and BC Data versus Current Ratio and Set Current Value
BC DATA
(Hex)
DC DATA
(Hex)
SET CURRENT RATIO
TO MAXIMUM CURRENT
(%)
00
00
01
01
02
—
150 mA IOLCMax
(mA, Typical)
10 mA IOLCMax
(mA, Typical)
0
0
0
0
0.01
0
02
0.01
0.04
0
—
—
—
—
7D
7D
96.88
145.31
9.69
7E
7E
98.43
147.65
9.84
7F
7F
100.0
150.00
10.00
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GRAYSCALE (GS) FUNCTION (PWM CONTROL)
The OUTn PWM control is controlled by a 12-bit grayscale counter that is clocked on each rising edge of either
the internal oscillator or the shift clock signal generated by the differential signal, SCKA and SCKB. When bit 9 in
the Function Control Data Latch is '0', the internal oscillator drives the PWM grayscale counter. When bit 9 is '1',
SCKA and SCKB drive the grayscale counter. The OUTn that are programmed with a non-zero grayscale value
(GSn) turn on at the first rising edge of the selected clock after the internal latch pulse generation. After the
internal latch latch pulse goes high, the 12-bit grayscale counter counts the clock rising edges. Each OUTn stays
on until the grayscale counter value is larger than the output GSn value. OUTn turns off on the rising edge of the
clock.
When the IC powers up, all data in the Grayscale Data Latch are set to '0'. Therefore, GSn data must be written
into the Grayscale Data Latch to turn on OUTn. Equation 3 determines each OUTn on-time (tOUT_ON):
tOUT_ON (ns) = tGSCLK (ns) ´ GSn
Where:
tGSCLK = Twice the period of the internal oscillator frequency if the internal clock is selected. One period of
the shift clock frequency is generated by the differential signal if the external clock is selected.
GSn = the programmed grayscale value for OUTn (GSn = 0d to 4095d)
(3)
AUTO DISPLAY REPEAT
Auto display repeat, DSPRPT, allows OUTn to continuously turn on for multiple PWM cycles without the need to
continuously reprogram the PWM grayscale registers. When Auto Repeat is enabled, bit 8 in the Function
Control Data Latch is '1' and OUTn automatically turns on again at the next rising clock of the internal oscillator.
When Auto Display Repeat is disabled by setting the control bit to '0', OUTn do not turn on again until an internal
latch pulse is generated and another GS clock pulse goes high. This timing is shown in Figure 19 and Figure 20.
Table 5. GS Data versus OUTn On-Duty and OUTn On-Time
22
OUTn ON-DUTY RATIO
AGAINST MAXIMUM CODE (%)
OUTn ON-TIME WHEN 5 MHz
INTERNAL OSCILLATOR IS
SELECTED FOR GS CLOCK
(µs, Typical)
GS DATA
(Binary)
GS DATA
(Decimal)
GS DATA
(Hex)
0000 0000 0000
0
000
0
0
0000 0000 0001
1
001
0.02
0.20
0000 0000 0010
2
002
0.05
0.40
—
—
—
—
—
0111 1111 1111
2047
7FF
49.99
409.4
1000 0000 0000
2048
800
50.01
409.6
1000 0000 0001
2049
801
50.04
409.8
—
—
—
—
—
1111 1111 1101
4093
FFD
99.95
818.6
1111 1111 1110
4094
FFE
99.98
818.8
1111 1111 1111
4095
FFF
100.00
819.0
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SDTA
SDTB
SCKA
SCKB
Generated Shift Data
(Internal)
Generated Shift Data
(Internal)
Shift Register Bit 0
(Internal)
Shift Register Bit 1
(Internal)
Shift Register Bit 2
(Internal)
D39
D38
1
D39
D37
2
D36
3
D35
4
D6
5
D5
34
D3
D4
35
36
D2
37
D0
D1
38
39
40
D36
D35
D6
D5
D4
D3
D2
D1
D0
D39
D38
D37
D36
D7
D6
D5
D4
D3
D2
D1
D39
D38
D37
D8
D7
D6
D5
D4
D3
D2
D39
D38
Shift Register Bit 38
(Internal)
Shift Register Bit 39
(Internal)
¼
¼
D37
¼
¼
D38
D39
SDTY
SDTZ
SCKY
Latch pulse is generated with
the programmed internal latch
delay time from last rising edge
of the shift clock.
SCKZ
Latch Pulse
(Internal)
Addressed Latch Bit 0
(Internal)
D0
Addressed Latch Bit 1
(Internal)
D1
Addressed Latch Bit 2
(Internal)
D2
¼
¼
¼
¼
Addressed Latch Bit 34
(Internal)
D34
Addressed Latch Bit 35
(Internal)
D35
Figure 19. Serial Data Input/Output Timing Diagram 1
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SDTA
SDTB
SCKA
SCKB
Generated Shift Data
(Internal)
D39A D38A D37A D36A D35A
1
2
3
4
5
D6A
D5A
34
D4A
D3A
D2A
D1A
D0A
36
37
38
39
40
35
Generated Shift Data
(Internal)
Shift Register Bit 1
(Internal)
Shift Register Bit 2
(Internal)
D39A D38A D37A D36A D35A
D6A
D5A
D4A
D3A
D2A
D1A
D0A
RD1
RD0
D39A D38A D37A D36A
D7A
D6A
D5A
D4A
D3A
D2A
D1A
D2
RD2
RD1
RD0
D39A D38A D37A
D8A
D7A
D6A
D5A
D4A
D3A
D2A
RDn are the SID or
EEPROM read data.
RD4
RD3
RD2
RD1
RD0
D39A
D38A
RD5
RD4
RD3
RD2
RD1
RD0
D39A
D0
D1
D38
D37
D36
Shift Register Bit 39
(Internal)
D39
D38
D37
¼
Shift Register Bit 38
(Internal)
¼
¼
RD0
¼
Shift Register Bit 0
(Internal)
RD35 RD34 RD33
D36
RD35 RD34
SDTY
D39+
D38+ D37+ D36+
D35+
RD5+ RD4+ RD3+ RD2+ RD1+ RD0+ D39A+
SDTZ
D39-
D38-
D35-
RD5- RD4- RD3- RD2- RD1- RD0- D39A-
D37- D36-
SCKY
SCKZ
Latch Pulse
(Internal)
Addressed Latch Bit 0
(Internal)
D0
Addressed Latch Bit 1
(Internal)
D1
Addressed Latch Bit 2
(Internal)
D2
D34
Addressed Latch Bit 35
(Internal)
D35
¼
¼
¼
¼
Addressed Latch Bit 34
(Internal)
Figure 20. Serial Data Input/Output Timing Diagram 2 (SID/EEPROM Data Read)
24
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DIFFERENTIAL SIGNAL INTERFACE
This device has a differential signal receiver and differential signal driver. These differential components provide
very reliable, high-quality signal integrity over long distances. This integrity allows very large distances between
the display pixels without the need for additional drive circuitry. The drivers are enabled one second after the IC
powers up. A 10-kΩ resistor is internally mounted between SDTA and SDTB/SCKA and SCKB. Table 6 shows a
truth table of the differential signal interface receiver and driver.
Table 6. Differential Signal Interface Truth Table
RECEIVER (SDTA-SDTB, SCKA-SCKB)
DRIVER (SDTY-SDTZ, SCKY-SCKZ)
DIFFERENTIAL OUTPUTS
DIFFERENTIAL INPUTS
(VID = SDTA/SCKA – SDTB/SCKB)
INTERNAL INPUT DATA
VID ≥ 0.2 V
High
–0.2 V < VID < 0.2 V
Undefined
VID ≤ –0.2 V
Low
Open input
Low
DRIVER INPUT
SDTY/SCKY
SDTZ/SCKZ
Low
Low
High
High
High
Low
BUCK DC/DC CONVERTER
The buck converter operates with the Pulse Frequency Mode (PFM).The buck converter controls the LED anode
voltage to keep the LED cathode voltage to approximately 1 V for high efficiency and reduces the system
power-supply current. The LED anode voltage is controlled by the buck converter in this manner:
1. After the IC powers on, the LED anode voltage charges up to the FB voltage set by EEPROM with a
soft-start squence. The maximum time of the soft-start sequence is 800 ms.
2. The LED then turns on and comparators check the OUTn voltage when all LED are turned on at the 32nd
GSCLK. If the lowest voltage in OUT0 to OUT2 is below 0.9 V when all OUTn are on at 32nd GSCLK, the
buck converter target voltage is changed by one step to a higher voltage at the rising edge of the 33rd
GSCLK. If the lowest voltage in OUT0 to OUT2 is above 1.1 V, the buck converter target voltage changes by
one step to a lower voltage. If the lowest voltage in OUT0 to OUT2 is between 0.9 V and 1.1 V, then the
buck converter target voltage remains at the previous voltage.
3. If the highest voltage in OUT0 to OUT2 exceeds 4.0 V at the 32nd GSCLK rising edge when all OUTn are
on, then the buck converter target voltage does not change to a higher voltage side.
Parameter Selection for Buck Converter
The following steps select the parameters for the buck converter.
1. PH on-time selection:
VFB Minimum Voltage
Calculated PH On-Duty Ratio1 (%) =
´ 100
VCC Maximum Input Voltage
Where:
VFB = the number of LEDs in series × LED minimum forward voltage (VF) + 1.0 V
(4)
Select the closest and smaller number in Table12, then calculate PH on-duty ratio1 (%).
Example: VCC = 24 V (typical) and 25 V (maximum). LED forward voltage (VF) = 3.2 V (minimum) and 3.5 V
(typical). Two LEDs are connected in series.
Thus, VFB = 2 × 3.2 + 1 = 7.4 V. The PH on-duty ratio1 (%) = 7.4/25 = 29.6%. Therefore, 29% code ('1h')
should be selected for PH on-duty.
So, the selected PH on-duty in the EEPROM write data latch is 29%.
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2. Inductor value and current selection:
VFB Maximum Voltage
PH On-Duty Ratio2 (%) =
´ 100
VCC Minimum Input Voltage
(5)
Example: VCC = 23 V (minimum), 24 V (typical), and 25 V (maximum). LED forward voltage (VF) = 3.2 V
(minimum), 3.5 V (typical), and 3.8 V (maximum). Two LEDs are connected in series.
Thus, VFB = 2 × 3.8 + 1 = 8.6 V. The PH on-duty ratio 2 (%) = 8.6/23 = 37.4% in this case.
Calculate inductor peak current (mA):
IOUT + IFBn
Selected PH On-Duty
Inductor Peak Current (mA) =
´2
PH On-Duty Ratio2
h
100
Where:
IOUT (mA) = Total current of LEDs connected to OUT0/1/2.
IFBn (mA) = Maximum input current of IFB pin.
h (%) = Efficiency of TLC5970 buck converter (recommended to use 90).
(6)
Example: In case all LED currents are set to 60 mA by the 2.50-kΩ external resistor and total current is 180
mA. IFB3 in this data sheet is used when the differential interface output drives the next TLC5970 without a
resistor between SDTA/SDTB and SCKA/SCKB. Therefore:
180 + 115
´2
29
37.4
ILPK (mA) =
= 845.5 mA
90
100
(7)
A 25% margin for inductor variation is required. Thus, ILPK = 845.5 × 1.25 = 1057 mA. The maximum inductor
current should be larger than 1057 mA. However, the TLC5970 PH peak current must be less than 2 A in
any case.
3. Calculate inductor value (µH) for minimum inductor value:
1
Inductor Value (mH) = VCC Voltage (V, Minimum) ´
Maximum PH Switching Frequency (MHz, Maximum)
(8)
Selected PH On-Duty (%)
ILPH (mA) ´ 1000
(9)
Example: VCC = 23 V (minimum), 24 V (typical), and 25 V (maximum). Maximum PH switching frequency is
1.5 MHz. The selected PH on-duty ratio as calculated by Equation 4 is 29%. ILPK (mA) is 1057 mA as
calculated by Equation 6.
0.29
Therefore, the inductor value (mH) = 23 ´ 1 ´
1.5 1057 ´ 1000
0.29
= 23 ´ 0.67 ´
1057 ´ 1000
= 4.2 mH
(10)
26
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4. Calculate inductor peak current that should be selected:
The TLC5970 PH peak current must be less than 2 A and ILPK must not be greater than 2 A in any case.
1
Inductor Peak Current (A) = VCC (V, Maximum) ´
Maximum PH Switching Frequency (MHz, Maximum)
Selected PH On-Duty
Inductor Value (mH)
<2A
(11)
Example: In this case, 25 × 0.67 × 0.29/4.2 = 1.15 A. So the inductor value is correct.
As the result of the above calculation, the inductor value should be selected over 4.2 µH and the inductor
peak current should be over 1.15 A.
Figure 21 shows a block diagram of the buck dc/dc converter; Figure 22 details the buck dc/dc converter
operation. Figure 23 and Figure 24 illustrate the timings of the external and internal GS clock mode for PWM
operation, respectively.
VCC
Boot Regulator
BOOT
OSC
(10 MHz)
C2
Buck Converter
Switching Control
with Soft-Start
VREF
L1
PH
PH High-Side
MOS SW
C1
D1
SCP/TSD
FB
UVLO
ERR_VO
OR
LEDBn
RRED
DAC
LEDGn
4.0 V
HI_VO
LEDRn
AND
EEPROM
LEDB1
1.1 V
LOW_VO
Buck Converter
Target Voltage
Control
LEDR1
0.9 V
5 MHz
1/2
Divider
External Clock
From Differential
Signal Interface Pin,
SCKA and SCKB
Clock
Select
LED
On-Off
Timing
Control
LEDG1
OR
ConstantCurrent
Control
OUT0
OUT1
OUT2
IREF0
Control Data From
Logic Circuit Block
RIREF0
IREF1
RIREF1
IREF2
RIREF2
GND
Figure 21. Buck DC/DC Converter Operation
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LED Is Off
LED Is On
LED Is Off
FB target voltage set by the DAC.
FB
Voltage
5. The FB voltage increases because the
current is charged from L1 into C1.
The FB voltage falling slope becomes sharp
when the LED lamp is turned on.
ON
MOS
Switcher
The FB voltage falling slope
becomes mild when the LED
lamp is turned off.
1. When the FB voltage falls below the FB target voltage
set by the DAC, the MOS switcher is turned on to
synchronize the internal oscillator with the EEPROM-programmed on-time.
OFF
2. The PH voltage goes to a VCC level when the MOS swicher
is turned on and then charges the current to L1.
6. When the L1 current becomes zero, the resonance starts.
VCC
FB
PH
GND
D1 Forward Voltage
4. PH voltage drops with the D1 forward voltage from GND.
3. When the MOS switcher is turned off, the current
in the inductor is discharged to the capacitor connected to FB.
L1
Current
0 mA
Figure 22. Buck DC/DC Converter Block Diagram
28
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SDTA
SDTB
SCKA
SCKB
The latch pulse is generated after
the programmed time from the
last serial clock rising edge.
Pre-Boost Period
1
2
17
18
1040
1041
4111
4112
1
2
Generated Shift Clock
(Internal)
Generated Shift Register Data
(Internal)
The GS first and second latches are updated at the same time when the latch pulse
is generated with the display timing reset mode enabled.
Generated Latch Pulse
(Internal)
GS First Latch Data
(Internal)
GS Second Latch Data
(Internal)
1/2 Divided Internal Oscillator Clock
(Internal)
Grayscale Counter
(Internal)
XXX
FF0
FF1
001
400
002
401
FFE
FFF
000
001
002
1
Function Control Bit 13
(External GS clock)
0
1
Function Control Bit 14
(Display Timing Reset)
0
GS counter is set to FF0h when the latch pulse is generated for
GS data when the display timing reset bit is '1'.
OFF
OUTn
(GSDATA = 000h)
ON
No drivers turn on when
grayscale data are '0'.
T = Shift Clock ´ 1
OFF
OUTn
(GSDATA = 001h)
OUTn is not turned on again until the next latch pulse is input for
auto repeat off mode (AutoRpt bit of the function control latch = 0).
ON
OUTn is turned on again for auto repeat on mode
(AutoRpt bit of the function control latch = 1).
OFF
OUTn
(GSDATA = 3FFh)
OFF
¼
ON
¼
¼
OUTn
(GSDATA = 002h)
T = Shift Clock ´ 1023
ON
T = Shift Clock ´ 1024
OFF
OUTn
(GSDATA = 400h)
ON
OFF
OUTn
(GSDATA = FFEh)
OFF
ON
OFF
OUTn
(GSDATA = FFFh)
T = Shift Clock ´ 4094
¼
ON
¼
¼
OUTn
(GSDATA = 401h)
T = Shift Clock ´ 4095
ON
Figure 23. PWM Operation (External GS Clock Mode)
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SDTA
SDTB
SCKA
SCKB
The latch pulse is generated after the programmed time
from the last shift clock rising edge.
1
2
3
Generated Shift Clock
(Internal)
Generated Shift Register
(Internal)
The GS first latch data are copied to the second latch at the 4096th rising edge of
the reference clock when auto-repeat mode is on and while in no GS counter reset mode.
Generated Latch Pulse
(Internal)
GS First Latch
(Internal)
GS Second Latch
(Internal)
4096
1
2
1022 1023 1024 1025 1026 1027 4095 4096
1
2
3
4094 4095 4096
1
2
3
4
1/2 Divided Internal Oscillator Clock
(Internal)
Grayscale Counter
(Internal)
FFF
000 001
3FE 3FF 400 401 402
FFF 000 001 002
FFE FFF 000 001 001 002
1
Function Control Bit 13
(External Grayscale Clock)
0
1
Function Control Bit 14
(Display Timing Reset)
0
No drivers turn on when the grayscale data are '0'.
OUTn OFF
(GSDATA = 000h) ON
OUTn is not turned on again until the next latch pulse input when
auto repeat is off (AutoRpt bit of the function control latch = 0).
T = Internal OSC Clock ´ 1
OFF
OUTn
(GSDATA = 001h)
ON
OUTn
(GSDATA = 002h)
¼
OUTn
(GSDATA = 3FFh)
ON
T = Internal OSC Clock ´ 1023
OFF
ON
OFF
OUTn
(GSDATA = 400h)
¼
OUTn
(GSDATA = FFEh)
T = Internal OSC Clock ´ 1024
ON
OFF
OUTn
(GSDATA = 401h)
OUTn is not turned on again for auto repeat on mode
(AutoRpt bit of the function control latch = 1)
T = Internal OSC Clock ´ 2
OFF
T = Internal OSC Clock ´ 1025
ON
T = Internal OSC Clock ´ 4094
OFF
ON
T = Internal OSC Clock ´ 4095
OFF
OUTn
(GSDATA = FFFh)
ON
Figure 24. PWM Operation (Internal GS Clock Mode)
30
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REGISTER AND DATA LATCH CONFIGURATION
The TLC5970 has five writable data latches, two readable registers, and one error release address. All data
written into or read from these registers and data latches go through the differential signal interfaces and the
40-bit Common Shift Register. The first four most significant bits (MSBs) in the 40-bit Common Shift Register are
used to define which internal latch the data are transferred into. Data in the 40-bit Common Shift Register are
automatically transferred into an internal latch or data from the internal latch are automatically transferred into the
40-bit Common Shift Register when the TLC5970 generates the internal latch signal. Figure 25 shows the shift
register and data latch configurations. Table 7 lists the assignment of latch addresses.
Table 7. Register/Data Latch Address Assignment
ADDRESS (4-Bit)
BINARY
DECIMAL
HEX
READ/WRITE
SELCTED DATA LATCH/FUNCTION
0000
0
0
W
Grayscale (GS) data latch. These data control LED
brightness by PWM.
0001-1000
1-8
1-8
—
No assigned latch. Data are not transferred when these
addresses are selected.
1001
9
9
W
Restart operation.
If the TLC5970 is disabled because of overvoltage
protection (OVP) or short-circuit protection (SCP), writing
any value to the Restart Operation latch enables the
TLC5970. Writing to this latch has no effect if the TLC5970
is operating normally. The system should diagnose and
correct any problems that have caused OVP or SCP before
writing to this latch to restart the IC.
1010
10
A
R
Status Information Data (SID) Register. Writing any value
to this register causes the SID data to be loaded into the
40-bit Common Shift Register.
1011
11
B
R
EEPROM Data Read Register. Writing any value to this
register causes the EEPROM data to be loaded into the
40-bit Common Shift Register.
1100
12
C
W
EEPROM1 Write Data Latch (write command = A5h).
The data in this latch program the PH on-duty, VFB target
voltage, differential interface timing mode. and Internal latch
pulse delay time. In order to properly program the
EEPROM with this data, bits 35-28 must contain A5h
(1010101b).
1101
13
D
W
EEPROM Write Data Latch 2 (write commend = 5Ah).
The data in this latch program the default Dot Correction. In
order to properly program the EEPROM with this data, bits
35-28 must contain 5Ah (0101010b).
1110
14
E
W
Dot Correction (DC) Data Latch.
The data in this latch contain OUTn DC data. When the IC
is powered up, the data stored in EEPROM2 are
automatically written to this latch.
1111
15
F
W
Function Control (FC) and Brightness Control (BC) Data
Latch.
These data control several IC functions. This latch also
contains the Brightness Control data.
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40-Bit Common Shift Register (Default = 0h)
35
34
Latch Address Bits (4 Bits)
MSB
39
Shift out data to the
differential line driver.
SOUT
38
37
33
2
0
1
Latch Data (36 Bits)
36
Latch
Latch
Latch
Latch
Address Address Address Address
Bit 3
Bit 2
Bit 0
Bit 1
35
34
33
Latch
Data
Bit 35
Latch
Data
Bit 34
Latch
Data
Bit 33
35
34
33
¼
2
1
LSB
0
Latch
Data
Bit 2
Latch
Data
Bit 1
Latch
Data
Bit 0
2
1
0
SIN
Shift in data from the
differential signal receiver.
SCLK
Shift clock from the
differential signal receiver.
Latch pulse from the
pulse generator
(the latch pulse is generated
after the programmed time
set by the data in the function
control data latch from the
last shift clock when the
auto refresh bit is ‘1’).
4
Latch Address
4-Bit Decoder
Address = 0000b
MSB
35
34
33
OUT2
GS
Bit 11
OUT2
GS
Bit 10
OUT2
GS
Bit 9
¼
2
1
LSB
0
OUT0
GS
Bit 2
OUT0
GS
Bit 1
OUT0
GS
Bit 0
Grayscale First Data Latch (Default = 0)
Address = 1001b
Restart Operation
From OVP/SCP Error
MSB
35
34
33
OUT2
GS
Bit 11
OUT2
GS
Bit 10
OUT2
GS
Bit 9
¼
2
1
LSB
0
OUT0
GS
Bit 2
OUT0
GS
Bit 1
OUT0
GS
Bit 0
36
Grayscale Second Data Latch (Default = 0)
MSB
35
Address = 1010b
34
33
2
TI
TI
TI
Reserved Reserved Reserved
Bit 28
Bit 29
Bit 30
¼
LSB
0
1
ShortOver
LED
Circuit
Voltage
Open
Protection Protection Detection
Status Information Data (SID) Read Out Register
35
34
33
2
1
35
34
33
2
1
MSB
35
Address = 1011b
TI
Reserved
Bit 0
34
33
Latch
Delay
Time
Bit 3
Latch
Delay
Time
Bit 2
¼
0
0
2
1
LSB
0
OUT0
DC
Bit 2
OUT0
DC
Bit 1
OUT0
DC
Bit 0
EEPROM Data Read Out Register
35
34
33
2
1
35
34
33
2
1
36
MSB
35
Address = 1100b
34
33
2
Write
Write
Write
Command Command Command
Bit 5
Bit 6
Bit 7
¼
0
0
LSB
0
1
PH
PH
PH
On-Duty On-Duty On-Duty
Bit 2
Bit 0
Bit 1
36
EEPROM1 Write Data Latch
36-Bit
EEPROM
35
14
35
36
MSB
35
21
Address = 1101b
34
34
33
2
Write
Write
Write
Command Command Command
Bit 7
Bit 5
Bit 6
¼
0
1
2
1
LSB
0
OUT2
DC
Bit 2
OUT2
DC
Bit 1
OUT2
DC
Bit 0
33
Lower 20
EEPROM2 Write Data Latch
Lower 31
20
Address = 1110b
19
MSB
20
19
OUT2
DC
Bit 6
OUT2
DC
Bit 5
2
¼
0
1
2
1
LSB
0
OUT0
DC
Bit 2
OUT0
DC
Bit 1
OUT0
DC
Bit 0
Lower 12
Dot Correction Data Latch (Default = Data in EEPROM2)
6
11
MSB
11
DC Data
Load
Control
Address = 1111b
0
LSB
0
6
¼
Brightness
Bit 6
¼
Brightness
Bit 0
Function Control Data Latch
(Default = 007Fh)
Latch pulse from the display timing control block.
(This latch pulse is generated at the end of one display
period or the timing of the display timing reset when the
auto refresh bit is ‘1’. Also, when the auto refresh
bit is ‘0’, the latch pulse is generated when the grayscale
or global brightness control data are written.
MSB
6
Brightness
Bit 6
8
4
LSB
0
¼
Brightness
Bit 0
Global Brightness Control
Second Data Latch
(Default = 7Fh)
2
To Buck To Latch Pulse To Differential
Converter
Signal Interface
Generator
Block
Block
Block
Figure 25. Register and Data Latch Configuration
32
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Grayscale (GS) First/Second Data Latch (Register Address = 0000b)
The GS Latch is 36 bits long. The second GS Latch controls the pulse width modulation (PWM) for each OUTn.
The first GS Latch holds the data written through the differential signal interface. If the Auto Data Refresh bit in
the Function Control Latch is '1', the data in the first latch are copied to the second latch at the rising edge of the
4096th grayscale clock. If the Auto Data Refresh bit is '0', both the first and second GS Latches are updated at
the same time from the data written into the differential signal interface. When the IC is powered on, both latches
are reset to all '0'. At startup, GS data should not be programmed until after the Function Control Data Latch is
programmed because the PWM control automatically starts when data are written into the second GS Latch.
Table 8 and Figure 26 show the GS Data Latch bit assignments. Table 5 shows an example of OUTn duty cycle
ratios for different GS data.
Table 8. Grayscale Data Latch Bit Assignment
BIT NUMBER
BIT NAME
DESCRIPTION
11-0
GSOUT0
Grayscale data for OUT0 (data = 000h to FFFh, default = 000h = LED off)
23-12
GSOUT1
Grayscale data for OUT1 (data = 000h to FFFh, default = 000h = LED off)
35-24
GSOUT2
Grayscale data for OUT2 (data = 000h to FFFh, default = 000h = LED off)
Grayscale First Data Latch
MSB
35
OUT2
OUT2
GS Data GS Data
Bit 10
Bit 11
MSB
35
25
34
¼
25
¼
23
22
OUT2
OUT2
OUT1
OUT1
GS Data GS Data GS Data GS Data
Bit 1
Bit 0
Bit 11
Bit 10
34
OUT2
OUT2
GS Data GS Data
Bit 11
Bit 10
24
24
23
13
¼
13
¼
11
10
OUT1
OUT1
OUT0
OUT0
GS Data GS Data GS Data GS Data
Bit 1
Bit 0
Bit 11
Bit 10
22
OUT1
OUT1
OUT2
OUT2
GS Data GS Data GS Data GS Data
Bit 10
Bit 11
Bit 0
Bit 1
12
12
11
1
¼
10
OUT0
OUT0
OUT1
OUT1
GS Data GS Data GS Data GS Data
Bit 10
Bit 11
Bit 0
Bit 1
OUT0
OUT0
GS Data GS Data
Bit 1
Bit 0
1
¼
LSB
0
LSB
0
OUT0
OUT0
GS Data GS Data
Bit 0
Bit 1
Grayscale Second Data Latch
36
To Display Timing Control Block
Figure 26. GS Data Latch Bit Assignment
Function Control (FC) and Global Brightness Control (BC) First/Second Data Latch
(Register Address = 1111b)
The FC and BC first Data Latch total bit length is 15 bits. The BC second latch bit length is seven bits. The FC
data are used to set the function mode; the BC second data latch sets the current ratio of each constant-current
output. The BC first latch holds the data written through the differential signal interface, and the latched data in
the first latch are copied to the second latch at the rising edge of the 4096th GS clock when the auto data refresh
bit is set to '1' in the FC latch. The first and second latch data are updated at the same time by the data written
through the differential signal interface when the auto data refresh bit is set to '0'. When the IC is powered on,
the FC data should be set before the GS data setting because the PWM control starts as soon as the GS data
(except '0') are written into this second latch.
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The data bit assignments are shown in Table 9 and Figure 27. OUTn set the current ratio in select BC data; see
Table 3.
Table 9. Global Brightness Control and Function Control Data Latch Bit Assignment
BIT NUMBER
BIT NAME
6-0
BCDATA
Global brightness control (BC) data for all outputs (default = 7Fh)
DATRFH
Auto data refresh (default = 0)
0 = Disabled; the GS and BC first and second data latches are
simultaneously updated by the internal data latch pulse.
1 = Enabled; the GS and BC second data latches are updated with
the data in the first latch at the 4096th rising edge of the grayscale
clock or the display timing reset timing.
DSPRPT
Auto display repeat (default = 0)
0 = Disabled; all OUTn on/off controls are not repeated. The output
is turned on and off one time only after the GS clock counter is reset.
1 = Enabled; all OUTn on/off controls are repeated according to the
4096th GS clock after the GS clock counter is reset.
EXTCLK
External grayscale clock select (default = 0)
0 = Internal clock is selected; each OUTn on/off control timing is
synchronized with the internal clock.
1 = External clock is selected; each OUTn on/off timing control is
synchronized with the shift clock generated by the differential signal
with the SCKA and SCKB input pin.
TMGRST
Display timing reset (default = 0)
0 = Disabled; the GS clock counter is not reset and all OUTn are not
forced off when the internal latch pulse is generated for GS data
writing. This bit is always '0' when the internal clock is selected.
1 = Enabled; the GS clock counter is reset and all OUTn are forced
off whenever an internal latch pulse is generated for GS data writing.
This bit can be set to '1' only when the external clock is selected.
7
8
9
10
DESCRIPTION
11
DCENA
Dot Correction (DC) data write control (default = 0)
0 = Disabled; the DC data latch is fixed to the DC data in the
EEPROM and DC data cannot be changed.
1 = Enabled; the DC data latch is not fixed to the DC data in the
EEPROM and the data in the DC data latch can be changed via
serial interface.
35-12
—
No assigned bit (24-bit data).
No function has not been assigned to these bits. If any data are
written to these bits, device operation is not affected.
Function Control and Global Brightness Control First Data Latch
MSB
11
10
9
8
Auto
DC Data Display External
Timing
Display
GS
Write
Reset
Repeat
Clock
Control
7
6
4
5
4
To Display Timing
Control Block
2
1
LSB
0
3
2
1
LSB
0
Global
Global
Global
Global
Global
Global
Global
BC Data BC Data BC Data BC Data BC Data BC Data BC Data
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Global Brightness Control
Second Data Latch
To Constant-Current
Control Block
3
Auto
Global
Global
Global Global
Global
Global
Global
Data
BC Data BC Data BC Data BC Data BC Data BC Data BC Data
Refresh
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
MSB
6
4
5
7
To Constant-Current Control Block
Figure 27. Function Control Data Latch Bit Assignment
34
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Dot Correction (DC) Data Latch (Register Address = 1110b)
This data latch bit length is 21 bits. These data are used to set the current ratio of each constant-current output.
When the IC is powered on, the DC data latch is set to the data in the DC data EEPROM. When the DC data
write control bit is '1', the data can be changed by data written through the differential signal interface. The data
bit assignments are shown in Table 10 and Figure 28.
Table 10. Dot Correction Data Latch Bit Assignment
BIT NUMBER
BIT NAME
DESCRIPTION
6-0
DCOUT0
Dot correction data for OUT0 (data = 00h to 7Fh, default = EEPROM data)
13-7
DCOUT1
Dot correction data for OUT1 (data = 00h to 7Fh, default = EEPROM data )
20-14
DCOUT2
Dot correction data for OUT2 (data = 00h to 7Fh, default = EEPROM data )
35-21
—
No assigned bit (24-bit data).
No function has not been assigned to these bits. If any data are written to
these bits, device operation is not affected.
21-Bit Dot Correction Data
MSB
20
OUT2
GS Data
Bit 11
15
¼
14
13
OUT1
OUT2
OUT2
GS Data GS Data GS Data
Bit 11
Bit 0
Bit 1
8
¼
7
6
OUT0
OUT1
OUT1
GS Data GS Data GS Data
Bit 11
Bit 0
Bit 1
1
¼
LSB
0
OUT0
OUT0
GS Data GS Data
Bit 0
Bit 1
To Display Timing Control Block
Figure 28. Dot Correction Data Latch Bit Assignment
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EEPROM1 and EEPROM2 Write Data Latch
Each data latch bit length is 36 bits. The EEPROM1 write data latch sets the buck converter maximum on-duty
ratio, VFB target voltage, and the EEPROM differential interface mode. The EEPROM2 write data latch is used
to set the EEPROM DC default value.
EEPROM1 Write Data Latch (Register Address = 1100b)
The data bit assignments of the EEPROM write data latch 1 are shown in Table 11 and Figure 29.
Table 11. EEPROM1 Write Data Latch Bit Assignment
BIT NUMBER
BIT NAME
2-0
ONDUTY
PH on-duty (data = 0h to 7h, factory default = 0h)
DESCRIPTION
7-3
FBVOLT
FB target voltage (data = 00h to 1Fh, factory default = 00h)
9-8
DSIMOD
Differential signal interface (DSI) timing mode (data = 0h to 3h, factory default
= 0h)
13-10
LATTIM
Internal latch generation delay time (data = 0h to Fh, factory default = Fh)
27-14
—
35-28
WRCMD1
No EEPROM bits (14-bit data). The data cannot be stored in these bits even
if data are written to these bits.
Write command. When data are written to the EEPROM1 write data latch,
these data must be A5h (10100101b).
EEPROM1 Write Data Latch
MSB
35
Write
Command
Bit 7
28
¼
27
14
Write
No
Command EEPROM
Bit 0
Bit 13
¼
13
Latch
No
EEPROM Delay Time
Bit 3
Bit 0
10
Latch
¼ Delay Time
Bit 0
9
8
7
FB Target
DSI
DSI
Voltage
Timing
Timing
Mode Bit 1 Mode Bit 0 Data Bit 4
3
¼
2
1
LSB
0
FB Target
PH on
PH on
PH on
Voltage Duty Data Duty Data Duty Data
Data Bit 0
Bit 0
Bit 1
Bit 2
Figure 29. EEPROM1 Write Data Latch Bit Assignment
Maximum On-Duty Data for Buck Converter
The TLC5970 buck converter always operates with the Pulse Frequency Modulation (PFM) mode. Therefore, the
PH on-duty should be set to the value calculated by Table 12 to avoid inductor current saturation at the inductor.
Table 12. Maximum On-Duty Selection Truth Table
36
ON-DUTY DATA (Binary)
ON-DUTY DATA (Decimal)
ON-DUTY DATA (Hex)
ON-DUTY AT PH (%, Typical)
000
0
0
18
001
1
1
30
010
2
2
42
011
3
3
55
100
4
4
67
101
5
5
80
110
6
6
86
111
7
7
86
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FB Target Voltage
These bits select the target voltage of the FB pin. The FB pin is connected to the LED anode side. The set data
should be determined by Equation 12. Also, the set data should be set to the higher voltage of the three-color
LED line. The buck converter chargeup FB voltage to the FB target voltage (VFB) is set by these bits with a
soft-start sequence after the IC is powered on.
VFB (V) = Typical LED forward voltage × the number of LED in series + 1 V.
VFB set data can be calculated by Equation 12:
(VFB - 7) ´ 31
FB Set Data for VFB =
10
(12)
FB voltage (VFB) can be calculated by Equation 13:
10 ´ FB Set Data
FB Voltage (V) =
+7
31
(13)
Table 13 lists the FB voltage set by FB set data.
Table 13. FB Target Voltage Selection Truth Table
FB DATA
(Binary)
FB DATA
(Decimal)
FB DATA
(Hex)
TARGET FB
VOLTAGE (V)
FB DATA
(Binary)
FB DATA
(Decimal)
FB DATA
(Hex)
TARGET FB
VOLTAGE (V)
0 0000
0
00
7.0
1 0000
16
10
12.2
0 0001
1
01
7.3
1 0001
17
11
12.5
0 0010
2
02
7.6
1 0010
18
12
12.8
0 0011
3
03
8.0
1 0011
19
13
13.1
0 0100
4
04
8.3
1 0100
20
14
13.5
0 0101
5
05
8.6
1 0101
21
15
13.8
0 0110
6
06
8.9
1 0110
22
16
14.1
0 0111
7
07
9.3
1 0111
23
17
14.4
0 1000
8
08
9.6
1 1000
24
18
14.7
0 1001
9
09
9.9
1 1001
25
19
15.1
0 1010
10
0A
10.2
1 1010
26
1A
15.4
0 1011
11
0B
10.5
1 1011
27
1B
15.7
0 1100
12
0C
10.9
1 1100
28
1C
16.0
0 1101
13
0D
11.2
1 1101
29
1D
16.4
0 1110
14
0E
11.5
1 1110
30
1E
16.7
0 1111
15
0F
11.8
1 1111
31
1F
17.0
Differential Signal Interface (DSI) Timing Mode
These bits select a differential interface timing mode from three types of timing modes, as shown in Table 14.
Table 14. DSI Timing Mode Selection Truth Table
DSIMOD DATA (Binary)
DSIMOD DATA (Decimal)
DSIMOD DATA (Hex)
SELECTED MODE
00
0
0
Mode 0 (factory default)
01
1
1
Mode 1
10
2
2
Mode 2
11
3
3
Mode 2
Mode 0 is a low-frequency transfer mode. Maximum transfer frequency is lowest in the timing modes but it is
easy to transfer the data over long distances without transmission errors because this mode can control the data
hold time for the next connected device. The SCKY/SCKZ output level is controlled by the SCKA/SCKB level.
SCKY/SCKZ go to a high level when the SCKA/SCKB level is high. The SCKY/SCKZ output level is controlled by
the SCKA/SCKB level. SCKY/SCKZ go to a low level when the SCKA/SCKB level is low. The SDTY/SDTZ data
change after 30 ns (typical) from when the SCKA/SCKB falling clock is input.
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Mode 1 is the middle frequency transfer mode. Maximum transfer frequency and transmission distance are mean
between mode 0 and mode 2. The SDTY/SDTZ data change after 50 ns (typical) from when the SCKA/SCKB
rising clock is input.
Mode 2 is the high-frequency transfer mode. Maximum transfer frequency is highest in the three timing modes.
This mode should be used for short distance data transmission. SDTY/SDTZ data change after 30 ns (typical)
from when the SCKA/SCKB rising clock is input. The timing diagram for each mode is shown in Figure 30 to
Figure 32.
SDTA
D39A+
D38A+
D37A+
D1A+
D0A+
D39B+
SDTB
D39A-
D38A-
D37A-
D1A-
D0A-
D39B-
D38A
D37A
D1A
D0A
D39B
SCKA
SCKB
Generated Shift Data
(Internal)
D39A
D0
1
Generated Shift Clock
(Internal)
Shift Register Bit 0
(Internal)
D0
3
2
1
Timing Adjusted Shift Clock
(Internal)
D39A
40
3
2
40
D37A
D1A
D0A
D37
D36
D0
D39A
¼
D38A
Shift Register Bit 39
(Internal)
D39
D38
SDTY
D39+
D38+
D37+
D0+
D39A+
SDTZ
D39-
D38-
D37-
D0-
D39A-
SCKY
SCKZ
Figure 30. DSI Timing Mode 0
38
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SDTA
D39A+
D38A+
D37A+
D1A+
D0A+
D39B+
SDTB
D39A-
D38A-
D37A-
D1A-
D0A-
D39B-
D38A
D37A
D1A
D0A
D39B
SCKA
SCKB
Input Shift Data
(Internal)
D0
D39A
1
2
40
3
Input Shift Clock
(Internal)
1
2
3
40
Timing Adjusted Shift Clock
(Internal)
Shift Register Bit 0
(Internal)
D0
D38A
D37A
D1A
D0A
D38
D37
D36
D0
D39A
¼
D39A
Shift Register Bit 39
(Internal)
D39
SDTY
D39+
D38+
D37+
D0+
D39A+
SDTZ
D39-
D38-
D37-
D0-
D39A-
SCKY
SCKZ
Figure 31. DSI Timing Mode 1
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SDTA
D39A+
D38A+
D37A+
D1A+
D0A+
D39B+
SDTB
D39A-
D38A-
D37A-
D1A-
D0A-
D39B-
D39A
D38A
D37A
D1A
D0A
D39B
2
3
SCKA
SCKB
Input Shift Data
(Internal)
D0
1
40
Input Shift Clock
(Internal)
1
2
3
40
Timing Adjusted Shift Clock
(Internal)
Shift Register Bit 0
(Internal)
D39A
D38A
D37A
D1A
D0A
Shift Register Bit 39
(Internal)
D39
D38
D37
D36
D0
D39A
SDTY
D39+
D38+
D37+
D0+
D39A+
SDTZ
D39-
D38-
D37-
D0-
D39A-
¼
D0
SCKY
SCKZ
Figure 32. DSI Timing Mode 2
40
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Internal Latch Pulse Delay Time
Shifted in lower 36-bit data in the 40-bit shift register is latched into the latch selected by the higher four bits of
the shift register after the programmed time by the following code is passed from the last rising edge of SCLK.
The next SCLK rising edge for new data inputs must be input after over two clocks of the internal oscillator clock
period from the shift register is latched.
Table 15. Internal Latch Pulse Delay Time Selection Truth Table
INTERNAL LATCH PULSE DELAY TIME (µs)
FB DATA
(Binary)
FB DATA
(Decimal)
FB DATA
(Hex)
MINIMUM
MAXIMUM
0000
0
0
0.3
0.8
0001
1
1
0.6
1.3
0010
2
2
1.3
2.3
0011
3
3
2.6
4.3
0100
4
4
5.3
8.3
0101
5
5
10
16
0110
6
6
21
33
0111
7
7
42
65
1000
8
8
85
129
257
1001
9
9
170
1010
10
A
341
513
1011
11
B
682
1025
1100
12
C
1365
2049
1101
13
D
2730
4097
1110
14
E
5461
8193
1111
15
F
10922
16385
EEPROM2 Write Data Latch (Register Address = 1101b)
The EEPROM2 write data latch data bit assignments are shown in Table 16 and Figure 33.
Table 16. EEPROM2 Write Data Latch Bit Assignment
BIT NUMBER
BIT NAME
DESCRIPTION
6-0
DCOUT0
Dot correction data for OUT0 (data = 00h to 7Fh, factory default = 7Fh)
13-7
DCOUT1
Dot correction data for OUT1 (data = 00h to 7Fh, factory default = 7Fh)
20-14
DCOUT2
Dot correction data for OUT2 (data = 00h to 7Fh, factory default = 7Fh)
27-21
—
No EEPROM bits (7-bit data). Data cannot be stored in these bits even if
data are written to these bits.
35-28
WRCMD2
Write command. When data are written to the EEPROM1 write data latch,
these data must be 5Ah (01011010b).
EEPROM2 Write Data Latch
MSB
35
Write
Command
Bit 7
28
¼
27
Write
No
Command EEPROM
Bit 0
Bit 6
¼
21
20
No
EEPROM
Bit 0
OUT2
DC Data
Bit 6
¼
14
13
OUT2
DC Data
Bit 0
OUT1
DC Data
Bit 6
¼
7
6
OUT1
DC Data
Bit 0
OUT0
DC Data
Bit 6
LSB
0
¼
OUT0
DC Data
Bit 0
Figure 33. EEPROM2 Write Data Latch Bit Assignment
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EEPROM Data Write Procedure
The DC data and the maximum on-duty data can be programmed into the EEPROM with the following
procedure:
1. Turn on the VCC power supply.
2. Set the VROM pin voltage to 19 V ± 0.5 V. The supply current is 5 mA (typical). The buck converter stops
while the VROM pin is held at the voltage.
3. Write the data for EEPROM write data latch 1 with the address. Write the command and the write data to
EEPROM data latch address.
4. Wait for more than 40 ms without data transfer. The maximum wait time is unlimited.
5. Stop supplying 19 V to the VROM pin and release the pin.
6. Write the grayscale data to turn on the LED and check LED brightness.
7. If the brightness must be adjusted, send new dot correction data to the DC data latch for brightness adjust.
8. Check the brightness again.
9. Repeat steps 8 and 9 to determine the best DC data.
10. Write the best DC data to the EEPROM write data latch 2 using steps 3 to 5 in this sequence.
Readout Register
EEPROM Data Readout Register (Register Address = 1011b)
When any data are written to this register address, the programed data in the EEPROM are loaded to the lower
36 bits in the 40-bit shift register from this readout register (register address = 1011b). The higher 4-bit data in
the 40-bit shift register are not changed from 1011b. The loaded data can be read out from SDTY and SDTZ and
syncronized by the shift clock generated from SCKA and SCKB. The data bit assignments are shown in Table 17
and Figure 34.
Table 17. EEPROM Data Readout Register Bit Assignment
BIT NUMBER
BIT NAME
DESCRIPTION
6-0
RDDC0
Dot correction data for OUT0 in EEPROM (7-bit data)
13-7
RDDC1
Dot correction data for OUT1 in EEPROM (7-bit data)
20-14
RDDC2
Dot correction data for OUT2 in EEPROM (7-bit data)
23-21
RDONDTY
28-24
RDVFB
FB target voltage (5-bit data)
30-29
RDDSI
DSI mode (2-bit data)
34-31
RDDLY
Internal data latch pulse delay time (4-bit data)
35
RDRSV
TI reserved data (1-bit data, no fixed data)
On-duty (4-bit data)
EEPROM Data Read Out Register
MSB
35
34-31
30-29
28-24
DSI Timing FB Target
Latch
TI
Voltage
Reserved Delay Time Mode
Bits[1:0]
Bits[4:0]
Bits[3:0]
Bit 0
23-21
20
PH on
Duty
Bits[2:0]
OUT2
DC Data
Bit 6
¼
14
13
OUT2
DC Data
Bit 0
OUT1
DC Data
Bit 6
¼
12-7
6
OUT1
DC Data
Bit 0
OUT0
DC Data
Bit 6
LSB
0
¼
OUT0
DC Data
Bit 0
Figure 34. EEPROM Data Readout Register Bit Assignment
42
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Status Information Data (SID) Readout Register (Register Address = 1010b)
When any data are written to this register address, the status of five error detections are loaded to the lower 36
bits in the 40-bit shift register from this readout register (register address = 1010b). The higher 4-bit data in the
40-bit shift register are not changed from 1010b. The loaded data can be readout from SDTY and SDTZ and
syncronized by the shift clock generated from SCKA and SCKB. The data bit assignments are are shown in
Table 18 and Figure 35.
Table 18. SID Readout Register Bit Assignment
BIT NUMBER
BIT NAME
DESCRIPTION
0
LOD
LED open detection (LOD) error flag
0 = All OUTn are either connected to the LED lamp or are not
connected to the LED lamp. When all OUTn are not connected to
LED lamp, the OVP flag is set to '1'.
1 = One or two OUTn are not connected to the LED lamp. This bit is
set to '1' when the voltage of OUTn connected to the LED lamp is
greater than approximately 4 V. Also, this bit is set to '1' when the
SWOFF pin is connected to VREG.
1
SCP
Short-Circuit Protection (SCP) error flag
0 = The buck converter is operating normally. Also, this bit is set to
'0' when SWOFF is connected to VREG.
1 = The buck converter is not operated by the SCP.
2
OVP
Overvoltage Protection (OVP) flag
0 = The buck converter is operating normally. Also, this bit is set to
'0' when SWOFF is connected to VREG.
1 = The buck converter is not operated by the OVP.
PTD
Pre-Thermal Shutdown (PTD) log
0 = The LED driver has been in normal operation after the previous
readout register reading.
1 = The LED driver has stopped operating due to the device
temperature exceeding the PTD detect temperature after the
previous readout register reading. This log is held until these register
data are readout.
4
TSD
Thermal Shutdown (TSD) log
0 = The buck converter/LED driver/interface has been in normal
operation after the previous readout register reading.
1 = The buck converter/LED driver/interface has stopped operating
due to the device temperature exceeding the TSD detect
temperature after the previous readout register reading. This flag is
held until these register data are readout.
35-5
—
3
TI reserved data (31-bit data, no fixed data)
Status Information Data (SID) Read Out Register
MSB
35
34
TI
Reserved
Bit 30
TI
Reserved
Bit 29
6
¼
5
TI
TI
Reserved Reserved
Bit 0
Bit 1
4
3
2
1
LSB
0
TSD
Log
PTD
Log
OVP
Flag
SCP
Flag
LOD
Flag
Figure 35. SID Readout Register Bit Assignment
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DEVICE PROTECTION
When the Short-Circuit Protection (SCP) and Overvoltage protection (OVP) are operating, the buck converter
stops. Afterwards, the buck converter is restarted with a soft-start when any data are written to the restart
operation address, 1001b. The TLC5970 has an LED Open Detection (LOD) and four device protections as
listed:
1. LED open detection (LOD): When SWOFF is connected to GND, the LOD can detect if one or two LEDs
are opened or if OUTn is shorted to GND. The LOD flag is set to '1' in the readout data register when LEDs
open or when OUTn is shorted to GND. If all LEDs are opened, the OVP flag comes up because the
OUT0-OUT2 voltage is not pulled up. When SWOFF is connected to the VREG level, the LOD flag is set to
'1' when the voltage of any OUTn is less than approximately 0.3 V at the 33rd GS clock from when OUTn is
turned on. Also, the LOD data are kept until the next 33rd GS clock. Therefore, GS data must be set at 33d
(decimal data) or more to ensure the correct LOD data.
2. Short-Circuit Protection (SCP): The SCP detects if the buck converter output is overloaded or if the FB line
is open. SCP operates in this manner:
(a) The SCP circuit observes the FB pin voltage.
(b) If the FB is under 4 V (typical), then the SCP timer starts to count the number of times the PH switches.
(c) When the SCP timer counts to 4, if FB voltage is still below 4 V, the SCP circuit stops the buck converter
and the LED driver from operating. Also, the buck converter target voltage is set to the FB voltage
programmed in the EEPROM at same time.
(d) The SCP flag is set in the readout register.
(e) The differential interface can be used even if buck converter is not operating.
It is required to write any data to the address 1001b to restart the device operation.
3. Overvoltage Protection (OVP): The OVP detects if the buck converter target voltage is set to the maximum
code. Also, the OVP detects when all LEDs are opened. The OVP does not work when the SWOFF signal
level is high. Therefore, the OVP flag in the SID is always '0'. The OVP circuit operates in this manner:
(a) The OVP circuit checks that the internal digital-to-analog converter (DAC) code is at the 33rd GS clock.
(b) If the DAC code is not the maximum code, the OVP period counter is reset. If the DAC code is the
maximum code, then the OVP period counter is counted up.
(c) When the OVP period counter becomes 4, the OVP circuit stops the LED driver from operating and sets
the DAC code to the FB voltage programmed in the EEPROM. Then the buck converter operation does
not stop.
(d) The OVP flag is set to '1' in the readout register.
(e) The differential interface can be used even if the buck converter is not operating.
(f) The LED driver cannot be controlled again until any data are written to the address 1001b to clear the
OVP flag.
4. Pre-Thermal Shutdown (PTD): The PTD stops the LED driver operation at TPTD (TPTD = +138°C, typical)
device temperature to avoid the device temperature from becoming higher. PTD operation follows this logic:
(a) The LED driver (OUT0to OUT2) is forced off.
(b) Set the PTD flag in the readout register.
(c) Start the LED driver control again when the device temperature drops below TPTD – THYSP (THYSP = +8°C,
typical).
5. Thermal Shutdown (TSD): The TSD stops the buck coverter/LED driver/differential interface operation at
TTSD (TTSD = +168°C, typical) device temperature to prevent the device temperature from becoming too high.
TSD operation follows this sequence:
(a) The buck converter switching/LED driver (OUT0 to OUT2)/differential interface are forced off.
(b) The TSD flag is set in the readout register.
(c) Buck converter target voltage is set to the FB voltage programmed in the EEPROM.
(d) Differential interface operation starts again when the device temperature drops below TTSD – THYST
(THYST = +10°C, typical). Then the buck converter starts to operate.
44
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PRE-BOOST FUNCTION
The TLC5970 has a pre-boost function. This function increases the DAC code of the buck converter a few steps
from the 16th GS clock before the LED turns on to prevent the output voltage from decreasing much. The
pre-boost is finished at the 33rd GS clock rising edge. After the GS counter is reset, the first 16 GS clocks are
spent for the pre-boost and the LED is turned on from the 17th clock. Therefore, 4112 GS clocks are needed to
display the full GS data in the first period in auto repeat mode. In no auto repeat mode, 4112 GS clocks are
always needed for one display period.
UNDERVOLTAGE LOCKOUT (UVLO)
An undervoltage lockout (UVLO) circuit is implemented to keep the device disabled when VREG is lower than the
UVLO start voltage. The following list describes each functional block status during a UVLO condition:
• The buck converter control block, constant-current timing control, and oscillator are initialized.
• The 40-bit data shift register is set to all '0'.
• Each data latch is set to the default value except for the DC latch.
• The data in the EEPROM is set to the DC data latch.
• The power-supply source for the differential interface is connected to VCC.
• FB voltage is discharged to GND.
NOISE REDUCTION
Large surge currents would flow through the IC and the board if all three LED channels are fully turned on
simultaneously at the start of each grayscale cycle. These large surge currents could introduce detrimental noise
and electromagnetic Interference (EMI) into other circuits. The TLC5970 turns on/off each OUTn with
approximately a 40-ns time difference to reduce the switching noise and LED anode voltage drop.
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APPLICATION CIRCUITS
The TLC5970 can be used to increase the LED drive current for high-current LEDs with the high-current LED
operating mode (Figure 36) or with the parallel operating mode (Figure 37). In the parallel operating mode, the
external clock mode should be used to avoid flickering that can occur in an unsyncronized internal clock.
VCC
Power
Supply
GND
GND
VCC
SWOFF
0.01 mF
0.1 mF
PH
VREG
GND
VREGIF
SWOFF
0.01 mF
0.01 mF
BOOT
VREG
0.1 mF
FB
Open
SDTY
SDTZ
SDKY
SDKZ
PH
0.01 mF
BOOT
VREGIF
IREF2
Controller
VCC
FB
IREF2
IREF1
OUT2
IREF1
OUT2
IREF0
OUT1
IREF0
OUT1
VROM
OUT0
VROM
OUT0
SDTA
SDTY
SDTA
SDTY
SDTB
SDTZ
SDTB
SDTZ
SCKA
SCKY
SCKA
SCKY
SCKB
SCKZ
SCKB
SCKZ
Open
TLC5970
TLC5970
Figure 36. High-Current LED Operating Mode
VCC
Power
Supply
GND
GND
VCC
SWOFF
0.01 mF
0.1 mF
VREG
PH
BOOT
VREGIF
FB
GND
SWOFF
0.01 mF
0.01 mF
0.1 mF
IREF2
Controller
Open
SDTY
SDTZ
SDKY
SDKZ
VCC
VREG
PH
0.01 mF
BOOT
VREGIF
FB
IREF2
IREF1
OUT2
IREF1
OUT2
IREF0
OUT1
IREF0
OUT1
Open
VROM
OUT0
VROM
OUT0
SDTA
SDTY
SDTA
SDTY
SDTB
SDTZ
SDTB
SDTZ
SCKA
SCKY
SCKA
SCKY
SCKB
SCKZ
SCKB
SCKZ
TLC5970
TLC5970
Figure 37. Parallel Operating Mode
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The TLC5970 can be used to drive several LED lamps for small-current LEDs with the master-slave operation
mode (Figure 38). In this operating mode, BC data and DC data in the master device should not be set to '0' to
hold the LED anode (FB) voltage.
VCC
Power
Supply
GND
GND
VCC
SWOFF
0.01 mF
0.1 mF
VREG
PH
GND
VREGIF
0.01 mF
0.1 mF
FB
IREF2
Controller
Open
SDTY
SDTZ
SDKY
SDKZ
PH
Open
BOOT
Open
SWOFF
0.01 mF
BOOT
VCC
VREG
VREGIF
FB
IREF2
IREF1
OUT2
IREF1
OUT2
IREF0
OUT1
VROM
OUT0
IREF0
OUT1
VROM
OUT0
SDTA
SDTY
SDTA
SDTY
SDTB
SDTZ
SDTB
SDTZ
SCKA
SCKY
SCKA
SCKY
SCKB
SCKZ
SCKB
SCKZ
Open
TLC5970
TLC5970
Figure 38. Master/Slave Operating Mode
The TLC5970 can be used as a 5 V single power-supply LED without a buck converter operating mode, as
shown in Figure 39.
Power
Supply
(5V)
VCC
GND
GND
VCC
PH
Open
SWOFF
Open
VREG
VREGIF
FB
Open
SDTY
SDTZ
SDKY
SDKZ
PH
Open
BOOT
Open
VREGIF
IREF2
Controller
VCC
BOOT
SWOFF
VREG
GND
FB
IREF2
IREF1
OUT2
IREF1
OUT2
IREF0
OUT1
IREF0
OUT1
VROM
OUT0
VROM
OUT0
SDTA
SDTY
SDTA
SDTY
SDTB
SDTZ
SDTB
SDTZ
SCKA
SCKY
SCKA
SCKY
SCKB
SCKZ
SCKB
SCKZ
Open
TLC5970
TLC5970
Figure 39. No Buck Converter Operating Mode
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