LG Semicon 8-bit Microcontrollers GMS81604/08 Revision History Rev 1.2 (Dec. 1998) Redraw package dimension on page 5~6. Rev 1.1 (Nov. 1998) Operating Voltage, 2.7~5.5V is extended with 2.4~5.5V. Operating Temperature, -20~80°C is extended with -20~85°C. Add the "Typical Characteristics" on page 16, 17. Add the unused port guidance on page 48. Revision the information for the OTP programming guidance, recommand using "Intelligent Mode" on page 49. Add the chapter for OTP programming specification as an appendix. Rev 1.0 (Nov. 1997) First Edition Second Edition Published by MCU Application Team 1998 LG Semicon Co., Ltd. All right reserved. Additional information of this manual may be served by LG Semicon offices in Korea or Distributors and Representatives listed at address directory. LG Semicon reserves the right to make changes to any information here in at any time without notice. The information, diagrams and other data in this manual are correct and reliable; however, LG Semicon Co,. Ltd. is in no way responsible for any violations of patents or other rights of the third party generated by the use of this manual. Table of Contents OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 PIN ASSIGNMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 PACKAGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 PIN DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 PORT STRUCTURES 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 MEMORY ORGANIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 BASIC INTERVAL TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 TIMER/COUNTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 8-bit Timer/Counter Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 16-bit Timer/Counter Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 8-bit Capture Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 16-bit Capture Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 ANALOG TO DIGITAL CONVERTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 How to Use A/D Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 BUZZER FUNCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 External Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 BRK Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Multiple Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 WATCHDOG TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 STOP MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Release Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Minimizing Current Consumption in Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . 43 RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 POWER FAIL PROCESSOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 OSCILLATOR CIRCUIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 UNUSED PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 GMS81608T (OTP) PROGRAMMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 1. Using the Universal programmer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 2. Using the general EPROM(27C256) programmer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 GMS81608T PROGRAMMING MANUAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 APPENDIX A. INSTRUCTION SET B. MASK ORDER SHEET LG Semicon GMS81604/08 GMS81604 / GMS81608 CMOS SINGLE-CHIP 8-BIT MICROCONTROLLER OVERVIEW Description The GMS81604/08 is a high-performance CMOS 8-bit microcontroller with 4K or 8K bytes of ROM. The device is one of GMS800 family. The LG Semicon GMS81604/08 is a powerful microcontroller which provides a highly flexible and cost effective solution to many embedded control applications. The GMS81604/08 provides the following standard features: 8K bytes of ROM, 256 bytes of RAM, 35 I/O lines(33 lines for 40PDIP), 16-bit or 8-bit timer/counter, a precision analog to digital converter, on-chip oscillator and clock circuitry. In addition, the GMS81604/08 supports power saving modes to reduce power consumption. The Stop Mode saves the RAM contents but freezes the oscillator disabling all other chip functions until the next hardware reset or external interrupt. Features 4K/ 8K On-chip Program Memory One Buzzer Driving port 256 Bytes of On-Chip Data RAM 31 Programmable I/O, 4 Input pins, Instruction execution time: 0.5us at 8MHz Twelve Interrupt Sources 2.4V to 5.5V Operating Range All LED Direct Drive Output Ports 1~8 MHz Operating frequency 8-Channel 8-Bit On-Chip Analog to Digital Converter Basic Interval Timer Four 8-Bit Timer/ Counters (can be used as two 16-bit) Power Fail Processor (Noise immunity circuit) Power Down Mode (Stop Mode) Four external interrupt ports Two Programmable Clock Out Memory Proliferation Device ROM Bytes RAM Bytes GMS81604 4K 256 GMS81608 8K 256 GMS81608T 8K EPROM 256 Development Tools The GMS800 family is supported by a full-featured macro assembler, an in-circuit emulators CHOICEJr. T M , socket adapters for OTP device. The availability of OTP devices are especially useful for customers expecting frequent code changes and updates. The OTP devices, packaged in plastic pack- ages permit the user to program them once. In addition to the program memory, the configuration fuses must be programmed. GMS81604, GMS81608 In-Circuit Emulators CHOICE-Jr. T M OTP devices GMS81608T (40 DIP) GMS81608T K (42 SDIP) GMS81608T PL (44 pin PLCC) Socket Adapters for OTP Devices OA816A-40PD (40 DIP) OA816A-42SD (42 SDIP) OA816A-44PL (44 PLCC) Assembler LGS Macro Assembler 1 GMS81604/08 LG Semicon Device Selection Guide ROM size 4K bytes 8K bytes 8K bytes (OTP) 2 Package Ordering code 40DIP GMS81604 42SDIP GMS81604 K 44PLCC GMS81604 PL 40DIP GMS81608 42SDIP GMS81608 K 44PLCC GMS81608 PL 40DIP GMS81608T 42SDIP GMS81608T K 44PLCC GMS81608T PL LG Semicon GMS81604/08 BLOCK DIAGRAM Figure 1. Block Diagram 3 GMS81604/08 LG Semicon PIN ASSIGNMENT 42 SDIP 40 PDIP 44 PLCC Figure 2. Pin Connections PACKAGES Part GMS8160X GMS8160X K GMS8160X PL 4 Package Type 40DIP 42SDIP 44PLCC ← "X" means 4(4K bytes) or 8(8K bytes). LG Semicon GMS81604/08 PACKAGE 42SDIP UNIT: INCH 0.600 BSC min. 0.015 0.190 max. 1.470 1.450 0.140 0.120 0.045 0.035 0.020 0.016 0.550 0.530 0.012 0.008 0-15° 0.070 BSC 40DIP UNIT: INCH 0.600 BSC 0.022 0.015 0.065 0.045 0.100 BSC 0.140 0.120 min. 0.015 0.200 max. 2.075 2.045 0.550 0.530 0-15° 0.012 0.008 5 GMS81604/08 LG Semicon 44PLCC UNIT: INCH 0.695 0.685 0.032 0.026 0.656 0.650 0.695 0.685 0.050 BSC 0.012 0.0075 0.630 0.590 min. 0.020 0.656 0.650 0.120 0.090 0.180 0.165 6 LG Semicon GMS81604/08 PIN DESCRIPTIONS V D D : Supply voltage. V SS : Circuit Ground. TEST : For test purposes only. Connect it to V D D . RESET : Reset the MCU. X IN : Input to the inverting oscillator amplifier and input to the internal clock operating circuit. X O U T : Output from the inverting oscillator amplifier. R00~R07 : R0 is an 8-bit, CMOS, bidirectional I/O port. As an output port each pin can sink several LS TTL inputs. R0 pins that have 1 or 0 written to their Port Direction Mode Register, can be used as outputs or inputs. R10~R17 : R1 is an 8-bit, CMOS, bidirectional I/O port. As an output port each pin can sink several LS TTL inputs. R1 pins that have 1 or 0 written to their Port Direction Mode Register, can be used as outputs or inputs. R40~R47 : R4 is an 8-bit, CMOS, bidirectional I/O port. As an output port each pin can sink several LS TTL inputs. R4 pins that have 1 or 0 written to their Port Direction Mode Register, can be used as outputs or inputs. In addition, Port 4 serves the functions of the various following special features. Port Pin INT0 (External Interrupt 0) R41 INT1 (External Interrupt 1) R42 R43 INT2 (External Interrupt 2) INT3 (External Interrupt 3) R44 EC0 (External Count Input to Timer/ Counter 0) EC2 (External Count Input to Timer/ Counter 2) R46 R47 Port R55 serves the functions of special features. Port Pin Alternate Function R55 BUZ (Square wave output for Buzzer driving) R60~R67 : R6 is an 8-bit, CMOS, I/O port. R60~R63 can be used as only input, can not be output, R64~R67 are bidirectional I/O port. As an output port each pin can sink several LS TTL inputs. R64~R67 pins that have 1 or 0 written to their Port Direction Mode Register, can be used as outputs or inputs. R6 serves the functions of following special features. Port Pin R60 R61 R62 R63 R64 R65 R66 R67 Alternate Function AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 (ADC (ADC (ADC (ADC (ADC (ADC (ADC (ADC input input input input input input input input 0) 1) 2) 3) 4) 5) 6) 7) AV D D : Supply voltage to the ladder resistor of ADC circuit. To enhance the resolution of analog to digital converter, use independent power source as well as possible, other than digital power source. Alternate Function R40 R45 R50, R51, R55 : R5 is a 3-bit, CMOS, bidirectional I/O port. As an output port each pin can sink several LS TTL inputs. R5 pins that have 1 or 0 written to their Port Direction Mode Register, can be used as outputs or inputs. R50 and R51 differs in having internal pull-ups. T1O (Timer 1 Clock-Out) T3O (Timer 3 Clock-Out) 7 GMS81604/08 Port Pin LG Semicon Descriptions I/O Primary Functions Secondary Functions Pull-up/ Pull-down RESET STOP Mode VDD - Power supply to MCU - - - - VSS - Ground - - - - AVDD - Power supply for ADC - - - - TEST I Test mode - - - - RESET I Reset the MCU - Pull-up Low Last state X IN I Oscillation input - - Oscillation Low O Oscillation XOUT Oscillation output - - R00~R07 I/O General I/O - - Input 3) Last state R10~R17 I/O General I/O - - Input 3) Last state R40/INT0 R41/INT1 R42/INT2 R43/INT3 R44/EC0 R45/EC2 R46/T1O R47/T3O I/O I/O I/O I/O I/O I/O I/O I/O General I/O " " " " " " " External interrupt 0 External interrupt 1 External interrupt 2 External interrupt 3 External count input 0 External count input 2 Timer 1 output Timer 3 output - Input 3) Last state R50 1) R51 1) R55/BUZ I/O I/O I/O General I/O " " Buzzer driving output Input 3) Last state R60/AN0 R61/AN1 R62/AN2 R63/AN3 R64/AN4 R65/AN5 R66/AN6 R67/AN7 I I I I I/O I/O I/O I/O General Input " " " General I/O " " " Analog Analog Analog Analog Analog Analog Analog Analog Input 3) Last state input input input input input input input input 0 1 2 3 4 5 6 7 Pull-up Pull-up - - High 2) 2) NOTES: 1. R50 and R51 are not physically served on 40 pin package. 2. When input mode is selected, pull-up is activated. In output mode, pull-up is de-activated. 3. In reset status, status of R50,R51 are weak high (Typ. impedance 50~100k Ω). Other pin impedance is very high(High-Z). 8 LG Semicon GMS81604/08 PORT STRUCTURES R00~R07, R10~R17 VD D DATA REG. PROTECT DIODE DATA BUS DIRECTION REG. DATA BUS PROTECT DIODE VS S MUX DATA BUS Rd. R40/INT0, R41/INT1, R42/INT2, R43/INT3, R44/EC0, R45/EC2 PMR4 DATA REG. DATA BUS DIRECTION REG. DATA BUS DATA BUS MUX Rd. ALTERNATE FUNCTION EX) INT0 R46/T1O, R47/T3O, R55/BUZ Selection (PMR4 or PMR5) ALTERNATE FUNCTION EX) T1O MUX DATA REG. DATA BUS DATA BUS DIRECTION REG. DATA BUS MUX Rd. 9 GMS81604/08 LG Semicon R50, R51 PULL-UP RESISTOR DATA REG. DATA BUS DIRECTION REG. DATA BUS MUX DATA BUS INPUT MODE: PULL-UP RESISTOR IS ACTIVATED. OUTPUT MODE: PULL-UP RESISTOR IS DE-ACTIVATED. Rd. R60/AN0, R61/AN1, R62/AN2, R63/AN3 DATA BUS Rd. Rd. TO A/D Converter Ch. Select R64/AN4, R65/AN5, R66/AN6, R67/AN7 DATA REG. DATA BUS DIRECTION REG. DATA BUS DATA BUS MUX Rd. Rd. TO A/D Converter Ch. Select 10 0: Output 1: Reset, Input, AD ch. select LG Semicon GMS81604/08 RESET TEST OTP: No P-Ch diode Pull-up Resister X I N , XO U T X IN XO U T STOP 11 GMS81604/08 LG Semicon ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . -0.3 to +6.0 V Storage Temperature . . . . . . . . . . . . -40 to +125 °C Voltage on any pin with respect to Ground (V SS ) . . . . . . -0.3 to V DD +0.3 V Maximum current out of V SS pin . . . . . . . . . 150 mA Maximum current into V DD pin 100 mA . . . . . . . . . Maximum current sunk by (I OL per I/O Pin) . . . . 2 0 m A Maximum output current sourced by (I OH per I/O Pin) . . . . . . . . . . . . . . . 8 m A Maximum current ( Σ I OL ) . . . . . . . . . . . . Maximum current ( Σ I OH ) . . . . . . . . . . . . . 50 mA Notice: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these of any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 120 mA Recommended Operating Conditions Parameter Symbol Condition Specifications Min. Max. Unit Supply Voltage V DD f XIN = 8 MHz f XIN = 4 MHz 4.5 2.4 5.5 5.5 V Operating Frequency f XIN V DD = 4.5~5.5V V DD = 2.4~5.5V 1 1 8 4.2 MHz -20 85 °C Operating Temperature 12 T OPR LG Semicon GMS81604/08 DC Characteristics ( 5V ) (V DD = 5.0V ± 1 0 % , V SS = 0 V , T A = -20 ~ 85 °C, f XIN = 8 M H z ) Parameter Pin Symbol Specifications Test Condition Unit Min. Typ.* Max. X IN , RESET, R40~R45 V IH1 - 0.8V DD - V DD V R0,R1,R46,R47 R5,R6 V IH2 - 0.7V DD - V DD V X IN, RESET, R40~R45 V IL1 - 0 - 0.2V DD V R0,R1,R46,R47 R5,R6 V IL2 - 0 - 0.3V DD V Output High Voltage R0,R1,R4,R5,R6 VOH V DD = 5V I OH = -2mA V D D -1.0 V D D -0.4 - V Output Low Voltage R0,R1,R4,R5,R6 V OL V DD = 5V I OL = 10mA - 0.6 1.0 V Power Fail Detect Voltage V DD V PFD V DD =3~4V 3.0 - 4.0 V Input Leakage Current RESET, R0, R1, R4, R5, R6 I IH V I = V DD -5.0 - 5.0 uA I IL V I = 0V -5.0 - 5.0 uA RESET I P1 V DD = 5V -180 -120 -30 uA R50, R51 I P2 V DD = 5V -90 -60 -15 uA Operating mode I DD f XIN =4MHz f XIN =8MHz - 4.5 8 8 15 mA Input High Voltage Input Low Voltage Input Pull-up Current Power Current Hysteresis STOP mode I STOP V DD = 5V - 2 20 uA RESET, R40~R45 V T+ ~V T - V DD = 5V 0.5 0.8 - V * : Data in "Typ" column is at 5 V, 25 ° C unless otherwise stated. These parameters are for design guidance only and are not tested. A/D Converter Characteristics ( 5V ) (V DD = 5.0V ± 1 0 % , V AIN = 5.0V, V SS = 0V, T A = 25 °C ) Parameter Specifications Symbol Min. Unit Typ.* Max. Analog Input Range V AIN V SS - V AVDD V Non-linearity Error N LE - 0.7 ± 1.5 LSB Differential Non-linearity Error N DIF - 0.1 ± 0.5 LSB Zero Offset Error N OFF - 1.5 ± 2.5 LSB N FS - 1.0 ± 1.5 LSB Full Scale Error A CC - 2.0 ± 3.0 LSB AV DD Input Current I AVDD - 0.5 1.0 mA Conversion Time T CONV - - 40 uS Analog power supply Input Range V AVDD 4.5 5.0 5.5 V Accuracy * : Data in "Typ" column is at 5 V, 25 ° C unless otherwise stated. These parameters are for design guidance only and are not tested. 13 GMS81604/08 LG Semicon DC Characteristics ( 3V ) (V DD = 3.0V ± 1 0 % , V SS = 0 V , T A = -20 ~ 85 °C, f XIN = 4 M H z ) Parameter Pin Symbol Specifications Test Condition Unit Min. Typ.* Max. X IN , RESET, R40~R45 V IH1 - 0.8V DD - V DD V R0,R1,R46,R47 R5,R6 V IH2 - 0.7V DD - V DD V X IN , RESET, R40~R45 V IL1 - 0 - 0.2V DD V R0,R1,R46,R47 R5,R6 V IL2 - 0 - 0.3V DD V Output High Voltage R0,R1,R4,R5,R6 VOH V DD = 3V I O H = -1mA V D D -0.5 V D D -0.3 - V Output Low Voltage R0,R1,R4,R5,R6 V OL V DD = 3V I OL = 5mA - 0.5 0.7 V Power Fail Detect Voltage** - - - - - V Input Leakage Current RESET, R0, R1, R4, R5, R6 I IH V I = V DD -3.0 - 3.0 uA I IL V I = 0V -3.0 - 3.0 uA Input Pull-up Current RESET I P1 V DD = 3V -60 -40 -15 uA R50, R51 I P2 V DD = 3V -30 -20 -7.5 uA Input High Voltage Input Low Voltage Power Current Hysteresis - f XIN =4MHz - 2 5 mA STOP mode Operating mode I STOP I DD V DD = 3V - 1 10 uA RESET, R40~R45 V T+ ~V T - V DD = 3V 0.3 0.6 - V * : Data in "Typ" column is at 3 V, 25 ° C unless otherwise stated. These parameters are for design guidance only and are not tested. **: Power Fail Detection function is not available on 3V operation. A/D Converter Characteristics ( 3V ) (V DD = 3.0V ± 1 0 % , V AIN = 3.0V, V SS = 0V, T A = 25 °C) Parameter Specifications Symbol Min. Unit Typ.* Max. Analog Input Range V AIN V SS - V AVDD V Non-linearity Error N LE - 0.2 ± 1.0 LSB Differential Non-linearity Error N DIF - 0.1 ± 0.5 LSB Zero Offset Error N OFF - 2.0 ± 2.5 LSB N FS - 1.0 ± 1.5 LSB Full Scale Error A CC - 2.0 ± 3.0 LSB A V DD Input Current I AVDD - 0.3 0.5 mA Conversion Time T CONV - - 40 uS Analog power supply Input Range V AVDD 2.7 3.0 3.3 V Accuracy * : Data in "Typ" column is at 3 V, 25 ° C unless otherwise stated. These parameters are for design guidance only and are not tested. 14 LG Semicon GMS81604/08 AC Characteristics (V DD = 2.7~5.5V, V SS = 0 V , T A = -20 ~ 85 °C) Parameter Pin Specifications Symbol Unit Min. Typ. Max. f XIN 1 - 8 MHz Main clock frequency X IN Oscillation stabilization Time X IN , X OUT t ST 20 - - ms External Clock Pulse Width X IN tC P W 80 - - ns External Clock Transition Time X IN t RCP , t FCP - - 20 ns Interrupt Pulse Width INT0, INT1, INT2, INT3 t IW 2 - - t SYS * RESET Input Low Width RESET t RST 8 - - t SYS * Event Counter Input Pulse Width EC0, EC2 tE C W 2 - - t SYS * Event Counter Transition Time EC0, EC2 t REC , t FEC - - 20 ns *: t SYS is 2/f XIN . Timing Chart tC P W 1 / f XIN tC P W 0.9V D D 0.1V D D X IN tR C P tF C P tI W INT0, INT1 INT2, INT3 tI W 0.8V D D 0.2V D D tR S T RESET 0.2V D D tE C W EC0, EC2 tE C W 0.8V D D 0.2V D D tR E C tF E C 15 GMS81604/08 LG Semicon TYPICAL CHARACTERISTICS These parameters are for design guidance only and are not tested. I DD - V D D ID D (mA) I STOP ISTOP (uA) T A =25 °C 8 T A =25 °C 8 fXIN = 8MHz 6 6 4 4 f XIN = 4MHz 2 2 0 2 3 4 5 6 (V) 0 VD D 2 3 4 5 2 3 4 6 (V) V D D =5V I OL - V OL IO L (mA) 24 IO H - V O H IO H (mA) V D D =5.0V T A =25 °C 24 18 18 12 12 6 6 0 1 2 3 V OL (V) 4 Operating area f XIN (MHz) T A = -20~80 °C 8 6 4 2 0 16 1 2 3 4 5 VDD (V) 0 V D D =5.0V T A =25 °C 1 V D D -V O H (V) VD D LG Semicon GMS81604/08 V D D =3.0V I OL - V OL IO L (mA) 20 I OH - V OH IO H (mA) V D D =3.0V T A =25 °C -8 15 -6 10 -4 5 -2 0 0.5 1.0 1.5 2.0 VO L (V) 0 V D D =3.0V T A =25 °C 0.5 1.0 1.5 2.0 V D D -V O H (V) 17 GMS81604/08 LG Semicon MEMORY ORGANIZATION The GMS81604 has separate address spaces for Program and Data Memory. Program memory can only be read, not written to. It can be up to 4K (8K for GMS81608) bytes of Program Memory. Data memory can be read and written to up to 256 bytes including the stack area. Registers This device has six registers that are the Program Counter (PC), a Accumulator (A), two Index registers (X,Y), the Stack Pointer (SP) and the Program Status Word (PSW). The Program Counter consists of 16-bit register. A ACCUMULATOR X X REGISTER Y Y REGISTER The index registers also have increment, decrement, compare and data transfer functions and they can be used as simple accumulators. Stack Pointer : The stack pointer is an 8-bit register used for occurrence interrupts and calling out subroutines. The stack can be located at any position within 100 H to 13F H of the internal data memory. Data store and restore sequence to(from) stack area is shown in Figure 0. Caution: The stack pointer must be initialized by software because its value is undefined after reset. Ex) LDX #03FH TXSP ; SP ← 3F H Stack Address (100 H ~13F H ) 15 SP 8 1 7 0 SP STACK POINTER Hardware fixed. PCH PCL PROGRAM COUNTER PSW PROGRAM STATUS WORD Figure 3. Configuration of Registers Accumulator : The accumulator is the 8-bit general purpose register, used for data operation such as transfer, temporary saving and conditional judgment, etc. The accumulator can be used as a 16-bit register with Y register as shown below. Y Y A Figure 5. Stack Pointer Program Counter: The program counter is a 16-bit wide which consists of two 8-bit registers, PCH, PCL. This counter indicates the address of the next instruction to be executed. In reset state, the program counter has reset routine address (PCH: FF H , PCL: FE H ). . Program Status Word : The Program Status Word (PSW) contains several status bits that reflect the current state of the CPU. The PSW shown in Figure 6. It contains the Negative flag, the Overflow flag, the Direct page flag, the Break flag, the Half Carry (for BCD operations), the Interrupt enable flag, the Zero flag and the Carry bit. A TWO 8-BIT REGISTERS ONE "YA" 16-BIT REGISTER Figure 4. Configuration of YA 16-bit register X register, Y register : In the addressing modes which use these index registers, the register contents are added to the specified address and this becomes the actual address. These modes are extremely effective for referencing subroutine tables and memory tables. 18 [Carry flag C] This flag stores any carry or borrow from the ALU of CPU after an arithmetic operation and is also changed by the Shift instruction or rotate instruction. [Zero flag Z] This flag is set when the result of an arithmetic operation or data transfer is "0" and is cleared by any other result. [Interrupt disable flag I] This flag enables/disables all interrupts except interrupt caused by Reset or software LG Semicon GMS81604/08 MSB PSW N LSB V G B H I Z RESET VALUE: 00H C NEGATIVE FLAG CARRY FLAG RECEIVES CARRY OUT OVERFLOW FLAG ZERO FLAG G FLAG TO SELECT DIRECT PAGE INTERRUPT ENABLE FLAG BRK FLAG HALF CARRY FLAG RECEIVES CARRY OUT FROM BIT 1 OF ADDITION OPERANDS Figure 6. PSW (Program Status Word) Register BRK instruction. All interrupts are disabled when cleared to "0". This flag immediately becomes "0" when an interrupt is served. It is set by the EI instruction, cleared by the DI instruction. [Half carry flag H] After operation, set when there is a carry from bit 3 of ALU or there is not a borrow from bit 4 of ALU. This bit can not be set or cleared except CLRV instruction, clearing with Overflow flag (V). [Break flag B] This flag set by software BRK instruction to distinguish BRK from TCALL instruction which as the same vector address. [Direct page flag G] This flag assign direct page for direct addressing mode. In the direct addressing mode, addressing area is 1) INTERRUPT 2) RETI within zero page 00 H to FF H when this flag is "0". If it is set to "1", addressing area is 100 H to 1FF H . It is set by SETG instruction, and cleared by CLRG. [Overflow flag V] This flag is set to "1" when an overflow occurs in the result of an arithmetic operation involving signs. An overflow occurs when the result of an addition or subtraction exceeds +127(7F H ) or -128(80 H ). The CLRV instruction clears the overflow flag. There is no set instruction. When the BIT instruction is executed, for other than the above, bit 6 of memory is copy to this flag. [Negative flag N] This flag is set to match the sign bit (bit 7) status of the result of a data or arithmetic operation. When the BIT instruction is executed, bit 7 of memory is copy to this flag. 3) CALL 4) RET 5) PUSH A (X,Y,PSW) M(SP) ← (PCH) SP ← SP + 1 M(SP) ← (PCH) SP ← SP + 1 M(SP) ← ACC. SP ← SP - 1 (PSW) ← M(SP) SP ← SP - 1 (PCL) ← M(SP) SP ← SP - 1 M(SP) ← (PCL) SP ← SP + 1 M(SP) ← (PCL) SP ← SP + 1 6) POP A (X,Y,PSW) SP ← SP - 1 (PCL) ← M(SP) M(SP) ← (PSW) SP ← SP + 1 SP ← SP - 1 (PCH) ← M(SP) SP ← SP - 1 (PCH) ← M(SP) SP ← SP + 1 M(SP) ← (PCH) Figure 7. Stack Operation 19 GMS81604/08 LG Semicon Program Memory Address A 16-bit program counter is capable of addressing up to 64K bytes, but this devices have 4K bytes (8K for GMS81608) program memory space only the physically implemented. Accessing a location above FFFF H will cause a wrap-around to 0000 H . Figure 8, shows a map of the upper part of the Program Memory. After reset, the CPU begins execution from reset vector which is stored in address FFFE H , FFFF H . As shown in Figure 8, each area is assigned a fixed location in Program Memory. Program Memory area contains the user program, Page Call (PCALL) area contains subroutine program, to reduce program byte length because of using by 2 bytes PCALL instead of 3 bytes CALL instruction. If it is frequently called, more useful to save program byte length. E000H F000H FEFFH FF00H FFBFH FFC0H FFDFH FFE0H FFFFH PROGRAM MEMORY GMS81608 PCALL AREA GMS81604 TCALL AREA INTERRUPT VECTOR AREA Figure 8. Program Memory Table Call (TCALL) causes the CPU to jump to each TCALL address, where it commences execution of the service routine. The Table Call service locations are spaced at 2-byte interval : FFC0 H for TCALL15, FFC2 H for TCALL14, etc. 20 FFC0H FFC2H FFC4H FFC6H FFC8H FFCAH FFCCH FFCEH FFD0H FFD2H FFD4H FFD6H FFD8H FFDAH FFDCH FFDEH TCALL Name TCALL15 TCALL14 TCALL13 TCALL12 TCALL11 TCALL10 TCALL9 TCALL8 TCALL7 TCALL6 TCALL5 TCALL4 TCALL3 TCALL2 TCALL1 TCALL0/ BRK 1) 1) The BRK software interrupt is using same address with TCALL0. The interrupt causes the CPU to jump to specific location, where it commences execution of the service routine. The External interrupt 0, for example, is assigned to location FFFA H . The interrupt service locations are spaced at 2-byte interval : FFF8 H for External Interrupt 1, FFFA H for External Interrupt 0, etc. Any area from FF00 H to FFFF H , if it not going to be used, its service location is available as general purpose Program Memory. Address FFE0H FFE2H FFE4H FFE6H FFE8H FFEAH FFECH FFEEH FFF0H FFF2H FFF4H FFF6H FFF8H FFFAH FFFCH FFFEH Vector Name Basic Interval Timer Watch Dog Timer Analog to Digital Converter Timer/ Counter 3 Timer/ Counter 2 Timer/ Counter 1 Timer/ Counter 0 External Interrupt 3 External Interrupt 2 External Interrupt 1 External Interrupt 0 RESET LG Semicon GMS81604/08 Data Memory Figure 9 shows the internal Data Memory space available. Data Memory are divided into three groups, a user RAM, control registers and Stack. Address 00 H DATA MEMORY (RAM) BF H C0 H FF H 100 H Caution: Write only registers can not be accessed by bit manipulation instruction. 256 BYTES CONTROL REGISTERS STACK AREA 13F H Figure 9. Data Memory Internal Data Memory addresses are always one byte wide, which implies an address space of 256 bytes including the stack area. To access above FF H , G-flag should be set to "1" before, because after MCU reset, G-flag is "0". The stack pointer should be initialized within 00 H to 3F H by software because of implemented area of internal data memory. The control registers are used by the CPU and Peripheral functions for controlling the desired operation of the device. Therefore these registers contain control and status bits for the interrupt system, the timer/ counters, analog to digital converters, I/O ports. The control registers are in address C0 H to FF H . Note that unoccupied addresses may not be implemented on the chip. Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect. More detail informations of each register are explained in each peripheral sections. C0 H C1 H C2 H C3 H C8 H C9 H CA H CB H CCH CDH D0 H D1 H D3 H 2) D3 H 2) E0 H E2 H E3 H E4 H E5 H E6 H E7 H E8 H E9 H EC H ED H F4 H F5 H F6 H F7 H F8 H Symbol R0 R0DD R1 R1DD R4 R4DD R5 R5DD R6 R6DD PMR4 PMR5 BITR CKCTLR WDTR TM0 TM2 + + + + Note Note Note Note 3 3 3 3 ADCM ADR BUR PFDR IENL IRQL IENH IRQH IEDS R/W Power-on Reset Value R/W W 1) R/W W 1) R/W W 1) R/W W 1) R/W W 1) W 1) W 1) R W 1) W 1) R/W R/W R/W R/W R/W R/W R/W 4) R W 1) R/W R/W R/W R/W R/W W 1) X 00000000 X 00000000 X 00000000 X --0---00 X 00000000 00000000 --0----00000000 --010111 -0111111 00000000 00000000 X X X X --000001 X X -----100 000----000----00000000 00000000 00000000 Legend - = Unimplemented locations. X= Undefined value. NOTES: 1) The all write only registers can not be accessed by bit manipulation instruction. 2) The register BITR and CKCTLR are located at same address. Address D3H is read as BITR, as written to CKCTLR. 3) Several names are given at same address. Refer to below table. When read Address E4H E5H E6H E7H When write Timer mode Capture Mode T0 T1 T2 T3 CDR0 CDR1 CDR2 CDR3 TDR0 TDR1 TDR2 TDR3 4) Only bit 0 of ADCM can be read. 21 GMS81604/08 LG Semicon Control Registers for the GMS81604/08 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 C0H R0 R0 port data register C1H R0DD R0 port direction register C2H R1 R1 port data register C3H R1DD R1 port direction register C8H R4 R4 port data register C9H R4DD R4 port direction register CA H R5 R5 port data register CB H R5DD R5 port direction register CCH R6 R6 port data register CDH R6DD R6 port direction register D0H PMR4 D1H PMR5 D 3 H 1) BITR D 3 H 1) CKCTLR - - E0 H WDTR - WDTCL E2 H TM0 CAP0 T1ST T1SL1 T1SL0 T0ST T0CN T0SL1 T0SL0 E3 H TM2 CAP2 T3ST T3SL1 T3SL0 T2ST T2CN T2SL1 T2SL0 E4 H T0/ TDR0/ CDR0 Timer 0 register/ Timer data register 0/ Capture data register 0 E5 H T1/ TDR1/ CDR1 Timer 1 register/ Timer data register 1/ Capture data register 1 E6 H T2/ TDR2/ CDR2 Timer 2 register/ Timer data register 2/ Capture data register 2 E7 H T3/ TDR3/ CDR3 Timer 3 register/ Timer data register 3/ Capture data register 3 E8 H ADCM E9 H ADR EC H BUR ED H 2) PFDR F4 H IENL AE F5 H IRQL AIF F6 H IENH INT0E F7 H IRQH F8 H IEDS T3S T1S EC2S EC0S INT3S INT2S INT1S INT0S - - BUZS - - - - - ENPCK BTCL BTS2 BTS1 BTS0 Basic Interval Timer data register - - WDTON 6-bit Watch Dog Counter register ADEN ADS2 ADS1 ADS0 ADST ADSF ADC result data register BUCK1 BUCK0 BU5 BU4 BU3 BU2 BU1 BU0 - - - - - PFD PFR PFS WDTE BITE - - - - - WDTIF BITIF - - - - - INT1E INT2E INT3E T0E T1E T2E T3E INT0IF INT1IF INT2IF INT3IF T0IF T1IF T2IF T3IF IED3H IED3L IED2H IED2L IED1H IED1L IED0H IED0L Legend - = Unimplemented locations. NOTES: 1) The register BITR and CKCTLR are located at same address. Address D3 H is read as BITR, written to CKCTLR. 2) The register PFDR only be implemented on device, not on In-circuit Emulator. 22 LG Semicon GMS81604/08 I/O PORTS R1 and R1DD registers: R1 is an 8-bit bidirectional I/O port (address C2 H ). Each pin is individually configurable as input and output through the R1DD register (address C3 H ). The GMS81604/08 have five ports, R0, R1, R4, R5, R6. These ports pins may be multiplexed with an alternate function for the peripheral features on the device. In general, when a initial reset state, all ports are used as a general purpose input port. All pins have data direction registers which can configure these pins as output or input. A "1" in the port direction register configures the corresponding port pin as output. Conversely, write "0" to the corresponding bit to specify as an input pin. For example, to use the even numbered bit of R1 as output ports and the odd numbered bits as input ports, write "55 H " to address C1 H (R0 direction register) during initial setting as shown in Figure 10. R1 R17 R16 R15 R14 R13 R12 R11 R10 Input/ Output data 0 R0 DATA C1H R0 DIRECTION C2H R1 DATA C3H R1 DIRECTION 1 0 7 6 5 I O I 7 6 5 1 0 1 0 4 3 2 1 O I O I 4 3 2 1 R1DD R17 R16 R15 R14 R13 R12 R11 R10 Direction select 0: Input 1: Output 1 0 BIT O 0 PORT I: INPUT PORT O: OUTPUT PORT Figure 10. Example port I/O assignment Reading data register reads the status of the pins whereas writing to it will write to the port latch. R0 and R0DD registers: R0 is a 8-bit bidirectional I/O port (address C0 H ). Each pin is individually configurable as input and output through the R0DD register (address C1 H ). Port 0 Data Register R0 ADDRESS: C0 H RESET VALUE: Undefined R07 R06 R05 R04 R03 R02 R01 R00 Input/ Output data Port 0 Direction Register R0DD ADDRESS: C1 H RESET VALUE: 00000000 R07 R06 R05 R04 R03 R02 R01 R00 ADDRESS: C3 H RESET VALUE: 00000000 Port 1 Direction Register WRITE "55 H " TO PORT R0 DIRECTION REGISTER C0H ADDRESS: C2 H RESET VALUE: Undefined Port 1 Data Register R4 and R4DD registers: R4 is an 8-bit bidirectional I/O port (address C8 H ). Each pin is individually configurable as input and output through the R4DD register (address C9 H ). In addition, Port R4 is multiplexed with various special features. The control register PMR4 (address D0 H ) controls to select alternate function. After reset, this value is "0", port may be used as general I/O ports. To select alternate function such as External interrupt or External counter or Timer clock out, write "1" to the corresponding bit of PMR4. Port Pin Alternate Function R40 R41 R42 R43 INT0 INT1 INT2 INT3 R44 EC0 (External Count Input to Timer/ Counter 0) EC2 (External Count Input to Timer/ Counter 2) R45 R46 R47 (External (External (External (External Interrupt Interrupt Interrupt Interrupt 0) 1) 2) 3) T1O (Timer 1 Clock-Out) T3O (Timer 3 Clock-Out) Regardless of the direction register R4DD, PMR4 is selected to use as alternate functions, port pin can be used as a corresponding alternate features. Direction select 0: Input 1: Output 23 GMS81604/08 LG Semicon ADDRESS: C8 H RESET VALUE: Undefined Port 4 Data Register R4 R47 R46 R45 R44 R43 R42 R41 R40 Input/ Output data Port 4 Direction Register R4DD ADDRESS: C9 H RESET VALUE: 00000000 R47 R46 R45 R44 R43 R42 R41 R40 R5 and R5DD registers: R5 is a 3-bit bidirectional I/O port (address CA H ). R50, R51 and R55 only are physically implemented on this device. R50, R51 have internal pullups which is activated on input but deactivated on output. As input, these pins that are externally pull low will source current (I P2 on the DC characteristics) because of the internal pullups. Caution: Pins R50, R51 are present on 42SDIP, 44PLCC package only, but not on 40DIP . Refer to Pin assignment. Each pin is individually configurable as input and output through the R5DD register (address CB H ). Direction select 0: Input 1: Output Port Pin Alternate Function R55 PMR4 T3S T1S EC2S EC0S INT3S INT2S INT1S INT0S 0: R40 1: INT0 0: R44 1: EC0 The control register PMR5 (address D1 H ) controls the selection alternate function. After reset, this value is "0", port may be used as general I/O ports. To use buzzer function, write "1" to the PMR5. 0: R41 1: INT1 0: R45 1: EC2 ADDRESS: CA H RESET VALUE: Undefined Port 5 Data Register 0: R46 1: T1O 0: R47 1: T3O BUZ (Square-wave output for Buzzer driving) ADDRESS: D0 H RESET VALUE: 00000000 Port 4 Mode Register 0: R42 1: INT2 R5 - - R55 - - - R51 R50 0: R43 1: INT3 Input/ Output data Edge Selection Register IEDS ADDRESS: F8 H RESET VALUE: 00000000 MSB LSB INT3 INT2 INT1 ADDRESS: CB H RESET VALUE: --0---00 Port 5 Direction Register R5DD - - R55 - - - R51 R50 INT0 Direction select 0: Input 1: Output External Interrupt Edge select 00: Reserved 01: Falling (1-to-0 transition) 10: Rising (0-to-1 transition) 11: Both (Rising & Falling) ADDRESS: D1 H RESET VALUE: --0----- Port 5 Mode Register PMR5 - - BUZS - - - - - 0: R55 1: BUZ (Buzzer Port) 24 LG Semicon GMS81604/08 R6 and R6DD registers: R6 is an 8-bit port (address CCH). Pins R64~R67 are individually configurable as input and output through the R6DD register (address CDH), but pins R60~R63 are input only. Port Pin R60 R61 R62 R63 R64 R65 R66 R67 Port 6 Data Register R6 ADDRESS: CCH RESET VALUE: Undefined R67 R66 R65 R64 R63 R62 R61 R60 Alternate Function AN0 (ADC input 0) AN1 (ADC input 1) AN2 (ADC input 2) AN3 (ADC input 3) AN4 (ADC input 4) AN5 (ADC input 5) AN6 (ADC input 6) AN7 (ADC input 7) R6DD (address CDH) controls the direction of the R6 pins, even when they are being used as analog inputs. The user must make sure to keep the pins configured as inputs when using them as analog inputs. Input/ Output data Port 6 Direction Register R6DD ADDRESS: CDH RESET VALUE: 0000---- R67 R66 R65 R64 R63 R62 R61 R60 Fixed as Input. Can not write. Direction select 0: Input 1: Output On the initial RESET, R60 can not be used digital input port, because this port is selected as an analog input port by ADCM register. To use this port as a digital I/O port, change the value of lower 4 bits of ADCM (address 0E8H). On the other hand, R6 port, all eight pins can not be used as digital I/O port simultaneousely. At least one pin is used as an analog input. 25 GMS81604/08 LG Semicon Basic interval timer. BASIC INTERVAL TIMER The GMS81604 has one 8-bit Basic Interval Timer that is free-run, can not stop. Block diagram is shown in Figure 11. The 8-bit Basic interval timer register (BITR) is incremented every internal count pulse which is divided by prescaler. Since prescaler has divided ratio by 16 to 2048, the count rate is 1/16 to 1/2048 of the oscillator frequency. As the count overflows from FF H to 00 H , this overflow causes to generate the Basic interval timer interrupt. The BITR is interrupt request flag of BTS[2:0] X IN PIN 8 When write "1" to bit BTCL of CKCTLR, data register is cleared to "0" and restart to count-up. It becomes "0" after one machine cycle by hardware. BTCL CLEAR 3 ÷16 ÷32 ÷64 ÷128 ÷256 ÷512 ÷1024 ÷2048 Caution: All control bits of Basic interval timer are in CKCTLR register which is located at same address of BITR (address D3 H ). Address D3 H is read as BITR, written to CKCTLR. MUX BITR (8 BITS) BASIC INTERVAL TIMER INTERRUPT BITIF PRESCALER Figure 11. Block Diagram of The Basic Interval Timer CKCTLR Symbol - - W D T O N ENPCK Position BTCL BTS2 BTS1 BTS0 Name and Significance WDTON CKCTLR.5 WDTON=1, enables Watch Dog Timer operation, WDTON=0, operates as a 6-bit timer ENPCK CKCTLR.4 Enable Peripheral clock. BTCL CKCTLR.3 BTCL is set to "1", BITR is cleared. BTCL becomes "0" automatically after one machine cycle, and starts counting. BASIC INTERVAL TIMER CLOCK SELECTION BTS2 BTS1 BTS0 Prescale value 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 16 32 64 128 256 512 1024 2048 Figure 12. CKCTLR: Control Clock Register 26 ADDRESS: D3 H RESET VALUE: --010111 LG Semicon GMS81604/08 TIMER/COUNTER The GMS81604 has four Timer/Counter registers. Each module can generate an interrupt to indicate that an event has occurred (i.e. timer match). Timer 0 and Timer 1 are can be used either the two 8-bit Timer/Counter or one 16-bit Timer/Counter to combine them. Also Timer 2 and Timer 3 are same. "16-bit timer/counter", "8-bit capture", "16-bit capture" which are selected by bit in Timer mode register TM0 and TM2 as shown in right Table. In operation of Timer 2, Timer 3, their operations are same with Timer 0, Timer 1, respectively. TM0 FOR TIMER 0, TIMER 1 CAP0 T1SL1 T1SL0 0 0 0 16-bit Timer/Counter In the "timer" function, the register is incremented every internal clock input. Thus, one can think of it as counting internal clock input. Since a least clock consists of 4 and most clock consists of 64 oscillator periods, the count rate is 1/4 to 1/64 of the oscillator frequency. In the "counter" function, the register is incremented in response to a 1-to-0 (falling edge) transition at its corresponding external input pin, EC0 or EC2. Timer 0 Timer 1 1 0 0 16-bit Capture 0 X X 8-bit Timer 8-bit Timer 1 X X 8-bit Capture 8-bit Timer TM2 FOR TIMER 2, TIMER 3 CAP2 T3SL1 T3SL0 0 0 0 16-bit Timer/Counter In addition the "capture" function, the register is incremented in response external or internal clock sources same with timer or counter function. When external clock edge input, the count register is captured into Timer data register correspondingly. Timer 2 Timer 3 1 0 0 16-bit Capture 0 X X 8-bit Timer 8-bit Timer 1 X X 8-bit Capture 8-bit Timer It has four operating modes: "8-bit timer/counter", MSB TM0 CAP0 TM2 is in Figure 14. LSB T1ST T1SL1 T1SL0 T0ST T0CN TIMER 1 T0SL1 T0SL0 ADDRESS: E2 H RESET VALUE: 00H TIMER 0 CAP0 Capture mode selection flag, When set, timer operate as one 16-bit capture timer combine two 8-bit timers. T0ST When set, The Timer 0 Count Register is cleared and start again. When cleared, stop the counting. T1ST When set, Timer 1 count register is cleared and start again. When cleared, stop the counting. T0CN Start/Stop control for Timer 0. A logic 1 starts the timer. TIMER 1 TIMER 0 T1SL1 T1SL0 0 0 1 1 0 1 0 1 INPUT CLOCK 16-BIT TIMER MODE (NOTE 1) 8-BIT TIMER, ÷ 4 ← PRESCALER 8-BIT TIMER, ÷ 16 8-BIT TIMER, ÷ 64 T0SL1 T0SL0 0 0 1 1 0 1 0 1 INPUT CLOCK Timer or Counter select ÷ 4 ← PRESCALER ÷ 16 ÷ 64 NOTE: If this mode selected, the Timer 0 are used as a 16-bit timer mode. The Timer 1 is engaged to the Timer 0. The source clock is selected by bits T0SL1 and T0SL0. Figure 13. TM0: Timer 0, Timer 1 Mode Register 27 GMS81604/08 LG Semicon MSB TM2 CAP2 LSB T3ST T3SL1 T3SL0 T2ST T2CN TIMER 3 T2SL1 T2SL0 ADDRESS: E3 H RESET VALUE: 00 H TIMER 2 CAP2 Capture mode selection flag, When set, timer operate as one 16-bit timer combine two 8-bit timers. See Figure 21 and Figure 22. T2ST When set, Timer 2 count register is cleared and start again. When cleared, stop the counting. T3ST When set, Timer 3 count register is cleared and start again. When cleared, stop the counting. T2CN Start/Stop control for Timer 2. A logic 1 starts the timer. TIMER 3 TIMER 2 T3SL1 T3SL0 0 0 1 1 0 1 0 1 INPUT CLOCK 16-BIT TIMER MODE (NOTE 1) 8-BIT TIMER, ÷ 4 ←PRESCALER 8-BIT TIMER, ÷ 16 8-BIT TIMER, ÷ 64 T2SL1 T2SL0 0 0 1 1 0 1 0 1 INPUT CLOCK Timer or Counter select ÷ 4 ← PRESCALER ÷ 16 ÷ 64 NOTE: If this mode selected, the Timer 2 and Timer 3 are used as a 16-bit timer mode. The Timer 3 is engaged to the Timer 2. The source clock is selected by bits T2SL1 and T2SL0. Figure 14. TM2: Timer 2, Timer 3 Mode Register MSB LSB ADDRESS: E4 H RESET VALUE: 00 H ADDRESS: E5 H RESET VALUE: 00 H TDR0 TDR1 TDR2 TDR3 ADDRESS: E6 H RESET VALUE: 00 H ADDRESS: E7 H RESET VALUE: 00 H Figure 15. TDRx : Timer x Data Register 28 LG Semicon GMS81604/08 8-bit Timer/Counter Mode The GMS81604 has four 8-bit Timer/Counters, Timer 0, Timer 1, Timer 2, Timer 3. The Timer 0, Timer 1 only as shown in Figure 16. because other timer/counters are same with Timer 0 and Timer 1. The "timer" or "counter" function is selected by control registers TM0, TM2 as shown in Figure 13 and Figure 14. To use as an 8-bit timer/counter mode, bit CAP0 of TM0 is cleared to "0" and bits T1SL1, T1SL0 of TM0 or bits T3SL1, T3SL0 of TM2 should not set to zero (Figure 16). These timers have each 8-bit count register and data register. The count register is incremented by every internal or external clock input. The internal clock has a prescaler divide ratio option of 4, 16, 64 (selected by control bits TxSL1, TxSL0 of register TMx). until it matches TDR0 and then reset to 00 H . The match output of Timer 0 generates Timer 0 interrupt (latched in T0IF bit) As TDRx and Tx register are in same address, when reading it as a Tx, written to TDRx. Caution: The contents of Timer data register TDRx should be initialized 1 H ~ F F H except 0 H , because it is undefined after reset. In counter function, the counter is incremented every 1-to 0 (falling edge) transition of EC0 or EC2 pin. In order to use counter function, the bit EC0S, EC2S of the Port mode register PMR4 are set to "1". The Timer 0 can be used as a counter by pin EC0 input, but Timer 1 can not. Similarly, Timer 2 can be used by pin EC2 input but Timer 3 can not. In the Timer 0, timer register T0 increments from 00 H MSB TM0 LSB CAP0 T1ST T1SL1 T1SL0 T0ST T0CN T0SL1 0 X ≠0 ≠0 X X X ADDRESS: E2 H T0SL0 RESET VALUE: 00 H X T0ST T0SL[1:0] 0: Stop 1: Clear and Start EDGE DETECTOR 0 EC0 PIN T0 (8-BITS) CLEAR 1 X IN PIN ÷4 ÷ 16 ÷ 64 MUX T0CN T0IF PRESCALER TIMER 0 INTERRUPT COMPARATOR TIMER 0 TDR0 (8-BITS) T1SL[1:0] T1ST 0: Stop 1: Clear and Start MUX T1 (8-BITS) CLEAR T1IF TIMER 1 TIMER 1 INTERRUPT COMPARATOR TDR1 (8-BITS) F/F T1O PIN Figure 16. 8-bit Timer/Counter Mode 29 GMS81604/08 LG Semicon To pulse out, the timer match can goes to port pin as shown in Figure 16. Thus, pulse out is generated by the timer match. These operation is implemented to pin, T1O and T3O. The pin T1O is output from Timer 1, the T3O is from Timer 3. Operation of T3O is omitted in this document, but still presents and same architecture with T1O. f T x O (H z ) = MSB PMR4 O s c i l l a t o rFrequency 2 ⋅ Prescaler ⋅ T D R LSB T3S T1S EC2S EC0S INT3S INT2S INT1S ADDRESS: D0 H RESET VALUE: 00 H INT0S T3S 0: R47 1: T3O (TIMER 3 OUTPUT) INT3S 0: R43 1: INT3 (EXTERNAL INTERRUPT 3) T1S 0: R46 1: T1O (TIMER 1 OUTPUT) INT2S 0: R42 1: INT2 (EXTERNAL INTERRUPT 2) EC2S 0: R45 1: EC2 ( E X T E R N A L I N P U T P I N F O R TIMER 2 INT1S 0: R41 1: INT1 (EXTERNAL INTERRUPT 1) EC0S 0: R44 1: EC0 ( E X T E R N A L I N P U T P I N F O R TIMER 0 INT0S 0: R40 1: INT0 (EXTERNAL INTERRUPT 0) Figure 17. PMR4: R4 Port Mode Register EX) When TM0: 00110111 (PRESCALER= 16) TDR0: F9 H = 249 D OSCILLATOR FREQ.= 4MHz INTERRUPT PERIOD = 1 4 × 10 6 H z × 16 × (249 + 1 ) = 1ms COUNT PULSE PERIOD MATCH (TDR0 = T0) F9 F8 F7 F6 F5 F4 F3 F2 F1 F0 TDR0 4 us 3 2 1 00 H CLEAR TIMER 0 INTERRUPT CLEAR OCCUR INTERRUPT OCCUR INTERRUPT INTERRUPT PERIOD Figure 18. Timer Count Example 30 CLEAR OCCUR INTERRUPT TIME LG Semicon GMS81604/08 Even if the Timer 0 (including the Timer 1) is used as a 16-bit timer, the Timer 2 and Timer 3 can still be used as either two 8-bit timer or one 16-bit timer by setting the TM2. Reversely, even if the Timer 2 (including the Timer 3) is used as a 16-bit timer, the Timer 0 and Timer 1 can still be used as 8-bit timer independently. 16-bit Timer/Counter Mode The Timer register is being run with all 16 bits. A 16-bit timer/counter register T0, T1 are incremented from 0000 H until it matches TDR0, TDR1 and then resets to 0000 H . The match output generates Timer 0 interrupt. The clock source of the Timer 0 is selected either internal or external clock by bit T0SL1, T0SL0. MSB TM0 LSB CAP0 T1ST 0 X T1SL1 T1SL0 T0ST T0CN T0SL1 T0SL0 X X X X 0 0 DO NOT CARE T0ST T0SL[1:0] 0: Stop 1: Clear and Start EDGE DETECTOR 0 T1 (8-BITS) EC0 PIN ÷4 ÷ 16 ÷ 64 XIN PIN ADDRESS: E2 H RESET VALUE: 00 H 1 MUX T0 (8-BITS) CLEAR T0CN T0IF PRESCALER TIMER 0 COMPARATOR (+TIMER1) THIS FIGURE IS A EXAMPLE OF THE TIMER 0 AND TIMER 1. IN THE TIMER 2, EACH REGISTERS AND FLAGS MAY BE CHANGED CORRESPONDINGLY. TDR1 (8-BITS) TDR0 (8-BITS) HIGHER LOWER TIMER 0 INTERRUPT (NOT TIMER 1 INTERRUPT) Figure 19. 16-bit Timer/Counter Mode MATCH TDR0 MATCH Restart Stop Stop Clear and Start Count Up 00 H CLEAR TIMER INTERRUPT OCCUR INTERRUPT CLEAR CLEAR TIME OCCUR INTERRUPT HIGH TxST LOW HIGH TxCN LOW Figure 20. Timer Count Operation 31 GMS81604/08 LG Semicon input INTx pin causes the current value in the Timer x register (T0,T2), to be captured into registers CDRx (CDR0, CDR2), respectively. After captured, Timer x register is cleared and restarts by hardware. 8-bit Capture Mode The Timer 0 capture mode is set by bit CAP0 of timer mode register TM0 (bit CAP2 of timer mode register TM2 for Timer 2) as shown in Figure 21. In this mode, Timer 1 still operates as an 8-bit timer/counter. Caution: The CDRx and TDRx are in same address. In the capture mode, reading operation is read the CDRx, not TDRx because path is opened to the CDRx. As mentioned above, not only Timer 0 but Timer 2 can also be used as a capture mode. In 8-bit capture mode, Timer 1 and Timer 3 are can not be used as a capture mode. It has three transition modes: "falling edge", "rising edge", "both edge" which are selected by interrupt edge selection register IEDS (Refer to External interrupt section). In addition, the transition at INTx pin generate an interrupt. The Timer/Counter register is incremented in response internal or external input. This counting function is same with normal timer mode, but Timer interrupt is not generated. Timer/Counter still does the above, but with the added feature that a edge transition at external MSB LSB TM0 CAP0 T1ST T1SL1 T1SL0 1 X ≠0 ≠0 T0ST T0CN T0SL1 X X X ADDRESS: E2 H T0SL0 RESET VALUE: 00 H X T0ST T0SL[1:0] 0: Stop 1: Clear and Start EDGE DETECTOR 0 EC0 PIN XIN PIN T0 (8-BITS) ÷4 ÷ 16 ÷ 64 MUX 1 T0CN CAPTURE THIS FIGURE IS A EXAMPLE OF THE TIMER 0. IN THE TIMER 2, EACH REGISTERS AND FLAGS MAY BE CHANGED CORRESPONDINGLY. PRESCALER IEDS[1:0] CDR0 (8-BITS) INT0 PIN INT0IF Figure 21. 8-bit Capture Mode 32 INT0 INTERRUPT LG Semicon GMS81604/08 16-bit Capture Mode 16-bit capture mode is the same as 8-bit capture, except that the Timer register is being run will 16 bits. MSB LSB TM0 CAP0 T1ST T1SL1 T1SL0 1 X 0 0 T0ST T0CN T0SL1 X X X ADDRESS: E2 H T0SL0 RESET VALUE: 00 H X DO NOT CARE T0ST 0: Stop 1: Clear and Start T0SL[1:0] EDGE DETECTOR 0 EC0 PIN XIN PIN ÷4 ÷ 16 ÷ 64 1 MUX T1 (8-BITS) T0 (8-BITS) THIS FIGURE IS A EXAMPLE OF USING TIMER 0 AND TIMER 1. IN THE TIMER 2 AND TIMER 3 EACH REGISTERS AND FLAGS MAY BE CHANGED. T0CN PRESCALER IEDS[1:0] TIMER 0 + TIMER 1 CDR1 (8-BITS) CDR0 (8-BITS) HIGHER LOWER INT0 PIN INT0IF INT 0 INTERRUPT Figure 22. 16-bit Capture Mode 33 GMS81604/08 LG Semicon direction register. ANALOG TO DIGITAL CONVERTER The analog-to-digital converter (A/D) allows conversion of an analog input signal to a corresponding 8-bit digital value. The A/D module has eight analog inputs, which are multiplexed into one sample and hold. The output of the sample and hold is the input into the converter, which generates the result via successive approximation. The analog supply voltage is connected to AV D D of ladder resistance of A/D module. The A/D module has two registers which are the control register ADCM and A/D result register ADR. The register ADCM, shown in Figure 24, controls the operation of the A/D converter module. The port pins can be configured as analog inputs or digital I/O. To use analog inputs, I/O is selected input mode by R6DD How to Use A/D Converter The processing of conversion is start when the start bit ADST is set to "1". After one cycle, it is cleared by hardware. The register ADR contains the results of the A/D conversion. When the conversion is completed, the result is loaded into the ADR, the A/D conversion status bit ADSF is set to "1", and the A/D interrupt flag AIF is set. The block diagram of the A/D module is shown in Figure 23. The A/D status bit ADSF is set automatically when A/D conversion is completed, cleared when A/D conversion is in process. The conversion time takes maximum 40 uS (at f X I N =4 MHz). ADEN "0" LADDER RESISTOR DECODER AV D D PIN "1" 3 R60/AN0 R61/AN1 R62/AN2 R63/AN3 ADS[2:0] 000 001 010 011 V IN R64/AN4 R65/AN5 R66/AN6 100 S/H SUCCESSIVE APPROXIMATION CIRCUIT A/D INTERRUPT SAMPLE & HOLD 101 110 ADR R67/AN7 AIF 111 ADDRESS: E9 H RESET VALUE: Undefined A/D RESULT REGISTER INPUT CHANNEL SELECTION Figure 23. A/D Block Diagram 34 LG Semicon GMS81604/08 MSB ADCM - LSB - R/W R/W R/W R/W R/W R ADEN ADS2 ADS1 ADS0 ADST ADSF ADDRESS: E8 H RESET VALUE: --00001 A/D status bit 0: A/D conversion is in process. 1: A/D conversion is completed, not in process. RESERVED A/D start bit 1: Setting this bit starts an A/D conversion. After one cycle, bit is cleared to "0". 0: Bit force to zero. Analog channel select 000: channel 0 (R60/AN0) 001: channel 1 (R61/AN1) 010: channel 2 (R62/AN2) 011: channel 3 (R63/AN3) 100: channel 4 (R64/AN4) 101: channel 5 (R65/AN5) 110: channel 6 (R66/AN6) 111: channel 7 (R67/AN7) A/D converter Enable bit 0: A/D converter module shut off and consumes no operating current. 1: Enable A/D converter Figure 24. ADCM: A/D Converter Control Register 35 GMS81604/08 LG Semicon BUZZER FUNCTION The buzzer driver consists of 6-bit binary counter, the buzzer register BUR and the clock selector. It generates square-wave which is very wide range frequency (250 Hz~125 kHz at f XIN =4 MHz) by user programmable counter. X IN PIN ÷ 16 ÷ 32 ÷ 64 ÷ 128 COUNTER (6 BIT) PRESCALER F/F BUZ PIN Pin R55 is assigned for output port of Buzzer driver by setting the bit 5 of PMR5 (address D1 H ) to "1". At this time, the pin R55 must be defined as output mode (the bit 5 of R5DD=1) BUR[7:6] BUR[5:0] (6 BIT) BUR REGISTER Figure 25. Buzzer Driver The bit 0 to 5 of BUR determines output frequency for buzzer driving. Frequency calculation is following below. f BUZ (Hz ) = MUX The 6-bit buzzer counter is cleared and start the counting by writing signal to the register BUR. It is increment from 00 H until it matches 6-bit register BUR. fXIN 2 ⋅ Prescaler ratio ⋅ B U R value Caution: The register BUR contains undefined value after reset. It must be initialized none 0 H (1 H ~ 3 F H ). f BUZ : Buzzer frequency f XIN : Min oscillator frequency Prescaler: Prescaler divide ratio by BUCK1, BUCK0 BUR:Lower 6-bit of BUR. Buzzer period data value The bits BUCK1, BUCK0 of BUR selects the source clock from prescaler output. MSB BUR LSB BUCK1 BUCK0 BU5 BU4 BU3 BU2 BU1 BU0 ADDRESS: EC H RESET VALUE: Undefined Buzzer Period Data Buzzer Source Clock Selection 00: fX IN ÷ 16 01: fX IN ÷ 32 10: fX IN ÷ 64 11: fX IN ÷ 128 Figure 26. BUR: Buzzer Period Data Register MSB PMR5 - LSB - BUZS - - - - - R55/ BUZ Port Selection 0: R55 1: BUZ Figure 27. PMR5: Port 5 Mode Register 36 ADDRESS: D1 H RESET VALUE: --0----- LG Semicon GMS81604/08 INTERRUPTS The GMS81604/08 interrupt circuits consist of Interrupt enable register (IENH, IENL), Interrupt request flags of IRQH, IRQL, priority circuit and Master enable flag(I flag of PSW). The configuration of interrupt circuit is shown in Figure 28. 12 interrupt sources are provided including the Reset. Interrupt source Hardware RESET External Interrupt 0 External Interrupt 1 External Interrupt 2 External Interrupt 3 Timer/Counter 0 Timer/Counter 1 Timer/Counter 2 Timer/Counter 3 AD Converter Watch dog timer Basic interval timer Symbol Priority RST INT0IF INT1IF INT2IF INT3IF T0IF T1IF T2IF T3IF AIF WDTIF BITIF 1 2 3 4 5 6 7 8 9 10 11 12 *Vector addresses are shown in Program Memory section. INT0 INT1 INT1IF INT2 INT2IF INT3 INT3IF The Timer 0~Timer 3 Interrupts are generated by T0IF ~T3IF, which are set by a match in their respective timer/counter register. The AD converter Interrupt is generated by AIF which is set by finishing the analog to digital conversion. The Watch dog timer Interrupt is generated by WDTIF which set by a match in Watch dog timer register. The Basic Interval Timer Interrupt is generated by BITIF which are set by a overflow in the timer/counter register. The interrupts are controlled by the interrupt master enable flag I-flag (bit 2 of PSW), the interrupt enable register (IENH, IENL) and the interrupt request flags (in IRQH, IRQL) except Power-on reset and software BRK interrupt. Interrupt enable registers are shown in Figure 29. These registers are composed of interrupt enable flags of each interrupt source, these flags determines IENH IRQH INT0IF The External Interrupts INT0~INT3 can each be transition-activated, depending on interrupt edge selection register. I-flag is in PSW, it is cleared by "DI", set by "EI" instruction. When it goes interrupt service, I-flag is cleared by hardware, thus any other interrupt are inhibited. When interrupt service is completed by "RETI" instruction, I-flag is set to "1" by hardware. 0 1 MSB BRK (Software Interrupt) TIMER 0 T0IF TIMER 1 T1IF TIMER 2 T2IF TIMER 3 T3IF PRIORITY CONTROL 1 LSB IENL IRQL ADC AIF WDT WDTIF BASIC INTERVAL TIMER 0 BITIF RELEASE THE STOP (IF IN STOP MODE) TO CPU I-FLAG Master Enable Flag BIT 7 BIT 6 BIT 5 RESET Figure 28. Block Diagram of Interrupt Function 37 GMS81604/08 LG Semicon MSB IENH INT0E LSB INT1E INT2E INT3E T0E T1E T2E WDTE BITE - - - - MSB IENL AE ADDRESS: F6 H RESET VALUE: 00 H T3E LSB - ADDRESS: F4 H RESET VALUE: 000----- Enables or disables the interrupt individually. If flag is cleared, the interrupt is disabled. 0: Disable 1: Enable Figure 29. IENH, IENL: Interrupt Enable Registers whether an interrupt will be accepted or not. When enable flag is "0", a corresponding interrupt source is prohibited. Note that PSW contains also a master enable bit, I-flag, which disables all interrupts at once. When an interrupt is responded to, the I-flag is cleared to disable any further interrupt, the return address is pushed into the stack and the PC is vectored to. Once in the interrupt service routine the source(s) of the interrupt can be determined by polling the interrupt flag bits. The interrupt flag bit(s) must be cleared in software before reenabling interrupts to avoid recursive interrupts. The Interrupt Request flags are able to be read and write. External Interrupt External interrupt on INT0~INT3 pins are edge triggered depending the edge selection register IEDS. bit 0 to bit 3 of the port mode register PMR4. The PMR4 and IEDS registers are shown in Figure 32. EDGE DETECTOR IEDS[1:0] INT0 INT0IF INT0 INTERRUPT IEDS[3:2] INT1IF INT1 INT1 INTERRUPT IEDS[5:4] INT2IF INT2 INT2 INTERRUPT IEDS[7:6] INT3 INT3IF INT3 INTERRUPT The edge detection of external interrupt has three transition activated mode: rising edge, falling edge, both edge. INT0~INT3 are multiplexed with general I/O ports (R40~R43). To use external interrupt pin, set 38 Figure 30. External Interrupt LG Semicon GMS81604/08 MAX. 13 f O S C 8 fO S C f XIN INTERRUPT ACTIVE INTERRUPT PROCESSING INSTRUCTION EXECUTION (INTERRUPT HOLDING) INTERRUPT ROUTINE Figure 31. INT Pin Interrupt Timing MSB PMR4 LSB T3S T1S EC2S EC0S INT3S INT2S INT1S INT0S ADDRESS: D0 H RESET VALUE: 00 H Relation with External Interrupt function Relation with Timer/Counter Function T3S 0: R47 1: T3O (TIMER/COUNTER 3 OUTPUT) INT3S 0: R43 1: INT3 (EXTERNAL INTERRUPT 3) T1S 0: R46 1: T1O (TIMER/COUNTER 1 OUTPUT) INT2S 0: R42 1: INT2 (EXTERNAL INTERRUPT 2) EC2S 0: R45 1: EC2 (EXTERNAL INPUT PIN FOR TIMER/COUNTER 2 INT1S 0: R41 1: INT1 (EXTERNAL INTERRUPT 1) EC0S 0: R44 1: EC0 (EXTERNAL INPUT PIN FOR TIMER/COUNTER 0 INT0S 0: R40 1: INT0 (EXTERNAL INTERRUPT 0) MSB IEDS IED3H LSB IED3L INT3 IED2H IED2L INT2 IED1H IED1L INT1 IED0H IED0L ADDRESS: F8 H RESET VALUE: 00 H INT0 Edge selection register 00: Reserved 01: Falling (1-to-0 transition) 10: Rising (0-to-1 transition) 11: Both (Rising & Falling) Figure 32. PMR4 and IEDS Registers 39 GMS81604/08 LG Semicon BRK Interrupt Multiple Interrupt Software interrupt can be invoked by BRK instruction, which is the lowest priority order. If two requests of different priority levels are received simultaneously, the request of higher priority level is serviced. If requests of the same priority level are received simultaneously, an internal polling sequence determines by hardware which request is serviced. Hardware interrupt priority is shown in Page37. Interrupt vector address of BRK is shared with the vector of TCALL0 (Refer to Program Memory Section). When BRK interrupt is generated, B-flag of PSW is set to distinguish BRK from TCALL0. Each processing step is determined by B-flag as shown below. B-FLAG =0 In this example, the INT0 interrupt can be serviced without any pending, even TIMER 0 is in progress. Because of re-setting the interrupt enable registers IENH, IENL and master enable flag "EI" in the Timer/Counter 0 routine. =1 BRK or TCALL0 BRK INTERRUPT ROUTINE RETI However, multiple processing through software for special features is possible. Generally when an interrupt is accepted, the I-flag is cleared to disable any further interrupt. But as user set I-flag in interrupt routine, some further interrupt can be serviced even if certain interrupt is in progress. TCALL0 ROUTINE RET TIMER 0 ROUTINE MAIN ROUTINE INT 0 ROUTINE MOV IENH,#80H MOV IENL,#00H EI INT0 ROUTINE Occur TIMER 0 INTERRUPT Figure 33. Execution of BRK/ TCALL0 RETI MOV IENH,#FFH MOV IENL,#FFH RETI Figure 34. Execution of Multi-Interrupt 40 LG Semicon GMS81604/08 WATCHDOG TIMER The purpose of the watchdog timer is to detect the malfunction (runaway) of program due to external noise or other causes and return the operation to the normal condition. The watchdog timer consists of 6-bit binary counter, 6-bit comparator and the watchdog timer data register. When the value of 6-bit binary counter is equal to the lower 6 bits of WDTR, the match is generated to go to reset the CPU. Caution: Because the watchdog timer counter is enabled after clearing Basic Interval Timer . After the bit WDTON set to "1", maximum error of timer is depend on prescaler ratio of Basic Interval Timer. This watchdog timer can also be used as a simple 6-bit timer by interrupt WDTIF. The interval of watchdog timer interrupt is decided by Basic Interval Timer. Interval equation is as below. T W D T = WDTR ⋅ Interval of BIT The 6-bit binary counter is cleared by WDTCL=1. WDTCL WATCHDOG COUNTER (6-BITS) BASIC INTERVAL TIMER OVERFLOW COUNT SOURCE CLEAR NOTE: The bit WDTON is in register CKCTLR. See Figure 12. "0" "1" COMPARATOR TO RESET CPU WDTON WDTR[5:0] (6-BITS) WDTIF WATCH-DOG TIMER INTERRUPT WATCHDOG TIMER REGISTER Figure 35. Block Diagram of Watch-dog Timer MSB WDTR - LSB WDTCL Reserved 6-bit Watch-dog count register ADDRESS: EC H RESET VALUE: Undefined WDTCL 0: Free-run Watch-dog Timer 1: WDTCL is set to "1", Counter is cleared. WDTCL becomes "0" automatically after one machine cycle, and Counter starts counting. Figure 36. WDTR: Watch-dog Timer Data Register 41 GMS81604/08 LG Semicon STOP MODE restored to its normal operating level, and must be held active long enough to allow the oscillator to restart and stabilize (minimum 20 msec). For applications where power consumption is a critical factor, device provides reduced power of STOP. Caution: The NOP instruction have to be written more than two to next line of the STOP instruction. Ex) STOP NOP NOP An instruction that STOP causes that to be the last instruction executed before going into the Stop mode. In the Stop mode, the on-chip oscillator is stopped. With the clock frozen, all functions are stopped, but the on-chip RAM and Control registers are held. The port pins out the values held by their respective port data register Rx, port direction register RxDD. The status of peripherals during Stop mode is shown below. Release Stop Mode Peripheral Status RAM Retain Control registers Retain I/O Retain Oscillation Stop X IN Low X OUT High The exit from Stop mode is hardware reset or external interrupt. Reset redefines all the Control registers but does not change the on-chip RAM. External interrupts allow both on-chip RAM and Control registers to retain their values. If I-flag = 1, the normal interrupt response takes place. If I-flag = 0, the chip will resume execution starting with the instruction following the STOP instruction. It will not vector to interrupt service routine. In the Stop mode of operation, V D D can be reduced to minimize power consumption. Care must be taken, however, to ensure that V D D is not reduced before the Stop mode is invoked, and that V D D is restored to its normal operating level, before the Stop mode is terminated. The reset should not be activated before V D D is When exit from Stop mode by external interrupt from Stop mode, enough oscillation stabilization time is required to normal operation. Figure 37 shows the timing diagram. When release the Stop mode, the OSCILLATOR INTERNAL CLOCK EXTERNAL INTERRUPT BASIC INTERVAL TIMER COUNTER N N+1 N+2 STOP INSTRUCTION EXECUTION NORMAL OPERATION STOP MODE 00 01 FE FF 00 01 STABILIZATION TIME t ST > 20 ms Figure 37. Timing of Stop Release by External Interrupt 42 02 03 CLEAR BASIC INTERVAL TIMER NORMAL OPERATION LG Semicon GMS81604/08 Wake-up and Reset Function Table Chip Status before event Event Chip function after event PC Oscillator Circuit RESET Do not care Vector on STOP instruction Normal operation N+1 off External Interrupt Normal operation Vector on External Interrupt Wake-up Stop, I-flag = 1 Stop, I-flag = 0 Vector N+1 on on PC: Program Counter contents after the event. N: Address of STOP instruction. Basic interval timer is activated on wake-up. It is incremented from 00 H until FF H then 00 H . The count overflow is set to start normal operation. Therefore, before STOP instruction, user must be set its relevant prescaler divide ratio to have long enough time (more than 20msec). This guarantees that crystal oscillator has started and stabilized. By reset, exit from Stop mode is shown in Figure 38. M inimizing Current Consumption in Stop Mode The Stop mode is designed to reduce power consumption. To minimize current drawn during Stop mode, the user should turn-off output drivers that are sourcing or sinking current, if it is practical. Weak pull-ups on port pins should be turned off, if possible. All inputs should be either as V SS or at V D D (or as close to rail as possible). An intermediate voltage on an input pin causes the input buffer to draw a significant amount of current. STOP MODE OSCILLATOR INTERNAL CLOCK RESET STOP INSTRUCTION EXECUTION t ST = 64 ms at 8 MHz STABILIZATION TIME Time can not be control by software. Figure 38. Timing of Stop Mode Release by Reset 43 GMS81604/08 LG Semicon RESET Register The reset input is the RESET pin, which is the input to a Schmitt Trigger. A reset in accomplished by holding the RESET pin low for at least 8 oscillator periods, while the oscillator running. After reset, 64ms (at 8 MHz) plus 7 oscillator periods are required to start execution as shown in Figure 40. Internal RAM is not affected by reset. When V D D is turned on, the RAM content is indeterminate. Initial state of each register is as follow. Therefore, this RAM should be initialized before reading or testing it. EX) 5V OPERATION +5V 10K Ω RESET 7042 + 10uF 4.2V RESET IC Figure 39. Example of Reset circuit Content A X Y PSW PC SP X X X 00H X X R0 R0DD R1 R1DD R4 R4DD R5 R5DD R6 R6DD PMR4 PMR5 X 00000000 X 00000000 X 00000000 X --0---00 X 00000000 00000000 --0----- BITR CKCTLR WDTR TM0 TM2 TDR0/ T0/ TDR1/ T1/ TDR2/ T2/ TDR3/ T3/ 00H --010111 -0111111 00H 00H X X X X CDR0 CDR1 CDR2 CDR3 ADCM ADR BUR PFDR --000001 X X -----100 IENH IENL IRQH IRQL IEDS 00H 000----00H 000----00H - = unimplemented bit X= unknown 1 2 3 ? ? 4 5 6 7 FFFE FFFF OSCILLATOR RESET ADDRESS BUS DATA BUS ? ? tS T = 64 ms at 8 MHz ? ? ? ? FE RESET PROCESS STEP STABILIZATION TIME Figure 40. Timing Diagram after Reset 44 ADL Start ADH OP Code MAIN PROGRAM LG Semicon GMS81604/08 POWER FAIL PROCESSOR Caution: Power fail processor function is not available on 3V operation, because this function will detect power fail all the time. The GMS81604/08 have on-chip power fail detection circuitry to immunize against power noise. A configuration register, PFDR, can enable (if clear/programmed) or disable (if set) the Power-fail Detect circuitry. If V D D falls below 3.0~4.0V range for longer than 100 ns, the Power fail situation may reset MCU according to PFR bit of PFDR. PFDR - - - - - As below PFDR register is not implemented on the in-circuit emulator, user can not experiment with it. Therefore, after final development of user program, this function may be experimented. R/W R/W R/W PFD PFR PFS MSB ADDRESS: ED H RESET VALUE: -----100 LSB Power Fail Status 0: Normal operate 1: This bit force to "1" when Power fail was detected. Reserved Operation Mode 0: Normal operation regardless of power fail. 1: MCU will be reset during power fail. Disable flag 0: Power fail detection enable 1: Power fail detection disable Figure 41. PFDR: Power Fail Detector Register RESET VECTOR YES PFS = 1 ? NO PFS = 0 RAM CLEAR INITIALIZE RAM DATA INITIALIZE ALL PORTS INITIALIZE REGISTERS Skip the initial routine. FUNCTION EXECUTION Figure 42. Example S/W of Reset flow by Power Fail 45 GMS81604/08 LG Semicon VDD PFV D D MAX. PFV D D MIN. 64 mS Internal Reset VDD PFV D D MAX. PFV D D MIN. When PFR = 1 Internal Reset t < 64 mS 64 mS VDD Internal Reset PFV D D MAX. PFV D D MIN. 64 mS Figure 43. Power Fail Processor Situations 46 LG Semicon GMS81604/08 OSCILLATOR CIRCUIT X IN and X O U T are the input and output, respectively, of a inverting amplifier which can be configured for use as an on-chip oscillator, as shown in Figure 44. C1 V SS X IN X OUT X OUT C2 RESET X IN VS S R00 R01 Recommend: C1,C2 = 30 pF ± 10 pF for Crystals. Figure 46. Layout of Crystal Figure 44. Oscillator Connections To drive the device from an external clock source, X O U T should be left unconnected while X IN is driven as shown in Figure 45. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum high and low times specified on the data sheet must be observed. N/C EXTERNAL OSCILLATOR SIGNAL Oscillation circuit is designed to be used either with a ceramic resonator or crystal oscillator. Since each crystal and ceramic resonator have their own characteristics, the user should consult the crystal manufacturer for appropriate values of external components. In addition, see Figure 46. for the layout of the crystal. In all cases, an external clock operation is available. XO U T X IN VS S Figure 45. External Clock Drive Configuration 47 GMS81604/08 UNUSED PORTS All unused ports should be set properly that current flow through the port does not exist. First conseider the setting to input mode. Be sure that there is no current flow after considering its relationship with external circuit. In input mode, the pin impedance viewing from external MCU is very high that the current does not flow. But input voltage level should be V SS or V D D . Be careful that if unspecified voltage, i.e. if unfirmed 48 LG Semicon voltage level is applied to input pin, there can be little current ( max. 1mA at around 2V) flow. If it is not appropriate to set to input mode, then set to output mode considering there is no current flow. Setting to High or Low is decided considering its relationship with external circuit. For example, if there is external pull-up resistor then it is set to output mode, i.e. to High, and if there is external pull-down register, it is set to low. LG Semicon GMS81604/08 GMS81608T (OTP) PROGRAMMING The GMS81608T is one-time PROM (OTP) microcontroller with 8K bytes electrically programmable read only memory for the GMS81604/08 system evaluation, first production and fast mass production. The programming to the OTP device, user can have two way. One is using the universal programmer which is support LGS microcontrollers, other is using the general EPROM programmer. 1. Using the Universal programmer Third party universal programmer support to program the GMS81608T microcontrollers and lists are shown as below. Manufacturer: A d v a n t e c h Web site: http://www.aec.com.tw Programmer: LabTool-48 W ith these socket adapters, the GMS81608T can easy be programming and verifying using 27C256 EPROM mode on general-purpose PROM programmer. In assembler and file type, two files are generated after compiling. One is "*.HEX", another is "*.OTP". The "*.HEX" file is used for emulation in circuit emulator (CHOICE-Dr T M or CHOICE-Jr T M ) and "*.OTP" file is used for programming to the OTP device. Programming Procedure 1. Select the EPROM device and manufacturer on EPROM programmer (Intel 27C256). 2. Select the programming algorithm as an Intelligent mode (apply 1ms writing pulse), not a Quick pulse mode. 3. Load the file (*.OTP) to the programmer. Manufacturer: H i - L o s y s t e m s Web site: http://www.hilosystems.com.tw Programmer: ALL-11, GANG-08 Socket adapters are supported by third party programmer manufacturer. 2. Using the general EPROM(27C256) programmer The programming algorithm is simmilar with the standart EPROM 27C256. It give some convience that user can use standard EPROM programmer. Make sure that 1ms programming pulse must be used, it generally called "Intelligent Mode". Do not use 100us programming pulse mode, "Quick Pulse Mode". 4. Set the programming address range as below table. Address Set Value Buffer start address 6000 H Buffer end address 7FFF H Device start address 6000 H 5. Mount the socket adapter with the GMS81608T on the PROM programmer. 6. Start the PROM programmer to programming/ verifying. When user use general EPROM programmer, socket adaper is essencially required. It convert pin to fit the pin of general 27C256 EPROM. Three type socket adapters are provided according to package variation as below table. Socket Adapter Package Type OA816A-40SD 40 pin DIP OA816A-42SD 42 pin SDIP OA816A-42PL 44 pin PLCC 49 GMS81608T PROGRAMMING MANUAL LG Semicon GMS81608T PROGRAMMING SPECIFICATION GMS815045T PACKAGE DEVICE NAME PACKAGE GMS81608T 40DIP GMS81608T K 42SDIP GMS81608T PL 44PLCC PIN CONFIGURATION 40DIP 51 GMS81608T PROGRAMMING SPECIFICATION 42SDIP 44PLCC 52 LG Semicon LG Semicon GMS81608T PROGRAMMING SPECIFICATION 40DIP Package for GMS81608T Pin No. 1 MCU Mode TEST OTP Mode I Pin No. MCU Mode OTP Mode V PP - 21 R17 I/O A12 I 2 AV D D - (1) - 22 R16 I/O A11 I 3 R67/AN7 I/O (1) - 23 R15 I/O A10 I 4 R66/AN6 I/O (1) - 24 R14 I/O A9 I 5 R65/AN5 I/O (1) - 25 R13 I/O A8 I 6 R64/AN4 I/O (1) - 26 R12 I/O A7 I 7 R63/AN3 I (1) - 27 R11 I/O A6 I 8 R62/AN2 I (1) - 28 R10 I/O A5 I 9 R61/AN1 I (1) - 29 R07 I/O O7 O 10 R60/AN0 I (1) - 30 R06 I/O O6 O 11 R47/T3O I/O A4 I 31 R05 I/O O5 O 12 R46/T1O I/O (1) - 32 R04 I/O O4 O 13 R45/EC2 I/O CE I 33 R03 I/O O3 O 14 R44/EC0 I/O OE I 34 R02 I/O O2 O 15 R43/INT3 I/O A3 I 35 R01 I/O O1 O 16 R42/INT2 I/O A2 I 36 R00 I/O O0 O 17 R41/INT1 I/O A1 I 37 RESET I (1) - 18 R40/INT0 I/O A0 I 38 XOUT O (3) - 19 R55/BUZ I/O (1) - 39 X IN I (1) - 20 VDD - VDD - 40 V SS - (1) - NOTES: (1) Pins must be connected to V SS , because these pins are input ports during programming, program verify and reading (2) Pins must be connected to V D D . (3) X O U T pin must be opened during programming. I/O: Input/Output Pin I: Input Pin O: Output Pin 53 GMS81608T PROGRAMMING SPECIFICATION LG Semicon 42SDIP Package for GMS81608T Pin No. 1 MCU Mode TEST OTP Mode I - 22 MCU Mode R50 OTP Mode I/O (2) I 2 AV D D - (1) - 23 R17 I/O A12 3 R67/AN7 I/O (1) - 24 R16 I/O A11 I 4 R66/AN6 I/O (1) - 25 R15 I/O A10 I 5 R65/AN5 I/O (1) - 26 R14 I/O A9 I 6 R64/AN4 I/O (1) - 27 R13 I/O A8 I 7 R63/AN3 I (1) - 28 R12 I/O A7 I 8 R62/AN2 I (1) - 29 R11 I/O A6 I 9 R61/AN1 I (1) - 30 R10 I/O A5 I 10 R60/AN0 I (1) - 31 R07 I/O O7 O 11 R47/T3O I/O A4 I 32 R06 I/O O6 O 12 R46/T1O I/O (1) - 33 R05 I/O O5 O 13 R45/EC2 I/O CE I 34 R04 I/O O4 O 14 R44/EC0 I/O OE I 35 R03 I/O O3 O 15 R43/INT3 I/O A3 I 36 R02 I/O O2 O 16 R42/INT2 I/O A2 I 37 R01 I/O O1 O 17 R41/INT1 I/O A1 I 38 R00 I/O O0 O - 18 R40/INT0 I/O A0 I 39 RESET I (1) 19 R55/BUZ I/O (1) - 40 XOUT O (3) - 20 VDD - VDD - 41 X IN I (1) - 21 R51 I/O (2) - 42 V SS - (1) - NOTES: (1) Pins must be connected to V SS , because these pins are input ports during programming, program verify and reading (2) Pins must be connected to V D D . (3) X O U T pin must be opened during programming. 54 Pin No. V PP I/O: Input/Output Pin I: Input Pin O: Output Pin LG Semicon GMS81608T PROGRAMMING SPECIFICATION 44PLCC Package for GMS81608T Pin No. 1 MCU Mode N.C. OTP Mode Pin No. MCU Mode OTP Mode - N.C. - 23 R51 I/O (2) - 2 TEST I V PP - 24 R50 I/O (2) - 3 AV D D - (1) - 25 R17 I/O A12 I 4 R67/AN7 I/O (1) - 26 R16 I/O A11 I 5 R66/AN6 I/O (1) - 27 R15 I/O A10 I 6 R65/AN5 I/O (1) - 28 R14 I/O A9 I 7 R64/AN4 I/O (1) - 29 R13 I/O A8 I 8 R63/AN3 I (1) - 30 R12 I/O A7 I 9 R62/AN2 I (1) - 31 R11 I/O A6 I 10 R61/AN1 I (1) - 32 R10 I/O A5 I 11 R60/AN0 I (1) - 33 R07 I/O O7 O 12 R47/T3O I/O A4 I 34 R06 I/O O6 O 13 R46/T1O I/O (1) - 35 R05 I/O O5 O 14 R45/EC2 I/O CE I 36 R04 I/O O4 O 15 R44/EC0 I/O OE I 37 R03 I/O O3 O 16 R43/INT3 I/O A3 I 38 R02 I/O O2 O 17 N.C. - N.C. - 39 R01 I/O O1 O 18 R42/INT2 I/O A2 I 40 R00 I/O O0 O 19 R41/INT1 I/O A1 I 41 RESET I (1) - 20 R40/INT0 I/O A0 I 42 XOUT O (3) - 21 R55/BUZ I/O (1) - 43 X IN I (1) - 22 VDD - VDD - 44 V SS - (1) - NOTES: (1) Pins must be connected to V SS , because these pins are input ports during programming, program verify and reading (2) Pins must be connected to V D D . (3) X O U T pin must be opened during programming. I/O: Input/Output Pin I: Input Pin O: Output Pin 55 GMS81608T PROGRAMMING SPECIFICATION LG Semicon PIN FUNCTION (OTP Mode) V PP (Program Voltage) V P P is the input for the program voltage for programming the EPROM. CE ( Chip Enable) CE is the input for programming and verifying internal EPROM. OE (Output Enable) OE is the input of data output control signal for verify. A 0 ~A 12 (Address Bus) A 0 ~A 12 are address input pins for internal EPROM. O 0 ~O 7 (EPROM Data Bus) These are data bus for internal EPROM. PROGRAMMING The GMS81608T has address A 0 ~A 12 pins. Therefore, the programmer just program 8K bytes data of addresses 6000 H to 7FFF H into the GMS81608T OTP device. During the programming addresses A 13 , A 14 , A 15 of programmer must be pulled to a logic high. When the programmer write the data from 6000 H to 7FFF H , consequently, the data actually will be written into addresses E000 H to FFFF H of the OTP device. Programming Flow 1. The data format to be programmed is made up of Motorola S1 format. Ex) "Motorola S1" format; S00B00005741544348363038DF S1246000E1FF3BFF04A13F8F06E1C1711BFF3F1B003E1B00371B00361BFF3D1B003C1BFF3385 S12460211BFF321BFF351B92131B7FCC1BF3D61B17FD1BFCFC1B821B1BE01D1B8E191BFD18B1 : : S1057FF2941FD6 S1057FFEFF1F5F S9030000FC 2. Down load above data into programmer from PC. 3. Programming the data from address 6000 H to 7FFF H into the OTP MCU, the data must be turned over respectively, and then record the data into the OTP device. When read the data, it also must be turned over. Ex) 00(00000000) →FF(11111111), 76(01110110) →89(10001001), FF (11111111)→00(00000000) etc. 4. Of course, the check sum is result of the sum of whole data from address 6000 H to 7FFF H in the file (not reverse data of the OTP MCU). * When GMS81608T shipped, the blank data of GMS81608T is initially 00 H (not FF H ). 56 LG Semicon GMS81608T PROGRAMMING SPECIFICATION Programming Flow Buffer Start Address: 6000 H Buffer End Address: 7FFF H Device Start Address: E000 H GMS81608T xxxxxxxx.OTP Address Address E000 H 6000 H Program Verify Reading Program area Down Loading File Type: Universal Programmer 8 K BYTES Motorola S-format 7FFF H FFFF H Programming Example Data Address 1E 00 C4 00 FC 5E C0 70 : : : : 6A E0 : 00 E0 E000 H E001 H E002 H E003 H E004 H E005 H E006 H E007 H : : : : FFF2 H FFF3 H : FFFE H FFFF H File xxxxxxxx.OTP Programmer Buffer GMS81608T device Program Reading Verify Data Address Data Address E1 FF 3B FF 04 A1 3F 8F : : : : 94 1F : FF 1F 6000 H 6001 H 6002 H 6003 H 6004 H 6005 H 6006 H 6007 H : : : : 7FF2 H 7FF3 H : 7FFE H 7FFF H E1 FF 3B FF 04 A1 3F 8F : : : : 94 1F : FF 1F 6000 H 6001 H 6002 H 6003 H 6004 H 6005 H 6006 H 6007 H : : : : 7FF2 H 7FF3 H : 7FFE H 7FFF H Down Loading Up Loading Checksum = E1+FF+3B+FF+04+A1+3F+8F+ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ + 94+1F+ ⋅ ⋅ ⋅ ⋅ +FF+1F 57 GMS81608T PROGRAMMING SPECIFICATION LG Semicon DEVICE OPERATION MODE (T A = 25 °C ± 5 °C) Mode Read CE OE X A0~A15 VPP VDD O 0~ O 7 X VDD 5.0V DOUT Output Disable V IH V IH X VDD 5.0V Hi-Z Programming V IL V IH X V PP VDD D IN X V PP VDD DOUT Program Verify X NOTES: 1. X = Either V IL or V IH 3. See DC Characteristics Table for V D D and V P P voltages during programming. DC CHARACTERISTICS (V S S =0 V, T A = 25 °C ± 5 °C) Symbol Item Min Typ Max Unit VPP V P P supply voltage 12.0 - 13.0 V V D D (1) V D D supply voltage 5.75 - 6.25 V I P P (2) V P P supply current 50 mA I D D (2) V D D supply current 30 mA V IH Input high voltage V IL Input low voltage VOH Output high voltage VOL Output low voltage I IL Input leakage current 0.8 V D D CE=V IL V 0.2 V D D V D D -1.0 V V I O H = -2.5 mA 0.4 V I O L = 2.1 mA 5 uA NOTES: 1. V D D must be applied simultaneously or before V PP and removed simultaneously or after V P P . 2. The maximum current value is with outputs O 0 to O 7 unloaded. 58 Test condition LG Semicon GMS81608T PROGRAMMING SPECIFICATION SWITCHING WAVEFORMS WAVEFORM INPUTS OUTPUTS Must be steady W ill be steady May change from H to L W ill be changing from H to L May change from L to H W ill be changing from L to H Do not care any change permitted Changing state unknown Does not apply Center line is high impedance "Off" state READING WAVEFORMS V IH Addresses Address Valid V IL V IH (2) OE V IL t AS tO E tD H V IH High-Z Output Valid Output V IL NOTES: 1. The input timing reference level is 1.0 V for a V IL and 4.0V for a V IH at V D D =5.0V 2. To read the output data, transition requires on the O E from the high to the low after address setup time t A S . 59 GMS81608T PROGRAMMING SPECIFICATION LG Semicon PROGRAMMING ALGORITHM WAVEFORMS Program Verify Program V IH Addresses Address Stable V IL tA S tA H V IH Data High-Z Data In Stable V IL Data out Valid tD H tD S 12.5V VPP V DD tV P S 6.0V VDD 5.0V tV D S V IH CE V IL tP W tO E S V IH OE V IL tO P W NOTES: 1. The input timing reference level is 1.0 V for a V IL and 4.0V for a V IH at V D D =5.0V 60 tO E tD F P LG Semicon GMS81608T PROGRAMMING SPECIFICATION AC READING CHARACTERISTICS (V S S =0 V, T A = 25 °C ± 5 °C) Symbol Item Min t AS Address setup time tO E Data output delay time tD H Data hold time Typ Max Unit 2 Test condition us 200 ns 0 ns NOTES: 1. V D D must be applied simultaneously or before V PP and removed simultaneously or after V P P . AC PROGRAMMING CHARACTERISTICS (V S S =0 V, T A = 25 °C ± 5 °C; See DC Characteristics Table for V D D and V P P voltages.) Symbol t AS Item Min Typ Max Unit Address set-up time 2 us tO E S O E set-up time 2 us tD S Data setup time 2 us tA H Address hold time 0 us tD H Data hold time 1 us tD F P Output disable delay time 0 us tV P S V PP setup time 2 us tV D S V D D setup time 2 us tP W Program pulse width 0.95 CE pulse width when over programming 2.85 tO P W tO E Data output delay time *AC CONDITIONS OF TEST Input Rise and Fall Times (10% to Input Pulse Levels . . . . . . . . Input Timing Reference Level . . Output Timing Reference Level . 90%) . . . . . . . . . . . . . . . . . . . . . . . . . 1.0 1.05 ms 78.75 ms 200 ns Condition* (Note 1) (Note 2) 20 ns 0.45V to 4.55V 1.0V to 4.0V 1.0V to 4.0V NOTES: 1. V D D must be applied simultaneously or before V PP and removed simultaneously or after V P P . 2. The length of the overprogram pulse may vary from 2.85 msec to 78.75 msec as a function of the iteration counter value X (Intelligent Programming Algorithm).Refer to flow chart of page 13. 61 GMS81608T PROGRAMMING SPECIFICATION LG Semicon Intelligent Programming Algorithm START ADDRESS= FIRST LOCATION V D D = 6.0V V PP = 12.5V X=0 PROGRAM ONE 1 ms PULSE INCREMENT X YES X = 25 ? NO FAIL VERIFY BYTE VERIFY ONE BYTE FAIL PASS PASS PROGRAM ONE PULSE OF 3X msec DURATION INCREMENT ADDRESS NO LAST ADDRESS ? YES V D D = V PP = 5.0V COMPARE ALL BYTES TO ORIGINAL DATA FAIL PASS DEVICE PASSED 62 DEVICE FAILED APPENDIX GMS800 Series A. INSTRUCTION A.1 Terminology List Terminology Description A Accumulator X X - register Y Y - register PSW Program Status Word #imm 8-bit Immediate data dp Direct Page Offset Address !abs Absolute Address [] Indirect expression {} Register Indirect expression { }+ Register Indirect expression, after that, Register auto-increment .bit Bit Position A.bit Bit Position of Accumulator dp.bit Bit Position of Direct Page Memory M.bit Bit Position of Memory Data (000H~0FFFH) rel upage Relative Addressing Data U-page (0FF00H~0FFFFH) Offset Address n Table CALL Number (0~15) + Addition Upper Nibble Expression in Opcode 0 x Bit Position Upper Nibble Expression in Opcode 1 y Bit Position i − Subtraction × Multiplication / Division () Contents Expression ∧ AND ∨ OR ⊕ Exclusive OR ~ NOT ← Assignment / Transfer / Shift Left → Shift Right ↔ Exchange = Equal ≠ Not Equal GMS800 Series A.2 Instruction Map LOW 00000 HIGH 00 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F BBS ADC SET1 BBS dp.bit,re #imm dp.bit A.bit,rel l ADC dp ADC dp+X ADC !abs ASL A ASL dp TCALL SETA1 0 .bit CLRC SBC #imm SBC dp SBC dp+X SBC !abs ROL A ROL dp 010 CLRG CMP #imm CMP dp CMP dp+X CMP !abs LSR A 011 DI OR #imm OR dp OR dp+X OR !abs 100 CLRV AND #imm AND dp AND dp+X 101 SETC EOR #imm EOR dp 110 SETG LDA #imm 111 EI 000 - 001 LOW 10000 HIGH 10 10001 10010 11 12 BIT dp POP A PUSH A BRK TCALL CLRA1 COM 2 .bit dp POP X PUSH X BRA rel LSR dp TCALL NOT1 4 M.bit POP Y PUSH PCALL Y Upage ROR A ROR dp TCALL OR1 CMPX 6 OR1B dp POP PSW PUSH PSW RET AND !abs INC A INC dp TCALL AND1 CMPY CBNE 8 AND1B dp dp+X TXSP INC X EOR dp+X EOR !abs DEC A DEC dp TCALL EOR1 DBNE 10 EOR1B dp XMA dp+X TSPX DEC X LDA dp LDA dp+X LDA !abs TXA LDY dp TCALL LDC 12 LDCB LDX dp LDX dp+Y XCN DAS LDM dp,#im m STA dp STA dp+X STA !abs TAX STY dp TCALL 14 STC M.bit STX dp STX dp+Y XAX STOP 10011 13 10100 14 10101 15 10110 16 10111 17 11000 18 11001 19 11010 1A 11011 1B 11100 1C 11101 1D 11110 1E 11111 1F BBC ADC {X} ADC ADC ADC !abs+Y [dp+X] [dp]+Y ASL !abs ASL dp+X TCALL 1 JMP !abs BIT !abs ADDW dp LDX #imm JMP [!abs] SUBW dp TST dp 000 BPL rel 001 BVC rel SBC {X} SBC SBC SBC !abs+Y [dp+X] [dp]+Y ROL !abs ROL dp+X TCALL CALL 3 !abs TEST !abs LDY #imm JMP [dp] 010 BCC rel CMP {X} CMP CMP CMP !abs+Y [dp+X] [dp]+Y LSR !abs LSR dp+X TCALL 5 TCLR1 CMPW CMPX !abs dp #imm CALL [dp] 011 BNE rel OR {X} OR OR OR !abs+Y [dp+X] [dp]+Y ROR !abs ROR dp+X TCALL DBNE CMPX 7 Y !abs 100 BMI rel AND {X} AND AND AND !abs+Y [dp+X] [dp]+Y INC !abs INC dp+X TCALL 9 DIV 101 BVS rel EOR {X} EOR EOR EOR !abs+Y [dp+X] [dp]+Y DEC !abs DEC dp+X TCALL 11 XMA {X} XMA dp 110 BCS rel LDA {X} LDA LDA LDA !abs+Y [dp+X] [dp]+Y LDY !abs LDY dp+X TCALL 13 LDA {X}+ 111 BEQ rel STA {X} STA STA STA !abs+Y [dp+X] [dp]+Y STY !abs STY dp+X TCALL 15 STA {X}+ CLR1 dp.bit BBC A.bit,rel dp.bit,rel MUL LDYA dp CMPY #imm RETI INC Y TAY DECW dp DEC Y TYA LDX !abs STYA dp XAY DAA STX !abs CBNE dp XYX NOP CMPY INCW !abs dp ii GMS800 Series A.3 Instruction Set Arithmetic / Logic Operation No. iii Mnemonic Op Code Byte No Cycle No Operation 1 ADC #imm 04 2 2 Add with carry. 2 ADC dp 05 2 3 A←(A)+(M)+C 3 ADC dp + X 06 2 4 4 ADC !abs 07 3 4 5 ADC !abs + Y 15 3 5 6 ADC [ dp + X ] 16 2 6 7 ADC [ dp ] + Y 17 2 6 8 ADC { X } 14 1 3 9 AND #imm 84 2 2 Logical AND A← (A)∧(M) Flag NVGBHIZC NV--H-ZC 10 AND dp 85 2 3 11 AND dp + X 86 2 4 12 AND !abs 87 3 4 13 AND !abs + Y 95 3 5 14 AND [ dp + X ] 96 2 6 15 AND [ dp ] + Y 97 2 6 16 AND { X } 94 1 3 17 ASL A 08 1 2 18 ASL dp 09 2 4 19 ASL dp + X 19 2 5 20 ASL !abs 18 3 5 21 CMP #imm 44 2 2 22 CMP dp 45 2 3 23 CMP dp + X 46 2 4 24 CMP !abs 47 3 4 25 CMP !abs + Y 55 3 5 26 CMP [ dp + X ] 56 2 6 27 CMP [ dp ] + Y 57 2 6 28 CMP { X } 54 1 3 29 CMPX #imm 5E 2 2 30 CMPX dp 6C 2 3 31 CMPX !abs 7C 3 4 32 CMPY #imm 7E 2 2 33 CMPY dp 8C 2 3 34 CMPY !abs 9C 3 4 35 COM dp 2C 2 4 1’S Complement : ( dp ) ← ~( dp ) N-----Z- 36 DAA DF 1 3 Decimal adjust for addition N-----ZC 37 DAS CF 1 3 Decimal adjust for subtraction N-----ZC 38 DEC A A8 1 2 Decrement N-----ZC N-----Z- Arithmetic shift left C 7 6 5 4 3 2 1 0 ← ←←←←←←←← N-----ZC ← “0” Compare accumulator contents with memory con- N-----ZC tents (A) -(M) Compare X contents with memory contents (X)-(M) N-----ZC Compare Y contents with memory contents (Y)-(M) N-----ZC GMS800 Series No. Mnemonic Op Code Byte No Cycle No Flag Operation NVGBHIZC M← (M)-1 39 DEC dp A9 2 4 40 DEC dp + X B9 2 5 N-----Z- 41 DEC !abs B8 3 5 N-----Z- 42 DEC X AF 1 2 N-----Z- 43 DEC Y BE 1 2 44 DIV 9B 1 12 Divide : YA / X Q: A, R: Y 45 EOR #imm A4 2 2 Exclusive OR 46 EOR dp A5 2 3 47 EOR dp + X A6 2 4 48 EOR !abs A7 3 4 49 EOR !abs + Y B5 3 5 50 EOR [ dp + X ] B6 2 6 51 EOR [ dp ] + Y B7 2 6 52 EOR { X } B4 1 3 53 INC A 88 1 2 54 INC dp 89 2 4 55 INC dp + X 99 2 5 N-----Z- 56 INC !abs 98 3 5 N-----Z- 57 INC X 8F 1 2 N-----Z- 58 INC Y 9E 1 2 N-----Z- 59 LSR A 48 1 2 60 LSR dp 49 2 4 61 LSR dp + X 59 2 5 62 LSR !abs 58 3 5 63 MUL 5B 1 9 Multiply : YA ← Y × A 64 OR #imm 64 2 2 Logical OR 65 OR dp 65 2 3 66 OR dp + X 66 2 4 67 OR !abs 67 3 4 68 OR !abs + Y 75 3 5 69 OR [ dp + X ] 76 2 6 70 OR [ dp ] + Y 77 2 6 N-----Z- N-----Z- Increment N-----ZC M← (M)+1 7 6 5 4 3 2 1 0 C “0” → → → → → → → → → → 74 1 3 28 1 2 73 ROL dp 29 2 4 74 ROL dp + X 39 2 5 75 ROL !abs 38 3 5 76 ROR A 68 1 2 Rotate right through Carry 77 ROR dp 69 2 4 78 ROR dp + X 79 2 5 7 6 5 4 3 2 1 0 →→→→→→→→ 78 3 5 24 2 2 N-----Z- N-----Z- OR { X } ROR !abs N-----ZC A ← (A)∨(M) ROL A SBC #imm N-----Z- Logical shift right 72 80 NV--H-Z- A← (A)⊕(M) 71 79 N-----Z- Rotate left through Carry C 7 6 5 4 3 2 1 0 ←←←←←←←← C N-----ZC N-----ZC Subtract with Carry iv GMS800 Series No. v Mnemonic Op Code Byte No Cycle No 81 SBC dp 25 2 3 82 SBC dp + X 26 2 4 83 SBC !abs 27 3 4 84 SBC !abs + Y 35 3 5 Operation Flag NVGBHIZC A ← ( A ) - ( M ) - ~( C ) NV--HZC 85 SBC [ dp + X ] 36 2 6 86 SBC [ dp ] + Y 37 2 6 87 SBC { X } 34 1 3 88 TST dp 4C 2 3 Test memory contents for negative or zero, ( dp ) N-----Z00H 89 XCN CE 1 5 Exchange nibbles within the accumulator A7~A4 ↔ A3~A0 N-----Z- GMS800 Series Register / Memory Operation No. Mnemonic Op Code Byte No Cycle No 1 LDA #imm C4 2 2 2 LDA dp C5 2 3 3 LDA dp + X C6 2 4 4 LDA !abs C7 3 4 5 LDA !abs + Y D5 3 5 6 LDA [ dp + X ] D6 2 6 Operation Load accumulator A←(M) N-----Z- 7 LDA [ dp ] + Y D7 2 6 8 LDA { X } D4 1 3 9 LDA { X }+ DB 1 4 X- register auto-increment : A ← ( M ) , X ← X + 1 10 LDM dp,#imm E4 3 5 Load memory with immediate data : ( M ) ← imm Load X-register 11 LDX #imm 1E 2 2 12 LDX dp CC 2 3 13 LDX dp + Y CD 2 4 14 LDX !abs DC 3 4 Flag NVGBHIZC X ←(M) 15 LDY #imm 3E 2 2 16 LDY dp C9 2 3 17 LDY dp + X D9 2 4 18 LDY !abs D8 3 4 19 STA dp E5 2 4 20 STA dp + X E6 2 5 21 STA !abs E7 3 5 22 STA !abs + Y F5 3 6 23 STA [ dp + X ] F6 2 7 24 STA [ dp ] + Y F7 2 7 25 STA { X } F4 1 4 26 STA { X }+ FB 1 4 X- register auto-increment : ( M ) ← A, X ← X + 1 27 STX dp EC 2 4 Store X-register contents in memory 28 STX dp + Y ED 2 5 29 STX !abs FC 3 5 30 STY dp E9 2 4 -------N-----Z- Load Y-register Y←(M) N-----Z- Store accumulator contents in memory (M)←A -------- (M)← X -------- Store Y-register contents in memory (M)← Y 31 STY dp + X F9 2 5 32 STY !abs F8 3 5 33 TAX E8 1 2 Transfer accumulator contents to X-register : X ← A N-----Z- 34 TAY 9F 1 2 Transfer accumulator contents to Y-register : Y ← A N-----Z- 35 TSPX AE 1 2 Transfer stack-pointer contents to X-register : X ← sp N-----Z- 36 TXA C8 1 2 Transfer X-register contents to accumulator: A ← X N-----Z- 37 TXSP 8E 1 2 Transfer X-register contents to stack-pointer: sp ← X N-----Z- 38 TYA BF 1 2 Transfer Y-register contents to accumulator: A ← Y N-----Z- 39 XAX EE 1 4 Exchange X-register contents with accumulator :X ↔ -------A -------- vi GMS800 Series 40 XAY DE 1 4 Exchange Y-register contents with accumulator :Y ↔ -------A Exchange memory contents with accumulator 41 XMA dp BC 2 5 42 XMA dp+X AD 2 6 43 XMA {X} BB 1 5 44 XYX FE 1 4 (M)↔A N-----Z- Exchange X-register contents with Y-register : X ↔ Y -------- 16-BIT operation No. Mnemonic Op Code Byte No Cycle No Operation Flag NVGBHIZC 1 ADDW dp 1D 2 5 16-Bits add without Carry YA ← ( YA ) ( dp +1 ) ( dp ) NV--H-ZC 2 CMPW dp 5D 2 4 Compare YA contents with memory pair contents : (YA) − (dp+1)(dp) N-----ZC 3 DECW dp BD 2 6 Decrement memory pair ( dp+1)( dp) ← ( dp+1) ( dp) - 1 N-----Z- 4 INCW dp 9D 2 6 Increment memory pair ( dp+1) ( dp) ← ( dp+1) ( dp ) + 1 N-----Z- 5 LDYA dp 7D 2 5 Load YA YA ← ( dp +1 ) ( dp ) N-----Z- 6 STYA dp DD 2 5 Store YA ( dp +1 ) ( dp ) ← YA -------- 7 SUBW dp 3D 2 5 16-Bits subtract without carry YA ← ( YA ) - ( dp +1) ( dp) NV--H-ZC Op Code Byte No Cycle No 8B 3 4 Bit AND C-flag : C ← ( C ) ∧ ( M .bit ) Bit Manipulation No. vii Mnemonic Operation Flag NVGBHIZC 1 AND1 M.bit 2 AND1B M.bit 8B 3 4 Bit AND C-flag and NOT : C ← ( C ) ∧ ~( M .bit ) -------C 3 BIT dp 0C 2 4 Bit test A with memory : MM----Z- 4 BIT !abs 1C 3 5 Z ← ( A ) ∧ ( M ) , N ← ( M7 ) , V ← ( M6 ) 5 CLR1 dp.bit y1 2 4 Clear bit : ( M.bit ) ← “0” -------- 6 CLRA1 A.bit 2B 2 2 Clear A bit : ( A.bit ) ← “0” -------- 7 CLRC 20 1 2 Clear C-flag : C ← “0” -------0 8 CLRG 40 1 2 Clear G-flag : G ← “0” --0----- 9 CLRV 80 1 2 Clear V-flag : V ← “0” -0--0--- 10 EOR1 M.bit AB 3 5 Bit exclusive-OR C-flag : C ← ( C ) ⊕ ( M .bit ) -------C -------C -------C 11 EOR1B M.bit AB 3 5 Bit exclusive-OR C-flag and NOT : C ← ( C ) ⊕ ~(M .bit) 12 LDC M.bit CB 3 4 Load C-flag : C ← ( M .bit ) -------C 13 LDCB M.bit CB 3 4 Load C-flag with NOT : C ← ~( M .bit ) -------C 14 NOT1 M.bit 4B 3 5 Bit complement : ( M .bit ) ← ~( M .bit ) -------- 15 OR1 M.bit 6B 3 5 Bit OR C-flag : C ← ( C ) ∨ ( M .bit ) -------C 16 OR1B M.bit 6B 3 5 Bit OR C-flag and NOT : C ← ( C ) ∨ ~( M .bit ) -------C GMS800 Series Set bit : ( M.bit ) ← “1” -------- 2 Set A bit : ( A.bit ) ← “1” -------- 2 Set C-flag : C ← “1” -------1 2 Set G-flag : G ← “1” --1----- 3 6 Store C-flag : ( M .bit ) ← C -------- 5C 3 6 Test and clear bits with A : A - ( M ) , ( M ) ← ( M ) ∧ ~( A ) N-----Z- 3C 3 6 Test and set bits with A : A-(M), (M)← (M)∨(A) N-----Z- 17 SET1 dp.bit x1 2 18 SETA1 A.bit 0B 2 19 SETC A0 1 20 SETG C0 1 21 STC M.bit EB 22 TCLR1 !abs 23 TSET1 !abs 4 viii GMS800 Series Branch / Jump Operation No. ix Mnemonic Op Code Byte No Cycle No Operation Flag NVGBHIZC 1 BBC A.bit,rel y2 2 4/6 Branch if bit clear : 2 BBC dp.bit,rel y3 3 5/7 if ( bit ) = 0 , then pc ← ( pc ) + rel 3 BBS A.bit,rel x2 2 4/6 Branch if bit set : 4 BBS dp.bit,rel x3 3 5/7 if ( bit ) = 1 , then pc ← ( pc ) + rel 5 BCC rel 50 2 2/4 Branch if carry bit clear if ( C ) = 0 , then pc ← ( pc ) + rel -------- 6 BCS rel D0 2 2/4 Branch if carry bit set if ( C ) = 1 , then pc ← ( pc ) + rel -------- 7 BEQ rel D0 2 2/4 Branch if equal if ( Z ) = 1 , then pc ← ( pc ) + rel -------- 8 BMI rel 90 2 2/4 Branch if minus if ( N ) = 1 , then pc ← ( pc ) + rel -------- 9 BNE rel 70 2 2/4 Branch if not equal if ( Z ) = 0 , then pc ← ( pc ) + rel -------- 10 BPL rel 10 2 2/4 Branch if minus if ( N ) = 0 , then pc ← ( pc ) + rel -------- 11 BRA rel 2F 2 4 Branch always pc ← ( pc ) + rel -------- 12 BVC rel 30 2 2/4 Branch if overflow bit clear if (V) = 0 , then pc ← ( pc) + rel -------- 13 BVS rel B0 2 2/4 Branch if overflow bit set if (V) = 1 , then pc ← ( pc ) + rel -------- 14 CALL !abs 3B 3 8 Subroutine call M( sp)←( pcH ), sp←sp - 1, M(sp)← (pcL), sp ←sp - 1, -------if !abs, pc← abs ; if [dp], pcL← ( dp ), pcH← ( dp+1 ) . --------------- 15 CALL [dp] 5F 2 8 16 CBNE dp,rel FD 3 5/7 17 CBNE dp+X,rel 8D 3 6/8 18 DBNE dp,rel AC 3 5/7 Decrement and branch if not equal : 19 DBNE Y,rel 7B 2 4/6 if ( M ) ≠ 0 , then pc ← ( pc ) + rel. 20 JMP !abs 1B 3 3 21 JMP [!abs] 1F 3 5 22 JMP [dp] 3F 2 4 23 PCALL upage 4F 2 6 U-page call M(sp) ←( pcH ), sp ←sp - 1, M(sp) ← ( pcL ), sp ← sp - 1, pcL ← ( upage ), pcH ← ”0FFH” . -------- 24 TCALL n nA 1 8 Table call : (sp) ←( pcH ), sp ← sp - 1, M(sp) ← ( pcL ),sp ← sp - 1, pcL ← (Table vector L), pcH ← (Table vector H) -------- Compare and branch if not equal : -------- if ( A ) ≠ ( M ) , then pc ← ( pc ) + rel. -------- Unconditional jump pc ← jump address -------- GMS800 Series Control Operation & Etc. No. Mnemonic Op Code Byte No Cycle No Operation ---1-0-- Flag NVGBHIZC 0F 1 8 Software interrupt : B ← ”1”, M(sp) ← (pcH), sp ←sp-1, M(s) ← (pcL), sp ← sp - 1, M(sp) ← (PSW), sp ← sp -1, pcL ← ( 0FFDEH ) , pcH ← ( 0FFDFH) . DI 60 1 3 Disable all interrupts : I ← “0” -----0-- EI E0 1 3 Enable all interrupt : I ← “1” -----1-- NOP FF 1 2 No operation -------- 1 BRK 2 3 4 5 POP A 0D 1 4 sp ← sp + 1, A ← M( sp ) 6 POP X 2D 1 4 sp ← sp + 1, X ← M( sp ) 7 POP Y 4D 1 4 sp ← sp + 1, Y ← M( sp ) 8 POP PSW 6D 1 4 sp ← sp + 1, PSW ← M( sp ) -------restored 9 PUSH A 0E 1 4 M( sp ) ← A , sp ← sp - 1 10 PUSH X 2E 1 4 M( sp ) ← X , sp ← sp - 1 11 PUSH Y 4E 1 4 M( sp ) ← Y , sp ← sp - 1 12 PUSH PSW 6E 1 4 M( sp ) ← PSW , sp ← sp - 1 13 RET 6F 1 5 Return from subroutine sp ← sp +1, pcL ← M( sp ), sp ← sp +1, pcH ← M( -------sp ) 14 RETI 7F 1 6 Return from interrupt sp ← sp +1, PSW ← M( sp ), sp ← sp + 1, pcL ← M( sp ), sp ← sp + 1, pcH ← M( sp ) restored 15 STOP EF 1 3 Stop mode ( halt CPU, stop oscillator ) -------- -------- x MASK ORDER & VERIFICATION SHEET GMS81604-HC Customer should write inside thick line box. 1. Customer Information 2. Device Information Package Company Name 40DIP 42SDIP 44PLCC Application YYYY MM DD Order Date Tel: Mask Data File Name: ( Hitel Fax: .OTP) Check Sum: ( ) 0000H Name & Signature: Chollian Set “FF” in this area Internet 6FFFH 7000H ROM (4K) 7FFFH 3. Marking Specification (Please check mark into LGS GM S81604 -HC YYW W ) Customer’s part num ber KOREA 4. Delivery Schedule Quantity Date YYYY MM DD Customer Sample pcs YYYY MM DD pcs Risk Order 5. ROM Code Verification YYYY This box is written after “5.Verification”. MM DD YYYY MM DD Approval Date: Verification D ate: Please confirm our verification data. I agree w ith your verification data and confirm you to m ake m ask set. Tel: Check Sum: Tel: Name & Signature: LG Confirmation Fax: Fax: Name & Signature: LG Semicon MASK ORDER & VERIFICATION SHEET GMS81608-HC Customer should write inside thick line box. 1. Customer Information 2. Device Information Package Company Name 40DIP 42SDIP 44PLCC Application YYYY MM DD Order Date Tel: Mask Data File Name: ( Hitel Fax: .OTP) Check Sum: ( ) 0000H Name & Signature: Chollian Set “FF” in this area Internet 5FFFH 6000H ROM (8K) 7FFFH 3. Marking Specification (Please check mark into LGS GM S81608 -HC YYW W ) Customer’s part num ber KOREA 4. Delivery Schedule Quantity Date YYYY MM DD Customer Sample pcs YYYY MM DD pcs Risk Order 5. ROM Code Verification YYYY This box is written after “5.Verification”. MM DD YYYY MM DD Approval Date: Verification D ate: Please confirm our verification data. I agree w ith your verification data and confirm you to m ake m ask set. Tel: Check Sum: Tel: Name & Signature: LG Confirmation Fax: Fax: Name & Signature: LG Semicon