GMS81508A GMS81516A USER’S MANUAL Revision History Rev 2.2 (Dec. 1998) Add the package dimension for 64LQFP on page 3-1, 4-1. Rev 2.1 (Nov. 1998) Operating Temperature, -10~75°C is extended to -20~85°C. Add the unused port guidance on page 55. Correct errata for opcode of “EOR [dp+X], EOR [dp]+Y, EOR {X}” in “Instruction Set”. Add the OTP device programming guidance, recommend using “Intelligent Mode”. Add the chapter for OTP programming manual as an appendix. Rev 2.0 (Sep. 1997) - CONTENTS 1. OVERVIEW...........................................................................................................................................1 1.1. FEATURES ..........................................................................................................................................1 1.2. BLOCK DIAGRAM..............................................................................................................................2 1.3. PIN ASSIGNMENT ..............................................................................................................................3 1.4. PACKAGE DIMENSION .....................................................................................................................4 1.5. PIN DESCRIPTION..............................................................................................................................5 2. FUNCTIONS..........................................................................................................................................7 2.1. REGISTERS .........................................................................................................................................7 2.1.1. A - Register....................................................................................................................................8 2.1.2. X- Register.....................................................................................................................................8 2.1.3. Y- Register .....................................................................................................................................8 2.1.4. Stack Pointer .................................................................................................................................8 2.1.5. Program Counter .........................................................................................................................10 2.1.6. Program Status Word...................................................................................................................10 2.2. MEMORY SPACE..............................................................................................................................12 2.2.1. RAM area ....................................................................................................................................12 2.2.2. Peripheral Register area ..............................................................................................................12 2.2.3. Program ROM area .....................................................................................................................12 2.2.4. Peripheral Register List ...............................................................................................................14 2.3. CLOCK GENERATION CIRCUIT .....................................................................................................16 2.3.1. Oscillation Circuit .......................................................................................................................16 2.3.2. Prescaler .....................................................................................................................................17 2.4. BASIC INTERVAL TIMER................................................................................................................18 2.4.1. Control of Basic Interval Timer ....................................................................................................18 2.5. WATCH DOG TIMER........................................................................................................................19 2.5.1. Control of Watch Dog Timer ........................................................................................................19 2.5.2. The output of WDT signal.............................................................................................................20 2.6. TIMER................................................................................................................................................21 2.6.1. Control of Timer ..........................................................................................................................23 2.6.2. Interval Timer ..............................................................................................................................24 2.6.3. Event Counter ..............................................................................................................................24 2.6.4. Pulse Output ................................................................................................................................24 2.6.5. Input Capture...............................................................................................................................24 2.7. EXTERNAL INTERRUPT..................................................................................................................26 2.8. A/D CONVERTER .............................................................................................................................27 2.8.1. Control of A/D Converter .............................................................................................................27 2.9. SERIAL I/O ........................................................................................................................................29 2.9.1. Data Transmission/Receiving Timing ...........................................................................................31 2.9.2. The Serial I/O operation by Srdy pin ............................................................................................31 2.9.3. The method of Serial I/O ..............................................................................................................32 2.9.4. The Method to Test Correct Transmission with S/W ......................................................................32 2.10. PWM ................................................................................................................................................33 2.10.1. Controls of PWM .......................................................................................................................33 2.11. BUZZER DRIVER............................................................................................................................35 2.11.1. Buzzer Driver Operation ............................................................................................................36 2.12. INTERRUPTS...................................................................................................................................37 2.12.1. Interrupt Circuit Configuration and Kinds..................................................................................37 2.12.2. Interrupt Control........................................................................................................................38 2.12.3. Interrupt Priority .......................................................................................................................39 2.12.4. Interrupt Sequence..................................................................................................................... 40 2.12.5. Software Interrupt ..................................................................................................................... 41 2.12.6. Multiple Interrupt ...................................................................................................................... 42 2.13. STANDBY FUNCTION ................................................................................................................... 44 2.13.1. STOP Mode ............................................................................................................................... 45 2.13.2. STOP Mode Release .................................................................................................................. 45 2.14. RESET FUNCTION ......................................................................................................................... 47 3. I/O PORTS........................................................................................................................................... 48 3.1. R0 PORT............................................................................................................................................ 48 3.2. R1 PORT............................................................................................................................................ 49 3.3. R2 PORT............................................................................................................................................ 50 3.4. R3 PORT............................................................................................................................................ 51 3.5. R4 PORT............................................................................................................................................ 52 3.6. R5 PORT............................................................................................................................................ 53 3.7. R6 PORT ............................................................................................................................................ 54 3.8. TERMINAL TYPES........................................................................................................................... 56 4. ELECTRICAL CHARACTERISTICS............................................................................................... 60 4.1. ABOULUTE MAXIMUM RATINGS................................................................................................. 60 4.2. RECOMMENDED OPERATING CONDITIONS............................................................................... 60 4.3. A/D CONVERTER CHARACTERISTICS ......................................................................................... 60 4.4. DC CHARACTERISTICS .................................................................................................................. 61 4.5. AC CHARACTERISTICS .................................................................................................................. 62 4.5.1. Input Conditions.......................................................................................................................... 62 4.5.2. Serial Transfer ............................................................................................................................ 63 4.5.3. Microprocessor Mode I/O Timing ................................................................................................ 64 4.5.4. Bus Holding Timing..................................................................................................................... 65 5. INSTRUCTION SET........................................................................................................................... 66 GMS81508/16 1. OVERVIEW GMS81508/16 is a single chip microcomputer designed CMOS technology. The use of CMOS process enables extremely low power consumption. This device using the G8MC Core includes several peripheral functions such as Timer, A/D Converter, Programmable Buzzer Driver, Serial I/O, Pulse Width Modulation Function, etc. ROM,RAM,I/O are placed on the same memory map in addition to simple instruction set. 1.1. FEATURES GMS81508 ROM(Bytes) RAM(Bytes) Execution Time Basic Interval Timer Watch Dog Timer Timer ADC PWM Serial I/O External Interrupt Buzzer Driver I/O Port Power Save Mode Operating Voltage Operating Frequency Package OTP Application GMS81516 8K 16K 448 bytes(includes stack area) 0.5us (@Xin=8MHz) 8bit ✕ 1ch. 6bit ✕ 1ch. 8bit✕ 4ch.(or 16bit ✕ 2ch.) 8bit ✕ 8ch. 8bit ✕ 2ch. 8bit ✕ 1ch. 4ch. Programmable Buzzer Driving Port 4 - Input only 52 - Input/Output STOP Mode 4.5 ∼ 5.5V ( @ Xin=8MHz ) 1 ∼ 8MHz 64SDIP, 64QFP GMS81516T Home Appliances, LED Applications 1 HYUNDAI MicroElectronics 1.2. BLOCK DIAGRAM AVref R60~R67 (AN0~AN7) R57/PWM1 R56/PWM0 AVss A/D CONVERTER G8MC CORE PWM RAM (448 BYTE) R55/BUZ R54/WDTO R53/Srdy R52/Sclk R51/Sout R50/Sin R47/T3 O R46/T1 O R45/EC2 R44/EC0 R43/INT3 R42/INT2 R41/INT1 R40/INT0 MP RESET Xin Xout BUZZER R64 : R67 R5 PORT R50 : R57 R4 PORT R40 : R47 R3 PORT R30 : R37 R2 PORT R20 : R27 R1 PORT R10 : R17 R0 PORT R00 : R07 W.D.T ROM (8/16K BYTE) S.I.C TIMER INTERRUPT CLOCK GEN. / SYSTEM CONTROL Vdd 2 R6 PORT R60 : R63 Vss PRESCALER / B.I.T GMS81508/16 PIN ASSIGNMENT MP MODE Vdd MP AVss AVref R67/AN7 R66/AN6 R65/AN5 R64/AN4 R63/AN3 R62/AN2 R61/AN1 R60/AN0 R57/PWM1 R56/PWM0 R55/BUZ R54/WDTO R53/Srdy R52/Sclk R51/Sout R50/Sin R47/T3O R46/T1O R45/EC2 R44/EC0 R43/INT3 R42/INT2 R41/INT1 R40/INT0 RESET Xin Xout Vss 1 64 2 63 3 62 4 61 5 60 6 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 R30/ R31/ R32/ R33/ R34/ R35/ R36/ R37/ R00/ R01/ R02/ R03/ R04/ R05/ R06/ R07/ R10/ R11/ R12/ R13/ R14/ R15/ R16/ R17/ R20/ R21/ R22/ R23/ R24/ R25/ R26/ R27/ 59 G M S 8 1 5 0 8 / 1 6 7 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 30 35 31 34 32 33 RD Wt R/W C SYNC BRK BRQ HALT D0 D1 D2 D3 D4 D5 D6 D7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 R21/A9 R20/A8 R17/A7 R16/A6 R15/A5 R14/A4 R13/A3 R12/A2 R11/A1 R10/A0 R07/D7 R06/D6 R05/D5 R04/D4 R03/D3 R02/D2 R01/D1 R00/D0 R37/HALT 64 SDIP 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 52 32 R22/A10 R35 BAK 53 31 R23/A11 R34 SYNC 54 30 R24/A12 R33 C 55 29 R25/A13 R32 R/W 56 28 R26/A14 R31 Wt 57 27 R17/A15 26 Vss 25 Xout MP 60 24 Xin AVss 61 23 RESET AVref 62 22 R40/INT0 R67/AN7 63 21 R41/INT1 R66/AN6 64 20 R42/INT2 GMS81508/16 R62/AN2 R61/AN1 R60/AN0 R57/PWM1 R56/PWM0 10 11 12 13 14 15 16 17 18 19 R43/INT3 R63/AN3 9 R44/EC0 8 R45/EC2 7 R46/T1O 6 R47/T3O 5 R50/Sin 4 R51/Sout 3 R52/Sclk 2 R53/Srdy 1 R64/AN4 Vdd 59 R54/WDTO R30 Rd 58 R55/BUZ R36 BRQ R65/AN5 1.3. 64 QFP 3 HYUNDAI MicroElectronics 49 50 51 52 53 54 55 56 57 58 59 GMS81508/16 60 61 62 63 64 12 13 14 15 16 5 6 7 8 9 10 11 R63/AN3 R62/AN2 R61/AN1 R60/AN0 R57/PWM1 R56/PWM0 R55/BUZ R54/WDTO R53/SRDY R52/SCLK R51/SOUT R50/SIN R47/T3O R46/T1O R45/EC2 R44/EC0 3-1 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 R37 R36 R35 R34 R33 R32 R31 R30 VDD MP AVSS AVREF R67/AN7 R66/AN6 R65/AN5 R64/AN4 37 36 35 34 33 48 47 46 45 44 43 42 41 40 39 38 R00 R01 R02 R03 R04 R05 R06 R07 R10 R11 R12 R13 R14 R15 R16 R17 64LQFP R20 R21 R22 R23 R24 R25 R26 R27 VSS XOUT XIN RESET R40/INT0 R41/INT1 R42/INT2 R43/INT3 HYUNDAI MicroElectronics 1.4 PACKAGE DIMENSION 64SDIP UNIT: INCH 2.280 2.260 min. 0.015 0.750 BSC 0.050 0.030 0.022 0.016 64QFP 0.070 BSC 0.140 0.120 0.205 max. 0.680 0.660 24.15 23.65 20.10 19.90 UNIT: MM 14.10 13.90 0-7° 0.36 0.10 SEE DETAIL "A" 3.18 max. 0.50 0.35 1.00 BSC 1.03 0.73 0.23 0.13 18.15 17.65 0.012 0.008 0-15° 1.95 REF DETAIL "A" 4 HYUNDAI MicroElectronics 64LQFP 12.00 BSC UNIT: MM 1.45 1.35 10.00 BSC 12.00 BSC 10.00 BSC 0-7° 0.15 0.05 SEE DETAIL "A" 1.60 max. 0.38 0.22 0.50 BSC 0.75 0.45 1.00 REF DETAIL "A" 4-1 GMS81508/16 1.5. PIN DESCRIPTION Classification No. Symbol I/O Descriptions Power 1 32 Vdd Vss I I I 2 MP 29 RESET 30 Xin 31 Xout I 24 23 22 21 28 27 26 25 4 3 12 11 10 9 8 7 6 5 17 18 19 20 14 13 15 16 EC0 EC2 T1O T3O INT0 INT1 INT2 INT3 AVref AVss AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 Srdy Sclk Sout Sin PWM0 PWM1 BUZ WDTO I I O O I I I I I I I I I I I I I I I/O I/O O I O O O O Power Supply Input Pin(4.5~5.5V) Ground(0V) Controls Microprocess Mode of the Chip At "H" input : Single Chip Mode At "L" input : Microprocess Mode In the state of "L" level, system enter to the reset state. This chip has an internal clock generating circuit. To control generating frequency, an external ceramic or a quartz crystal oscillator is connected between Xin and Xout pins. If external clock is used, the clock source should be connected to the Xin pin and the Xout pin should be left open. Event Counter Source Clock Input Pin System Control or Clock Timer Ext. Interrupt A/D Converter Serial I/O P.W.M Buzzer W.D.T I I Timer Counter Overflow Output Pin External Interrupt Request Signal Input Pin Reference Voltage Input Pin for A/D Converter Ground Level Input Pin for A/D Converter Analog Voltage Input Pin for A/D Converter Receive Enable Output Pin Serial Clock Output Pin Serial Data Output Pin Serial Data Input Pin PWM Pulse Output Pin Buzzer Driving Frequency Output Pin Watch dog Timer Overflow Output Pin 5 HYUNDAI MicroElectronics Classification I/O Port 6 No. Symbol I/O 49 : 56 R00 : R07 I/O 41 : 48 R10 : R17 I/O 33 : 40 R20 : R27 I/O 57 : 64 R30 : R37 I/O 28 : 21 20 : 13 12 : 9 8 : 5 R40 : R47 R50 : R57 R60 : R63 R64 : R65 Description I/O R0 Port ( Can be determined I/O by R0DD ) In MP mode, This port functions as 8-bit data bus for the CPU. (D0~D7) R1 Port ( Can be determined I/O by R1DD ) In MP mode, This functions as 8-bit lower address output pins. (A0~A7) R2 Port ( Can be determined I/O by R2DD ) In MP mode, This functions as 8-bit higher address output pins.(A8~A15) R3 Port ( Can be determined I/O by R3DD ) In MP mode, This port functions as 8-bit control bus for the CPU. R4 Port ( Can be determined I/O by R4DD ) I/O R5 Port ( Can be determined I/O by R5DD ) I I/O R6 Port Input Only R6 Port ( Can be determined I/O by R6DD ) GMS81508/16 2. FUNCTIONS 2.1. REGISTERS 6 registers are built-in the CPU of G8MC. Accumulator(A), Index register X, Y, Stack Pointer (SP) and Program Status Word(PSW) consists of 8-bit registers. Program Counter(PC) consists of 16bit registers. The contents of these registers are undefined after RESET. 15 87 0 PCH PCL Program 7 0 A 15 A - Register 8 7 0 Y ( YA 16bit Accumulator ) A 7 0 X - Register X 7 0 Y Y - Register 7 0 Stack SP 7 V G Pointer 0 Program Status Word PSW N Counter B H I Z C Carry Flag Zero Flag Interrupt Enable Flag Half Carry Flag Break Flag G ( Direct Page ) Flag Overflow Flag Negative Flag 7 HYUNDAI MicroElectronics 2.1.1. A - Register The accumulator is the 8-bit general purpose register. This is used register for data operation, data transfer, temporary saves and conditional judgment. Accumulator can be used as a 16-bit register with Y register and has a lower 8-bit data. In case of multiplication instruction(MUL), it works as a multiplier. After execution of MUL instruction, Accumulator has lower 8-bit data of the results(16-bit). In case of division instruction(DIV), it has the lower 8-bit of dividend (16-bit) 2.1.2. X- Register In index addressing mode, this register is executed as a 8-bit index register within direct page(RAM area). also, In indirect addressing mode, it is destination address register. This register can be used as a increment, decrement, comparison, and data transfer function. In case of division instruction(DIV), it works as a divisor. 2.1.3. Y- Register In index addressing mode, this register is executed as a index register. In case of 16-bit operation instruction, this register has upper 8-bit of YA (16-bit accumulator). In case of multiplication instruction(MUL), this register is executed as a multiplicand register. After multiplication operation, it has the upper 8-bit of the result. In case of division instruction, it is executed as a dividend(upper 8-bit). After division operation, it has quotient. This register can be used as a loop counter of conditional branch command. (e.g. DBNE Y, rel) 2.1.4. Stack Pointer The stack pointer(SP) is an 8-bit register used during subroutine calling and interrupts. When branching out from an on-going routine to subroutine or interrupt routine, it is necessary to remember the return address. normally, internal RAM is used for storing the return address and this area is called stack area. SP is pointer to show where the stack data are stored within the stack area. The stack area is located in 1-Page of internal RAM. SP must be initialized by S/W because the contents of SP is undefined after RESET. ex) LDX TXSP #0FEH ;0FEH -> X register ;X -> SP caution) You can't use !01FFH as stack. If you use this area, mal-function would be occurred. 8 GMS81508/16 Stack Address ( 0100H 01FFH ) 15 8 7 0 SP 01H Hardware fixed The bellows shows data store and restore sequence to/from stack area. Interrupt M (sp) ( PCH ) M (sp) ( PCL ) M (sp) ( PSW ) sp sp 1 sp sp 1 sp sp 1 sp sp 1 sp sp 1 sp sp 1 RETI ( PSW ) M (sp) ( PCL ) M (sp) M (sp) ( PCL ) ( PCH) M (sp) Subroutine CALL M (sp) ( PCH ) sp sp 1 sp sp 1 sp sp 1 sp sp 1 RET ( PCL ) PUSH M (sp) A ( X, M (sp) sp Y, A sp 1 ( PCH) PSW ) M (sp) POP A ( X, sp A Y, PSW ) sp 1 M (sp) 9 HYUNDAI MicroElectronics 2.1.5. Program Counter The program counter(PC) is a 16-bit counter which consists of 8-bit register PCH and PCL. The addressing space is 64K bytes. This counter indicates the address of the next instruction to be executed. In reset state, the program counter (PC) has reset routine address in address FFFFH and FFFEH . 2.1.6. Program Status Word PSW is an 8-bit register which is composed of flags to maintain the condition of the processor immediately after an operation. After RESET, The contents of PSW is set to "00H". PSW 7 6 5 4 3 2 1 0 N V G B H I Z C Carry Flag ( C ) After an operation, it is set to "1" when there is a carry from bit7 of ALU or not a borrow. SETC,CLRC instructions allow direct access for setting and resetting. it can be used as a 1-bit accumulator. It is a branch condition flag of BCS, BCC instructions. Zero Flag ( Z ) After an operation including 16-bit operation, it is set to "1" when the result is “0”. It is a branch condition flag of BEQ, BNE. Interrupt Enable Flag ( I ) This flag is used to enable/disable all interrupts except interrupt caused by BRK instruction. When this flag is "1", it means interrupt enable condition. When an interrupt is accept, this flag is automatically set to "0" thereby preventing other interrupts. also it is set to "1" by RETI instruction. This flag is set and cleared by EI, DI instructions. Half Carry Flag ( H ) After an operation, it is set when there is a carry from bit3 of ALU or is not a borrow from bit4 of ALU. It can not be set by any instruction. it is cleared by CLRV instruction like V flag. 10 GMS81508/16 Break Flag ( B ) This flag is set by BRK (S/W interrupt) instruction to distinguish BRK and TCALL instruction having the same vector address. Direct Page Flag ( G ) This flag assign direct page (0-page, 1-page) for direct addressing mode. When G-flag is "0", the direct addressing space is in 0-page(0000H~00FFH). When G-flag is "1", the direct addressing space is in 1-page(0100H~01FFH). It is set and cleared by SETG, CLRG instruction Overflow Flag ( V ) This flag functions when one word is added or subtracted in binary with the sign. When results exceeds +127 or -128, this flag is set. When BIT instruction is executed, The bit6 of memory is input into V-flag. This flag is cleared by CLRV instruction, but set instruction is not exist. It is a branch condition flag of BVS, BVC. Negative Flag ( N ) N-flag is set when the result of a data transfer or operation is negative (bit7 is “1”). it means the bit-7 of memory is sign bit. thereby data is valid in the range of -128 ~ +127. When BIT instruction is executed, The bit7 of memory is input into N-flag. Set or clear instruction is not exist. It is a branch condition flag of BPL, BMI instruction. 11 HYUNDAI MicroElectronics 2.2. MEMORY SPACE All RAM ,ROM,I/O, Peripheral Register are placed in the same memory area. Therefore, same instructions enable both data transfer and operation without the need to distinguish memory and I/O. The program counter of GMS81508/16 consists of 16-bit and memory addressing space is 64K byte. 2.2.1. RAM area RAM(includes stack area) is 448 Bytes ( 0000H 01FFH ). The internal RAM is used for data storage, subroutine calling or stack area when interrupts occur. When RAM is used as the stack area, the depth of the subroutine "nesting" and the interrupt levels should be kept in mind in order to avoid destruction of the RAM contents. 2.2.2. Peripheral Register area Address 00C0H 00FFH are assigned for peripheral register. 2.2.3. Program ROM area PCALL subroutines must be located in PCALL area ( FF00 FFBF ). TCALL vector area ( FFC0 FFDF ) has the vector address corresponding to TCALL H H H H instruction. Interrupt Vector area ( FFE0 FFFF H 12 H ) has the vector address of interrupts, inclusive RESET. GMS81508/16 Absolute Address !0000H !00C0H RAM (192 byte) 0-Page Peripheral Registers Direct Page(dp) !0100H RAM(STACK) (256 byte) 1-Page !0200H Not Used Area !C000H Program ROM !E000H !FF00H PCALL Area !FFC0H TCALL Vector Area !FFE0H Interrupt Vector Area U-Page G M S 8 1 5 0 8 G M S 8 1 5 1 6 VECTOR TABLE TCALL Address FFC0H - FFC1H FFC2H - FFC3H FFC4H - FFC5H FFC6H - FFC7H FFC8H - FFC9H FFCAH - FFCBH FFCCH - FFCDH FFCEH - FFCFH FFD0H - FFD1H FFD2H - FFD3H FFD4H - FFD5H FFD6H - FFD7H FFD8H - FFD9H FFDAH - FFDBH FFDCH - FFDDH FFDEH - FFDFH Vector TCALL 15 TCALL 14 TCALL 13 TCALL 12 TCALL 11 TCALL 10 TCALL 9 TCALL 8 TCALL 7 TCALL 6 TCALL 5 TCALL 4 TCALL 3 TCALL 2 TCALL 1 TCALL 0 INTERRUPT Address Vector FFE0H - FFE1H not used FFE2H - FFE3H not used FFE4H - FFE5H Serial I/O FFE6H - FFE7H Basic Interval Timer FFE8H - FFE9H Watch Dog Timer FFEAH - FFEBH A/D Converter FFECH - FFEDH Timer 3 FFEEH - FFEFH Timer 2 FFF0H - FFF1H Timer 1 FFF2H - FFF3H Timer 0 FFF4H - FFF5H Ext. Int. 3 FFF6H - FFF7H Ext. Int. 2 FFF8H - FFF9H Ext. Int. 1 FFFAH - FFFBH Ext. Int. 0 FFFCH - FFFDH not used FFFEH - FFFFH RESET 13 HYUNDAI MicroElectronics 2.2.4. Peripheral Register List Address Register Name SYMBOL R/W RESET VALUE 7 6 5 4 3 2 1 0 00C0H R0 PORT DATA REGISTER R0 R/W Undefined 00C1H R0 PORT I/O DIRECTION REGISTER R0DD W 0 0 0 0 0 0 0 0 00C2H R1 PORT DATA REGISTER R0 R/W Undefined 00C3H R1 PORT I/O DIRECTION REGISTER R0DD W 0 0 0 0 0 0 0 0 00C4H R2 PORT DATA REGISTER R0 R/W Undefined 00C5H R2 PORT I/O DIRECTION REGISTER R0DD W 0 0 0 0 0 0 0 0 00C6H R3 PORT DATA REGISTER R0 R/W Undefined 00C7H R3 PORT I/O DIRECTION REGISTER R0DD W 0 0 0 0 0 0 0 0 00C8H R4 PORT DATA REGISTER R4 R/W Undefined 00C9H R4 PORT I/O DIRECTION REGISTER R4DD W 0 0 0 0 0 0 0 0 00CA H R5 PORT DATA REGISTER R5 R/W Undefined 00CB H R5 PORT I/O DIRECTION REGISTER R5DD W 0 0 0 0 0 0 0 0 00CC H R6 PORT DATA REGISTER R6 R/W Undefined 00CD H R6 PORT I/O DIRECTION REGISTER R6DD W 0 0 0 0 - - - - 00D0H PORT R4 MODE REGISTER PMR4 W 0 0 0 0 0 0 0 0 00D1H PORT R5 MODE REGISTER PMR5 W - - 0 0 - - - - 00D2H TEST MODE REGISTER TMR W - - - - - 0 0 0 BASIC INTERVAL REGISTER BITR R Undefined CLOCK CONTROL REGISTER CKCTLR W - - 0 1 0 1 1 1 WDTR W - 0 1 1 1 1 1 1 00D3H 00E0H 14 WATCH DOG TIMER 00E2H TIMER MODE REGISTER 0 TM0 R/W 0 0 0 0 0 0 0 0 00E3H TIMER MODE REGISTER 2 TM2 R/W 0 0 0 0 0 0 0 0 00E4H TIMER0 DATA REGISTER TDR0 R/W Undefined 00E5H TIMER1 DATA REGISTER TDR1 R/W Undefined 00E6H TIMER2 DATA REGISTER TDR2 R/W Undefined 00E7H TIMER3 DATA REGISTER TDR3 R/W Undefined 00E8H A/D CONVERTER MODE REGISTER ADCM R/W - - 0 0 0 0 0 1 00E9H A/D CONVERTER DATA REGISTER ADR R Undefined 00EA H SERIAL I/O MODE REGISTER SIOM R/W - 0 0 0 0 0 0 1 GMS81508/16 Address Register Name SYMBOL R/W RESET VALUE 7 6 5 4 3 2 1 0 00EB H SERIAL I/O REGISTER SIOR R/W Undefined 00EC H BUZZER DRIVER REGISTER BUR W Undefined 00F0H PWM0 DATA REGISTER PWMR0 W Undefined 00F1H PWM1 DATA REGISTER PWMR1 W Undefined 00F2H PWM CONTROL REGISTER PWMCR W 00 00F3H INTERRUPT MODE REGISTER IMOD R/W - - 0 0 0 0 0 0 00F4H INTERRUPT ENABLE REGISTER LOW IENL R/W 0 0 0 0 - - - - 00F5H INTERRUPT REQUEST FLAG REGISTER LOW IRQL R/W 0 0 0 0 - - - - 00F6H INTERRUPT ENABLE REGISTER HIGH IENH R/W 0 0 0 0 0 0 0 0 00F7H INTERRUPT REQUEST FLAG REGISTER HIGH IRQH R/W 0 0 0 0 0 0 0 0 00F8H EXT. INTERRUPT EDGE SELECTION REGISTER IEDS W 0 0 0 0 0 0 0 0 -: Not Used Write Only Register can not be accessed by bit manipulation instruction. 15 HYUNDAI MicroElectronics 2.3. CLOCK GENERATION CIRCUIT The clock generation circuit of GMS81508/16 consists of oscillation circuit, prescaler, Basic Interval Timer. The source clock of peripherals is provided by 11-bit prescaler. OSC Circuit Clock Pulse Generator Internal System Clock IFBIT Prescaler ENPCK MUX 8 B.I.T.(8) BTCL W.D.T.(6) WDTCL 6 Comparator IFWDT 6 CKCTLR 0 1 2 3 4 5 6 7 WDTR 6 To RESET Circuit Internal Data Bus 2.3.1. Oscillation Circuit The clock signal incoming from crystal oscillator or ceramic resonator via Xin and Xout or from external clock via Xin is supplied to Clock Pulse Generator and Prescaler. The internal system clock for CPU is made by Clock Pulse Generator, and several peripheral clock is divided by prescaler. The clock generation circuit of crystal oscillator or ceramic resonator is shown in below. Cout Xout Xout Xin GND Open External Clock Xin Cin Crystal Oscillator or Ceramic Resonator In STOP Mode, The oscillation is stopped, External clock Xin pin goes to "L" level status, and Xout pin goes to "H" level state. 16 GMS81508/16 2.3.2. Prescaler The prescaler consists of 11-bit binary counter, and input clock is supplied by oscillation circuit. The frequency divided by prescaler is used as a source clock for peripherals. PS1 fex PS2 PS3 PS4 PS5 PS6 PS7 PS8 PS9 PS10 PS11 ENPCK B.I.T. 8 PS1 PS0 PS2 PS3 PS4 PS5 PS6 PS7 PS8 PS9 PS10 PS11 Internal Data Bus Peripherals Frequency-Divided Outputs of Prescaler fex ( 8 ) Interval Period PS1 PS2 250 500 4 PS3 PS4 1 2 PS5 2 1 4 500 250 PS6 8 125 PS7 PS8 16 62.5 PS9 15.36 32 64 31.25 PS10 PS11 128 7.18 256 3.59 The peripheral clock supplied from prescaler can be stopped by ENPCK. (However, PS11 cannot be stopped by ENPCK) CKCTLR 7 6 <00D3H> W 5 W 4 WDTON ENPCK W 3 W 2 W 1 BTCL BTS2 BTS1 W 0 BTS0 Enable Peripheral Clock 0 : stop 1 : supply 17 HYUNDAI MicroElectronics 2.4. BASIC INTERVAL TIMER The Basic Interval Timer(B.I.T.) has 8-bit binary counter. The operations is shown below. . Generates reference time interval interrupt request as a timer. . The counting value of B.I.T. can be read. ( Note; The writing at same address overwrites the CKCTLR.) . The overflow of B.I.T be used the source clock of Watch Dog Timer. Internal Data Bus CKCTLR PS4 PS5 PS6 PS7 PS8 PS9 PS10 PS11 WDTON ENPCK BTCL BTS2 BTS1 BTS0 Same address when read, it can be read as counter value. When write, it can be write as control register. BITR MUX bit7 bit6 bit5 bit3 bit4 bit2 bit1 bit0 IFBIT Internal Data Bus 2.4.1. Control of Basic Interval Timer The Basic Interval Timer is free running timer. When the counting value is changed "0FFH" to "00H" , The interrupt request flag is generated. The counter can be cleared by setting BTCL (Bit 3 of CKCTLR) and the BTCL is auto-cleared after 1 machine cycle. The initial state (after Reset) of BTCL is “0”. The input clock of Basic Interval Timer is selected by BTS2~BTS0 (Bit2~0 of CKCTLR) among the prescaler outputs (PS4~PS11). The Basic Interval Timer Register (BITR) can be read. The CKCTLR and the BITR have a same address (00D3H). So, If you write to this address, the CKCTLR would be controlled. If you read this address, the counting value of BITR would be read. CLOCK CONTROL REGISTER CKCTLR 7 6 W W W W W W 5 4 3 2 1 0 WDTON ENPCK BTCL BTS2 BTS1 BTS0 <00D3H> B.I.T. input clock selection B.I.T. CLEAR ( When writing ) 0 : B.I.T. Free-run 1 : B.I.T. Clear ( auto cleared after 1 machine cycle ) 18 GMS81508/16 BASIC INTERVAL TIMER DATA REGISTER BITR R R R R R R R R 7 6 5 4 3 2 1 0 <00D3H> B.I.T data 2.5. WATCH DOG TIMER The Watch Dog Timer is a means of recovery from a system problem. In this Device, the Watch Dog Timer consists of 6-bit binary counter, 6-bit comparator and watch dog timer register(WDTR). The source clock of WDT is overflow of Basic Interval Timer. The interrupt request of WDT is generated when the counting value of WDT equal to the contents of WDTR( bit0~5). This can be used as s/w interrupt or MICOM RESET signal(Watch Dog Function). 2.5.1. Control of Watch Dog Timer It can be used as 6-bit timer or WDT according to bit5(WDTON) of Clock Control Register (CKCTLR). The counter can be cleared by setting WDTCL ( Bit 6 of WDTR) and the WDTCL is auto-cleared after 1 machine cycle. The initial state (after Reset) of WDTCL is “0”. CLOCK CONTROL REGISTER CKCTLR W W W W W W 7 6 5 4 3 2 1 0 WDTON ENPCK BTCL BTS2 BTS1 BTS0 <00D3H> WDT ON 0 : 6-bit Timer 1 : Watch Dog Timer WATCH DOG TIMER REGISTER WDTR W W W W W W W W 7 6 5 4 3 2 1 0 WDTCL WDTR5 WDTR4 WDTR3 WDTR2 WDTR1 WDTR0 <00E0H> Watch Dog Timer Clear 0 : free run 1 : W.D.T counter clear Determines the interval of W.D.T Interrupt 19 HYUNDAI MicroElectronics The interval of WDT interrupt is decided by the interrupt interval of Basic Interval Timer and the contents of WDTR. The interval of WDT = The contents of WDTR The interval of B.I.T. Caution) Do not use the contents of WDTR = "0" The relationship between the input clock of B.I.T and the output of W.D.T. (@8MHz) BTS2 BTS1 BTS0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 B.I.T. Input Clock The cycle of B.I.T. ) PS5 ( 4 ) PS6 ( 8 ) PS7 ( 16 ) PS8 ( 32 ) PS9 ( 64 ) PS10 ( 128 ) PS11 ( 256 ) 1,024 2,048 4,096 8,192 16,384 32,768 65,536 PS4 ( 2 The cycle of W.D.T.(max) 64,512 129,024 258,048 516,096 1,032,192 2,064,384 4,128,768 512 32,256 2.5.2. The output of WDT signal The overflow of WDT can be output through R54/WDT O port by setting bit4 of PMR5(WDTS) to "1". PORT R5 MODE REGISTER 7 6 - - W W 5 4 3 2 1 0 - - - - PMR5 <00D1H> BUZS WDTS R54/WDT O Selection 0 : R54 ( Input / Output ) 1 : WDTO ( Output ) 20 GMS81508/16 2.6. TIMER The GMS81508/16 has four multi-functional 8-bit binary timers(Timer0~Timer3). Timer0 (or Timer2) is can be used as a 16-bit timer/event counter with Timer1(or Timer3). The Timer0-1 and Timer2-3 have same functions and structures. So, We will explains about Timer0 and Timer1 only. Internal Data Bus 7 8 TDR0 TM0 8 8 TDR1 8 Data Reg. 0 Data Reg. 1 8 8 Comparator 0 Comparator 1 8 8 7 6 5 4 3 2 1 0 T0CN T0ST CAP0 2 EC0 PS2 PS4 PS6 ck ck T0 T1 MUX Clea 0 MUX 1 Clea 2 IFT1 PS2 PS4 PS6 16bit Mode 16bit Mode MUX T1ST INT0 1 MUX 0 INTR0 EDGE 1 MUX 0 T1O Operation Mode of Timer Timer0,Timer2 IFT0 F/F Timer1,Timer3 -. 8-bit Interval Timer -. 8-bit Interval Timer -. 8-bit Event Counter -. -. 8-bit input capture 8-bit rectangular pulse output -. 16-bit Interval Timer -. 16-bit Event Counter -. 8-bit rectangular pulse output 21 HYUNDAI MicroElectronics TIMER MODE REGISTER 0,2(TM0,TM2) R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 TM0 <00E2H> CAP0 T1ST T1SL1 T1SL0 T0ST T0CN T0SL1 T0SL0 Input Capture Selection 0 : Timer/Counter 1 : Input Capture T0 Input Clock Selection 00 : EC0 01 : PS2 ( 500 ) 10 : PS4 ( 2 ) 11 : PS6 ( 8 ) T1 Start/Stop control 0 : Cout Stop 1 : Counting start after clearing T1 T0 Start/Stop control 0 : COUNT Stop 1 : COUNT Start T1 Input Clock Selection 00 : Connection to T0 (16bit Mode ) 01 : PS2 ( 500 ) 10 : PS4 ( 2 ) 11 : PS6 ( 8 ) T0 Start/Stop control 0 : Count Stop 1 : Counting start after clearing T0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 TM2 <00E3H> CAP2 T3ST T3SL1 T3SL0 T2ST T2CN T2SL1 T2SL0 Input Capture Selection 0 : Timer/Counter 1 : Input Capture T2 Input Clock Selection 00 : EC2 01 : PS2 ( 500 ) 10 : PS4 ( 2 ) 11 : PS6 ( 8 ) T3 Start/Stop control 0 : Cout Stop 1 : Counting start after clearing T3 T2 Start/Stop control 0 : COUNT Stop 1 : COUNT Start T3 Input Clock Selection 00 : Connection to T2 (16bit Mode ) 01 : PS2 ( 500 ) 10 : PS4 ( 2 ) 11 : PS6 ( 8 ) T2 Start/Stop control 0 : Count Stop 1 : Counting start after clearing T2 TIMER DATA REGISTER(TDR0 ~ TDR3) TDR0~3 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 <00E4H~00E7H > ( READ ) Count Value Read 22 ( WRITE) Modulo Data Write GMS81508/16 2.6.1. Control of Timer T0 ( T1 ) consists of 8-bit Binary Up-Counter. When the counting value of Timer0 , Timer1 and Timer0-1(16bit) become equal to the contents of Timer Data Register(TDR0,TDR1,TDR0-1) value, the counter is cleared to "00H" and restarts count-up operation. At this time, Interrupt request (IFT0 or IFT1) is generated. TDR0 VALUE MATCH MATCH MATCH T0 VALUE 00H Clear Clear Interrupt Clear Interrupt Interrupt IFT0 Interval Period Any of the PS2, PS4, PS6 or external clock can be selected as the clock source of T0 by bit1(T0SLI) and bit0(T0SL0) of TM0. Any of the PS2, PS4, PS6 or overflow of T0 can be selected as the clock source of T1 by bit5(T1SL1) and bit4(T1SL0) of TM0. When the overflow of T0 is selected as input clock of T1, Timer0-1 operates as 16 -bit timer. In this case, Timer0-1 only is controlled by T0ST,T0CN and the interrupt vector is Timer0 vector. The operation of T0, T1 is controlled by bit3(T0ST), bit2(T0CN) and bit6(T1ST) of TM0. T0CN controls count stop/start without clearing counter. T0ST and T1ST control count stop/start after timer clear. In order to enable count-up of timer , T0CN, T0ST and T1ST should become “1”. In order to start count-up after clearing of counter, T0ST or T1ST should be set to "1" after set to "0" temporarily. TDR0 VALUE MATCH MATCH T0 VALUE 00H Clear Clear Clear Interrupt IFT0 “0” T0ST Interrupt “1” Clear & Start “0” T0CN “1” Start COUNTER Count Stop Count Stop Count 23 HYUNDAI MicroElectronics By read Timer Data Register(TDR0~3),The counting value of timer can be read at any time. 2.6.2. Interval Timer The interrupt cycle is determined by the source clock of timer and the contents of TDR. Interrupt cycle = source clock the contents of TDR In order to write data to TDR, you have to stop timer. otherwise, TDR value is invalid. Maximum Interrupt Cycle according to source clock @ fex=8MHz 8-bit TIMER Mode 16-bit TIMER Mode source clock ) 2 ) 8 ) 0.5 ) 2 ) 8 ) PS2 ( 0.5 T0,T2 PS4 ( PS6 ( PS2 ( T1,T3 PS4 ( PS6 ( max. count 512 2,048 128 512 2,048 128 source clock ) 2 ) 8 ) PS2 ( 0.5 PS4 ( PS6 ( max. count 131,072 524,288 32,768 2.6.3. Event Counter The event counter operates in the same way as the interval timer except it counts the external event input from R44/EC0 and R45/EC1 port. it only counts at the falling edge of event input clock. In order to input of external event clock, the relevant Port Mode Register(bit4,bit5 of PMR4) is set to "1". TDR value should be initialized to “FFH” because timer is cleared when it equals to TDR value, but if you want to use interrupt, TDR value should be written to "1H~FFH". 2.6.4. Pulse Output A pulse width 50% cycle duty is output to the R46/T1 O or R47/T3 O port and reverse the output when timer interrupt is generated. This creates a pulse period which is two times that of the timer interrupt cycle. The output pulse period is determined by the source clock of timer and the contents of TDR. output period = source clock( ) the contents of TDR 2 In order to output of pulse, the bit6,bit7 of PMR4 is set to "1". 2.6.5. Input Capture This function measures the period or width of pulse input from external INT. (R40/INT0, R42/INT2) port. The period of pulse is measured by selecting rising edge or falling edge of the interrupt edge select register(IEDS) and the width of pulse is measured by selecting both edge of IEDS. The external interrupt is generated at the valid edge according to IEDS. At this time, The counting value of timer is loaded into TDR and counter is cleared and restarts count-up. 24 GMS81508/16 Rising Edge Falling Edge Period “H”Width “L”Width R40/INT0 or R42/INT2 Both Edge Timer Operation the counting value of timer is latched timer is cleared to 00H timer restart count-up PORT R4 MODE REGISTER W W W W W W W W 7 6 5 4 3 2 1 0 T3S T1S PMR4 <00D0H> EC2S EC0S INT3S INT2S INT1S INT0S R40 / INT0 Selection 0 : R40 ( Input / Output ) 1 : INT0 ( Input ) R47 / T3 Selection 0 : R47 ( Input / Output ) 1 : T3 ( Output ) R46 / T1 Selection 0 : R46 ( Input / Output ) 1 : T1 ( Output ) R44/ EC0 Selection 0 : R44 ( Input / Output ) 1 : EC0 ( Input ) R42 / INT2 Selection 0 : R42 ( Input / Output ) 1 : INT2 ( Input ) R45/ EC2 Selection 0 : R45 ( Input / Output ) 1 : EC2 ( Input ) 25 HYUNDAI MicroElectronics 2.7. EXTERNAL INTERRUPT An interrupt request is generated when a level-change from "H" to "L" or "L" to "H" of INT0,INT1,INT2,INT3 pin is detected. The edge of external interrupt is selected by interrupt edge selection register(IEDS) and ports(R40,R41,R42,R43) corresponding to INT0,INT1,INT4,INT3 are determined as a input port for external interrupt by bit0~3 of port4 mode register(PMR4). W W W W W W W W 7 6 5 4 3 2 1 0 T3S T1S PMR4 <00D0H> EC2S EC0S INT3S INT2S INT1S INT0S R40 / INT0 Selection 0 : R40 ( Input / Output ) 1 : INT0 ( Input ) R43 / INT3 Selection 0 : R43 ( Input / Output ) 1 : INT3 ( Input ) R42 / INT1 Selection 0 : R42 ( Input / Output ) 1 : INT2 ( Input ) R41 / INT1 Selection 0 : R41 ( Input / Output ) 1 : INT1 ( Input ) EXT. INTERRUPT EDGE SELECTION REGISTER W W W W W W W W 7 6 5 4 3 2 1 0 IEDS <00F8H> INT3 Edge Selection 00 : 01 : Falling 10 : Rising 11 : Falling & Rising 26 IED3H IED3L IED2H IED2L IED1H IED1L IED0H IED0L INT2 Edge Selection 00 : 01 : Falling 10 : Rising 11 : Falling & Rising INT0 Edge Selection 00 : 01 : Falling 10 : Rising 11 : Falling & Rising INT1 Edge Selection 00 : 01 : Falling 10 : Rising 11 : Falling & Rising GMS81508/16 2.8. A/D CONVERTER A/D Converter has an 8-bit resolution, and input is possible up to 8 channel. A/D Converter consists of Analog Input Multiplexer, A/D convert Mode Register, Resistance Ladder, Sample and Holder, Successive Approximation Circuit and A/D Conversion Data Register. Ladder Resistor Decoder AVref AVss AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 COMPARATOR MUX S/H Control Register - - Successive Approximation Circuit IFA A/D Conversion Data Register(8bit) ADEN ADS2 ADS1 ADS0 ADST ADSF Internal Data Bus 2.8.1. Control of A/D Converter The analog input is selected by bit2~4 of A/D Converter Mode Register(ADCM). This bits chooses among AN0~AN7. The other analog pins which are not used not A/D conversion be used as normal port. The A/D Conversion is started by setting A/D Conversion Start bit (ADST) to "1"(only for ADEN=1). After A/D Conversion is started, ADST is cleared by hardware. During A/D Conversion, when ADST is set to "1", A/D Conversion starts again from the beginning. The analog input voltage and the reference voltage are compared and the result is stored in the A/D Converter Data Register(ADR) and ADSF(bit0 of ADCM) is set to "1". The A/D interrupt request is generated at the completion of A/D conversion. The result of the conversion is obtained by reading out the A/D register(ADR). 27 HYUNDAI MicroElectronics A/D CONVERTER MODE REGISTER(ADCM) ADCM <00E8H> - - R/W R/W R/W R/W R/W R/W R 7 6 5 4 3 2 1 0 A/D Converter Enable bit 0 :Disable A/D Converter 1 : Enable A/D Converter ADEN ADS2 ADS1 ADS0 ADST ADSF A/D Conversion Status bit 0 : during A/D Conversion 1 : completed A/D Conversion A/D Converter input select 000 : channel 0(AN0) 001 : channel 1(AN1) 010 : channel 2(AN2) 011 : channel 3(AN3) 100 : channel 4(AN4) 101 : channel 5(AN5) 110 : channel 6(AN6) 111 : channel 7(AN7) A/D Conversion Start bit 0 : invalid 1 : Start A/D Conversion (after 1 cycle, be cleared to "0") A/D CONVERTER DATA REGISTER(ADR) R R R R R R R R 7 6 5 4 3 2 1 0 ADR <00E9H> A/D Conversion Data 28 GMS81508/16 2.9. SERIAL I/O The serial I/O is 8-bit clock synchronous type and consists of serial I/O register, serial I/O mode register, clock selection circuit octal counter and control circuit. 7 6 6 Srdy SM1 SM0 Internal Data BUS 0 SCK1 SCK0 SIOST SOSF SIOM Srdy SM1 SM0 2 PS3 Control PS4 MUX PS5 Octal Counter Circuit IFSIO Exclk Sclk R Srdy0 Q S Srdy In Sout Sin 7 6 5 4 3 2 1 0 SIOR Internal Data BUS 8 29 HYUNDAI MicroElectronics Serial I/O Mode Register This register controls serial I/O function. According to SCK1 and SCK0, the internal clock or external clock can be selected. SIOM <00EAH> R/W R/W R/W R/W R/W R/W R 7 6 5 4 3 2 1 0 Srdy SM1 SM0 SCK1 SCK0 SIOST SIOSF Serial Transmission Status Flag 0 : during transmission 1 : finished R53/Srdy Selection 0 : R53 1 : Srdy Serial Transmission Start 0 : Invalid 1 : Start(After one SCK, becomes”0”) Serial Operation Mode 00 : Normal Port(R52,R51,R50) 01 : Sending Mode(Sclk,Sout,R50) 10 : Receiving Mode(Sclk,R51,Sin) 11 : Sending & Receiving M d (S lk S Si ) Serial Transmission Clock Selection 00 : PS3 ( 1 ) 01 : PS4 ( 2 ) 10 : PS5 ( 4 ) 11 : External Clock Serial I/O Data Register The Serial I/O Data Register (SIOR) is a 8-bit shift register. First LSB is send or is received. R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 SIOR <00EBH> At transmittion Sending Data at Sending Mode Receiving Data at Receiving Mode 30 GMS81508/16 2.9.1. Data Transmission/Receiving Timing The serial transmission is started by setting SIOST(bit1 SIOM) to ”1”. After one cycle of SCK, SIOST is cleared automatically to “0”. The serial output data from 8-bit shift register is output at falling edge of Sclk. and input data is latched at rising edge of Sclk. When transmission clock is counted 8 times, serial I/O counter is cleared as “0”. Transmission clock is halted in “H” state and serial I/O interrupt (IFSIO) occurred. Input Clock Sclk SIOST Output Sout D0 D1 D2 D3 D4 D5 D6 D7 D2 D3 D4 D5 D6 D7 Latch Sin D0 D1 IFSIO Timing Diagram of Serial I/O 2.9.2. The Serial I/O operation by Srdy pin transmission clock = external clock The Srdy pin becomes "L" by SIOST = "1". This signal tells to the external system that this device is ready for serial transmission. The external system detects the "L" signal and starts transmission. The Srdy pin becomes "H" at the first rising edge of transmission clock. SIOST Srdy(Output) transmission clock = internal clock The I/O of Srdy pin is input mode. When the external system is ready to for serial transmission, the "L" level is inputted at this pin. At this time this device starts serial transmission. SIOST Srdy(Input) 31 HYUNDAI MicroElectronics 2.9.3. The method of Serial I/O Select transmission/receiving mode <Notice> When external clock is used, the frequency should be less than 1MHz and recommended duty is 50%. In case of sending mode, write data to be send to SIOR. Set SIOST to “1” to start serial transmission. <Notice > If both transmission mode is selected and transmission is performed simultaneously it would be made error. The SIO interrupt is generated at the completion of SIO and SIOSF is set to “1”. In SIO interrupt service routine, correct transmission should be tested. In case of receiving mode, the received data is acquired by reading the SIOR. 2.9.4. The Method to Test Correct Transmission with S/W Serial I/O Interrupt Service Routine SIOSF 0 1 SE=0 Abnormal Write SIOM SR 1 0 Normal Operation Overrun Error Serial Method to Test Transmission. Note) SE: Interrupt Enable Regist Low IENL ( Bit3 ) SR : Interrupt Request Flag Regist Low IRQL ( Bit3 ) 32 GMS81508/16 2.10. PWM PWM(Pulse Width Modulation) has a 8-bit resolution and the PS8,PS9,PS10,PS11 of the prescaler can be selected as input clock PWM. Internal Data Bus PWMR0 Overflow S Comparator Q Polarity R PS8 PS9 PS10 PS11 PWM0 Counter MUX P1CK1 P1CK0 P0CK1 P0CK0 EN1 EN0 POL1 POL0 PWMCR PS8 PS9 PS10 PS11 Counter MUX Overflow S Comparator Q R Polarity PWM1 PWMR1 Internal Data Bus 2.10.1. Controls of PWM The input clock is selected by PWM Control Register (PWMCR), and the width of pulse is determined by the PWM Register (PWMR). The pulse period according to input clock are as follows. Input clock PS8 (32 ) PS9 (64 ) PS10 (128 ) PS11 (256 ) PWM Period 8,192 16,384 32,768 65,536 Bit2 (EN0) and bit3 (EN1) of PWM control Register (PWMCR) determine the operation channel of PWM. When EN0=0 and EN1=0, PWM does not executed. The EN0 and EN1 are Enable bit of PWM channel 0 and channel 1 respectively. When EN0=1, PWM channel0 executes. When EN1=1, PWM channel1 executes. POLO and POL1 are a polarity control bit of channel0 and channel1. When they are 0, LOW active. When 1, HIGH active. PWMCR becomes "00h" in reset state. 33 HYUNDAI MicroElectronics (a) Active Low (b) Active High period period pulse width pulse width Counter Load Value + 1 100[%] Duty Cycle = 256 PWM CONTROL REGISTER W 7 W W 6 W 5 W 4 W W 3 2 EN1 EN0 W 1 0 PWMCR <00F2H> PICK1 PICK0 P0CK P0CK 1 0 POL1 POL0 PWM0 Output Polarity 0 : Active Low 1 : Active High PWM1 Clock Selection 00 : PS8 01 : PS9 10 : PS10 11 : PS11 PWM1 Output Polarity 0 : Active Low 1 : Active High PWM0 Clock Selection 00 : PS8 01 : PS9 10 : PS10 11 : PS11 PWM Enable Flag 00 : Disable 01 : PWM0 10 : PWM1 11 : PWM0,PWM1 PWM DATA REGISTER PWMR0 PWMR1 W W W W W W W W 7 6 5 4 3 2 1 0 <00F0H> <00F1H> 34 PWM DATA GMS81508/16 2.11. BUZZER DRIVER Buzzer driver consist of 6 bit binary counter, Buzzer Register(BUR), and selector of clock. The wide range frequency(500Hz~250KHz) can be generated using programmable counter. PORT R55 is assigned for output port of Buzzer Driver by setting bit5 of PMR5($00D1H) to "1". Internal Data Bus WtBUR BUCK1 BUCK0 BU5 BU4 BU3 BU2 4 5 BU1 BU0 6 PS4 PS5 PS6 PS7 0 MUX 1 2 3 T Q Buzzer Output 6bit Counter PORT R5 MODE REGISTER W W 7 6 5 4 3 2 1 0 - - BUZ WDTO - - - - PMR5 <00D1H> R55 / BUZ Selection 0 : R55 ( Input / Output ) 1 : BUZ ( Output ) BUZZER DATA REGISTER W W W W W W W W 7 6 5 4 3 2 1 0 BU5 BU4 BU3 BU2 BU1 BU0 BUR BUCK1 BUCK0 <00ECH> Buzzer Source Clock Selection 00 : PS4 01 : PS5 10 : PS6 11 : PS7 Buzzer Count Data 35 HYUNDAI MicroElectronics 2.11.1. Buzzer Driver Operation The bit0-5 of Buzzer Register (BUR) determines output frequency for buzzer driving. The frequency is calculated as shown bellows. N = BUR data freq. = 1/(source clock ✕ N ✕ 2) The bit6 and bit7 of Buzzer register (BUR) selects the source clock of the buzzer counter among PS4 (2us), PS5 (4us), PS6 (8us) and PS7 (16us). The buzzer counter is cleared by Wt signal of BUR and starts the counting. also, It is cleared by counter overflow, and continues count-up to output the rectangular wave of duty 50%. * Caution: don't use BUR register as 00H. (counter reset state) The output frequency of buzzer according to Buzzer Register bit5 - bit0 (fex = 8 MHz) REG. LOAD DEC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 36 REG. LOAD HEX 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 OUTPUT FREQUENCY[KHz] PS4 PS5 PS6 PS7 (2us) (4us) (8us) (16us) 250 125 62.5 31.25 125 62.5 31.25 15.626 83.333 41.666 20.834 10.416 62.5 31.25 15.626 7.812 50 25 12.5 6.25 41.666 20.834 10.416 5.208 35.714 17.858 8.928 4.464 31.25 15.626 7.812 3.906 27.778 13.888 6.944 3.472 25 12.5 6.25 3.126 22.728 11.364 5.682 2.84 20.834 10.416 5.682 2.604 19.23 9.616 4.808 2.404 17.858 8.928 4.464 2.232 16.666 8.334 4.166 2.084 15.626 7.812 3.906 1.9541 14.706 7.352 3.676 1.838 13.888 6.944 3.472 1.736 13.158 6.579 3.288 1.644 12.5 6.25 3.124 1.562 11.904 5.952 2.976 1.488 11.364 5.682 2.840 1.420 10.87 5.434 2.718 1.358 10.416 5.208 2.604 1.302 10 5 2.5 1.250 9.616 4.808 2.404 1.202 9.26 4.630 2.314 1.158 8.928 4.464 2.232 1.116 8.62 4.310 2.156 1.078 8.334 4.166 2.084 1.042 8.064 4.032 2.016 1.008 7.812 3.906 1.954 0.976 REG. LOAD DEC 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 REG. LOAD HEX 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F OUTPUT FREQUENCY[KHz] PS4 PS5 PS6 PS7 (2us) (4us) (8us) (16us) 7.576 3.788 1.894 0.947 7.352 3.676 1.838 0.919 7.142 3.571 1.786 0.893 6.944 3.472 1.736 0.868 6.756 3.378 1.689 0.845 6.578 3.289 1.645 0.822 6.41 3.205 1.602 0.801 6.3 3.125 1.563 0.781 6.098 3.049 1.524 0.762 5.952 2.976 1.488 0.744 5.814 2.907 1.453 0.727 5.682 2.841 1.421 0.710 5.556 2.778 1.389 0.694 5.434 2.717 1.359 0.679 5.32 2.660 1.33 0.665 5.208 2.604 1.302 0.651 5.102 2.551 1.276 0.638 5 2.5 1.25 0.625 4.902 2.451 1.225 0.613 4.808 2.404 1.202 0.601 4.716 2.358 1.179 0.590 4.63 2.315 1.157 0.579 4.546 2.273 1.136 0.568 4.464 2.232 1.116 0.558 4.386 2.193 1.096 0.548 4.31 2.155 1.078 0.539 4.238 2.119 1.059 0.530 4.166 2.083 1.042 0.521 4.098 2.049 1.025 0.512 4.032 2.016 1.008 0.504 3.968 1.984 0.992 0.496 GMS81508/16 2.12. INTERRUPTS The interrupts are usually used when the processing routine has the higher priority than on-going program and a routine muse be executed at specific interval. 2.12.1. Interrupt Circuit Configuration and Kinds GMS81508/16 Interrupt circuits consists of Interrupt Enable Register (IENH,IENL), Interrupt Request Register (IRQH,IRQL), priority circuit and selecting circuit. The configuration of Interrupt circuit is shown in below. Data BUS 8 6 8 IMOD IENH 0 1 2 3 4 5 6 7 RESET 0 1 2 3 4 5 4 IRQH 7 IFT3 T3R IFT2 T2R IFT1 T1R IFT0 T0R INT3 INT3R INT2 INT2R INT1 INT1R PRIORITY INT0 INT0R CONTROL IFA IFWDT IFBIT IFS AR Standby Mode Release to CPU 0 7 I-FLAG BRK WDTR BITR SR 12 4 IRQL 7 6 5 4 4 IENL 4 INTERRUPT VECTOR ADDRESS GEN. 8 Data BUS 37 HYUNDAI MicroElectronics Interrupt Source The interrupts sources are external interrupt source(INT0, INT1,INT2,INT3), peripheral function source (T0,T1,T2,T3,B.I.T.,W.D.T.,SIO,A/DC) and software interrupt source(BRK). After reset input(RESET), the program is executed from the address in reset vector table like general interrupts. Type Mask Non Maskable Priority Interrupt Request Source Vector Vector H L 1 RST Reset Pin FFFFH FFFEH 2 INT0R External Interrupt 0 FFFBH FFFAH 3 INT1R External Interrupt 1 FFF9H FFF8H 4 INT2R External Interrupt 2 FFF7H FFF6H H/W 5 INT3R External Interrupt 3 FFF5H FFF4H Interrupt 6 T0R Timer 0 FFF3H FFF2H 7 T1R Timer 1 FFF1H FFF0H 8 T2R Timer 2 FFEFH FFEEH 9 T3R Timer 3 FFEDH FFFCH 10 AR A/D Converter FFEBH FFEAH 11 WDTR Watch Dog Timer FFE9H FFE8H 12 BITR Basic Interval Timer FFE7H FFE6H 13 SR Serial I/O FFE5H FFE4H BRK Break Instruction FFDFH FFDEH S/W Interrupt Non Maskable 2.12.2. Interrupt Control The interrupts is controlled by the interrupt master enable flag I-Flag(3'rd bit of PSW), interrupt enable register(IENH,IENL), interrupt request register(IRQH,IRQL) except RESET and S/W interrupt. Interrupt Enable Register ( IENH, IENL) This register is composed of interrupt enable flags of each interrupt source, this flags determines whether an interrupt will be accepted or not. when enable flag is "0", an interrupt corresponding interrupt source is prohibited. 38 GMS81508/16 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 T0E T1E T2E T3E IENH <00F6H> INT0E INT1E INT2E INT3E R/W R/W R/W R/W - - - - 7 6 5 4 3 2 1 0 SE - - - - IENL <00F4H> AE WDTE BITE Interrupt Masking Flag 0 : Interrupt Disable 1 : Interrupt Enable Interrupt Request Flag Register ( IRQH, IRQL) Whenever interrupt request is generated, the interrupt request flag is set. The request flag maintains '1" until interrupt is accepted. The accepted interrupt request flag is automatically cleared by interrupt process cycle. Interrupt Request Flag Register ( IRQH, IRQL) is Read/ Write Register. So, it is possible to be checked and changed by program. R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 T0R T1R T2R T3R IRQH <00F7H> INT0R INT1R INT2R INT3R R/W R/W R/W R/W - - - - 7 6 5 4 3 2 1 0 SR - - - - IRQL <00F5H> AR WDTR BITR Interrupt Request Flag 0 : Disable 1 : Enable 2.12.3. Interrupt Priority When two or more interrupts requests are generated at the same sampling point, the interrupt having the higher priority is accepted. The interrupt priority is determined by H/W. however, multiple priority processing through software is possible by using interrupt control flags(IENH, IENL, I-flag) and interrupt mode register(IMOD). 39 HYUNDAI MicroElectronics 2.12.4. Interrupt Sequence When interrupt is accepted, the on-going process is stopped and the interrupt service routine is executed. After the interrupt service routine is completed it is necessary to restore everything to the state before the interrupt occurred. As soon as an interrupt is accepted, the contents of the program counter and the program status word are saved in the stack area. At the same time, the contents of the vector address corresponding to the accepted interrupt, which is in the interrupt vector table, enters into the program counter and interrupt service routine is executed. In the interrupt service routine, the corresponding interrupt request flag is cleared and interrupt master enable flag(I-flag) becomes "0", thereby another interrupts are not accepted before I-flag is set to "1" by program. In order to execute the interrupt service routine, it is necessary to write the jump address(the first address of the interrupt service routine) in vector table corresponding to each interrupt. System Clock Instruction Fetch 1 Cycles 0 12 Cycles A command before Interrupt 8 Cycles Interrupt Process Step Int.request Sampling 21 Cycles Interrupt Overhead : 9 40 Interrupt Accept Timing The valid timing after executing Interrupt control Flag I-Flag is valid, after EI, DI executed IENH, IENL register is valid after next instruction Interrupt routine GMS81508/16 System Clock Instruction Fetch Address Bus pc Data Bus not Used sp PCH sp-1 sp-2 PCL PSW V.L V.L V.H ADL new pc ADH Opcode Internal Read Internal Write Interrupt Process Step Interrupt Service Routine V.L, V.H is Vector Address, ADL, ADH is start Address of Interrupt Service Routine as Vector Contents Interrupt Process Step Timing 2.12.5. Software Interrupt The interrupt is the lowest priority order software interrupt by BRK instruction. B-flag is set. Interrupt vector of BRK instruction is shared with the vector of TCALL 0. Each processing step is determined by B-Flag as a below. B-Flag ? BRK or TCALL0 0 1 BRK Interrupt Routine TCALL 0 Routine RETI RET Execution of BRK/ TCALL0 41 HYUNDAI MicroElectronics 2.12.6. Multiple Interrupt When an interrupt is accepted, and program flow goes to the interrupt service routine. The interrupt master enable flag(I-flag) is automatically cleared and other interrupts are inhibited. When interrupt service is completed by RETI instruction, I-flag is set automatically. If other interrupts are generated during interrupt service, The interrupt having higher priority is accepted when the previous interrupt service routine is completed. In order to multiple interrupts, I-flag must be cleared by EI instruction within the interrupt routine. Then, The higher priority interrupt is accepted among the interrupts that interrupt request flag is "1". Interrupt Mode Register ( IMOD) if IM1,IM0 is selected as a "01", the interrupt selected by IP0~IP3 can be accepted and other interrupts are not accepted. Using this register, we can change the interrupt priority order by s/w. IMOD <00F3H> R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 IM1 IM0 IP3 IP2 IP1 IP0 Interrupt Mode Definition 00 : Mode 0 (Priority by H/W) 01 : Mode 1(Definition by IP3 IP0) 1- : Inhibit Interrupt 42 Interrupt Definition Selection 0001 : INT0 0010 : INT1 0011 : INT2 0100 : INT3 0101 : TIMER0 0110 : TIMER1 0111 : TIMER2 1000 : TIMER3 1001 : ADC 1010 : WDT 1011 : BIT 1100 : SIO GMS81508/16 When multiple interrupt is accepted, it is possible to change Interrupt Accept Mode. In case of multiple interrupt at hardware priority accept mode(Mode0) Main Program ( Mode 0 ) 1’st INT. Routine ( Mode 0 ) 2’nd INT. Routine ( Mode 0 ) 3’rd INT. Routine EI Interrupt EI Interrupt EI Interrupt In case of multiple interrupts nest H/W priority accept mode (Mode0) and S/W selection accept mode(Mode1) Main Program ( Mode 0 ) 1’st INT. Routine ( Mode 0 ) 2’nd INT. Routine ( Mode 1 ) 3’rd INT. Routine EI Interrupt EI Stacking IMOD Change Mode EI Interrupt Interrupt Reload IMOD 43 HYUNDAI MicroElectronics 2.13. STANDBY FUNCTION To save the consuming power of device, GMS81508/16 has STOP Mode. In this mode, the execution of program is stopped. Stop Mode entered by STOP instruction. OSC. Circuit Clock Pulse GEN. MUX halt Prescaler STOP CPU Clock S Q S Q R Q R Q Basic Interval Timer IFBIT Overflow Detection RESET Release Signal from Interrupt Circuit At STOP Mode, Device Operation State. Peripheral Function Oscillator CPU Clock RAM, Register Retain I/O Port Retain Prescaler Basic Interval Timer Serial I/O WDT, Timer, A/DC,PWM, Buzzer Driver 44 STOP Mode Operation( External Clock Selection) Address Bus, Data Bus Retain Rd, Wt, R/W Retain HALT, BRQ, BAK Active C "L" level SYNC "H" level GMS81508/16 2.13.1. STOP Mode STOP Mode can be entered by STOP instruction during program execution. In STOP mode, oscillator is stopped to make all clocks stop, which leads to the mode requiring much less power consumption. All register and RAM data are preserved. Caution) NOP instruction have to be written more than 2 to next lines of STOP instruction. 2.13.2. STOP Mode Release The release of STOP mode is done by reset input or interrupt. When there is a release signal of STOP mode, the instruction execution is started after stabilization oscillation time set by program. After releasing STOP mode, instruction execution is different by I-Flag(bit 2 of PSW). If I-Flag = “1” entered Interrupt Service Routine, If I-Flag = “0” execute program from next instruction of STOP instruction. STOP Mode Release Release Factor RESET INT0,INT1 INT2,INT3 Serial I/O Release Method By RESET pin=Low level, and Device is initialized. In the state of enable flag=1 corresponding to each interrupt at the edge. When Serial I/O is executed by external clock, STOP mode is released. STOP System Clock Release Signal by interrupt Stabilization oscillation time + 8 Cycles RESET STOP Mode Stabilization Oscillation Time determined by program. Release Timing of STOP Mode 45 HYUNDAI MicroElectronics When release the STOP Mode, to secure oscillation stabilization time, we use Basic Interval Timer. So, before execution STOP instruction, we must select suitable B.I.T. clock for oscillation stabilization time. Otherwise, It is possible to release by only RESET input. Because STOP mode is released by interrupt, even if both of interrupt enable bit(IE) and interrupt request flag is "1", STOP mode can not be executed. STOP Command STOP Mode Interrupt Request IE ? 0 1 STOP Mode Release I-Flag ? 1 NOP Interrupt Service Routine NOP 46 STOP Mode Releasing Flow 0 GMS81508/16 2.14. RESET FUNCTION To reset the device, maintain the RESET="L" at least 8 machine cycle after power supplying and oscillation stabilization. RESET terminal is organized as schmitt input. If initial value is undefined, it is needed initialize by a S/W. System Clock RESET Instruction Fetch Address Bus ? ? Data Bus ? ? ? ? ? ? FFFE FE ADL FFFF ADH Start Opcode Internal Read RESET Process Step Main Program FFFE H, is vector address and ADL, ADH is start address of main program as vector contents RESET Operation Timing 47 HYUNDAI MicroElectronics 3. I/O PORTS There are 7-ports(R0~R6) in this device. This ports are double-functional ports and the function can be selected by program. The direction of ports is determined by Port Direction Register.(1=output, 0=input) The data that is written on the programmed output pin is stored in the port data register and is transferred to the output pin. When data is input to the programmed pin. data is read not from output pin but from port data register. therefore, previously output data can be read correctly regardless or the logical level of the pin due to output loading. Because the programmed input pin is floating, the value of the pin can be read correctly. When data is written to the programmed input pin, it is written only to the port data register and the pin remains floating. 3.1. R0 PORT R0 Port is composed of 8-bit programmable I/O pin. Register Name R0 I/O Direction Register R0 PORT Data Register Symbol R0DD R0 R/W W R/W Address 00C1H 00C0H Initial Value 0000 0000 Not initialized R0 PORT I/O DIRECTION REGISTER W W W W W W W W 7 6 5 4 3 2 1 0 R0DD R0DD7 R0DD6 R0DD5 R0DD4 R0DD3 R0DD2 R0DD1 R0DD0 <00C1H> Determines I/O of R0 port 0 : Input 1 : Output R0 PORT DATA REGISTER R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 R07 R06 R05 R04 R03 R02 R01 R00 R0 <00C0H> Port R0 output data 48 GMS81508/16 Pin Function According to Operation Modes PIN Single Chip Mode Microprocessor Mode R00/D0 I/O I/O R01/D1 I/O I/O R02/D2 I/O R03/D3 Programmable I/O Port I/O Data I/O Port from/to External Memory I/O I/O for CPU. R04/D4 I/O I/O R05/D5 I/O I/O R06/D6 I/O I/O R07/D7 I/O I/O 3.2. R1 PORT R1 Port is composed of 8-bit programmable I/O pin. Register Name R0 I/O Direction Register R0 PORT Data Register Symbol R1DD R1 R/W W R/W Address 00C3H 00C2H Initial Value 0000 0000 Not initialized R1 PORT I/O DIRECTION REGISTER W W W W W W W W 7 6 5 4 3 2 1 0 R1DD R1DD7 R1DD6 R1DD5 R1DD4 R1DD3 R1DD2 R1DD1 R1DD0 <00C3H> Determines I/O of R1 port 0 : Input 1 : Output R1 PORT DATA REGISTER R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 R17 R16 R15 R14 R13 R12 R1 R10 R1 <00C2H> Port R1 output data Pin Function According to Operation Modes 49 HYUNDAI MicroElectronics PIN Single Chip Mode Microprocessor Mode R10/A0 I/O O R11/A1 I/O O R12/A2 I/O R13/A3 Programmable I/O Port O low 8bit address of External Memory I/O O for CPU. R14/A4 I/O O R15/A5 I/O O R16/A6 I/O O R17/A7 I/O O 3.3. R2 PORT R2 Port is composed of 8-bit programmable I/O pin. Register Name R2 I/O Direction Register R2 PORT Data Register Symbol R2DD R2 R/W W R/W Address 00C5H 00C4H Initial Value 0000 0000 Not initialized R2 PORT I/O DIRECTION REGISTER W W W W W W W W 7 6 5 4 3 2 1 0 R2DD R2DD7 R2DD6 R2DD5 R2DD4 R2DD3 R2DD2 R2DD1 R2DD0 <00C5H> Determines I/O of R2 port 0 : Input 1 : Output R2 PORT DATA REGISTER R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 R27 R26 R25 R24 R23 R22 R21 R20 R2 <00C4H> Port R2 output data 50 GMS81508/16 Pin Function According to Operation Modes PIN Single Chip Mode Microprocessor Mode R20/A8 I/O O R21/A9 I/O O R22/A10 I/O R23/A11 Programmable I/O Port O upper 8bit address of External Memory I/O O for CPU. R24/A12 I/O O R25/A13 I/O O R26/A14 I/O O R27/A15 I/O O 3.4. R3 PORT R3 Port is composed of 8-bit programmable I/O pin. Register Name R3 I/O Direction Register R3 PORT Data Register Symbol R3DD R3 R/W W R/W Address 00C7H 00C6H Initial Value 0000 0000 Not initialized R3 PORT I/O DIRECTION REGISTER W W W W W W W W 7 6 5 4 3 2 1 0 R3DD R3DD7 R3DD6 R3DD5 R3DD4 R3DD3 R3DD2 R3DD1 R3DD0 <00C7H> Determines I/O of R3 port 0 : Input 1 : Output R3 PORT DATA REGISTER R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 R37 R36 R35 R34 R33 R32 R31 R30 R3 <00C6H> Port R3 output data 51 HYUNDAI MicroElectronics Pin Function According to Operation Modes PIN Single Chip Mode Microprocessor Mode R30 I/O O Rd : external memory read strobe R31 I/O O Wt : external memory write strobe R32 I/O O R/W :Read/Write cycle output pin of CPU R33 I/O O C : timing signal output pin R34 I/O O SYNC : op code fetch output pin of CPU R35 I/O O BRK : bus acknowledge output pin of CPU R36 I/O I BRQ : bus request input pin of CUP R37 I/O I HALT : CPU halt input pin Programmable I/O Port 3.5. R4 PORT R4 Port is composed of 8bit programmable I/O port and this port are double functional pin. Register Name R4 I/O Direction Register R4 Port Data Register Port R4 Mode Register Interrupt Edge Select Register Symbol R4DD R4 PMR4 IEDS R/W W R/W W R/W Address 00C9H 00C8H 00D0H 00F8H Initial Value 0000 0000 Not initialized 0000 0000 0000 0000 R4 PORT I/O DIRECTION REGISTER W W W W W W W W 7 6 5 4 3 2 1 0 R4DD R4DD7 R4DD6 R4DD5 R4DD4 R4DD3 R4DD2 R4DD1 R4DD0 <00C9H> Determines I/O of R4 port 0 : Input 1 : Output R4 PORT DATA REGISTER R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 R47 R46 R45 R44 R43 R42 R41 R40 R4 <00C8H> Port R4 output data 52 GMS81508/16 PORT R4 MODE REGISTER W W W W W W W W 7 6 5 4 3 2 1 0 T3S T1S PMR4 <00D0H> EC2S EC0S INT3S INT2S INT1S INT0S R40 / INT0 Selection 0 : R40 ( Input / Output ) 1 : INT0 ( Input ) R47 / T3 Selection 0 : R47 ( Input / Output ) 1 : T3 ( Output ) R41 / INT1 Selection 0 : R41 ( Input / Output ) 1 : INT1 ( Input ) R46 / T1 Selection 0 : R46 ( Input / Output ) 1 : T1 ( Output ) R42 / INT2 Selection 0 : R42 ( Input / Output ) 1 : INT2 ( Input ) R45/ EC2 Selection 0 : R45 ( Input / Output ) 1 : EC2 ( Input ) R43 / INT3 Selection 0 : R43 ( Input / Output ) 1 : INT3 ( Input ) R44/ EC0 Selection 0 : R44 ( Input / Output ) 1 : EC0 ( Input ) INTERRUPT EDGE SELECTION REGISTER W W W W W W W W 7 6 5 4 3 2 1 0 IEDS <00F8H> IED3H IED3L IED2H IED2L IED1H IED1L IED0H IED0L INT3 Edge Selection 01 : Falling 10 : Rising 11 : Falling & Rising INT2 Edge Selection 01 : Falling 10 : Rising 11 : Falling & Rising INT1 Edge Selection 01 : Falling 10 : Rising 11 : Falling & Rising INT0 Edge Selection 01 : Falling 10 : Rising 11 : Falling & Rising 3.6. R5 PORT R5 Port is composed of 8-bit programmable I/O port. R54,R55 is double functional pin. Register Name R5 I/O Direction Register R5 Port Data Register R5 Port Mode Register Symbol R5DD R5 PMR5 R/W W R/W W Address 00CBH 00CAH 00D1H Initial Value 0000 0000 Not initialized --00 ---- 53 HYUNDAI MicroElectronics R5 PORT I/O DIRECTION REGISTER W W W W W W W W 7 6 5 4 3 2 1 0 R5DD <00CBH> R5DD7 R5DD6 R5DD5 R5DD4 R5DD3 R5DD2 R5DD1 R5DD0 Determines I/O of R5 port 0 : Input 1 : Output R5 PORT DATA REGISTER R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 R57 R56 R55 R54 R53 R52 R51 R50 R5 <00CAH> Port R5 Output Data PORT R5 MODE REGISTER W W PMR5 7 6 5 4 3 2 1 0 <00D1H> - - BUZ WDTON - - - - R54 / WDTON Selection 0 : R54 ( Input / Output ) 1 : WDTON ( Output ) R55 / BUZ Selection 0 : R55 ( Input / Output ) 1 : BUZ ( Output ) 3.7. R6 PORT R6 Port consists of 4-bit Programmable I/O ports and 4-bit input only ports and this port can be used as a analog input port for A/D conversion by program. Register Name R6 I/O Direction Register R6 Port Data Register A/D Converter Mode Register 54 Symbol R/W Address Initial Value R6DD W 00CDH 0000 ---- R6 R/W 00CCH Not initialized ADCM W 00E8H --00 0001 GMS81508/16 R6 PORT I/O DIRECTION REGISTER W W W W 7 6 5 4 3 2 1 0 R6DD R6DD7 R6DD6 R6DD5 R6DD4 R6DD3 R6DD2 R6DD1 R6DD0 <00CDH> Determines I/O of R6 port 0 : Input 1 : Output R6 PORT DATA REGISTER R/W R/W R/W R/W R R R R 7 6 5 4 3 2 1 0 R47 R46 R45 R44 R43 R42 R41 R40 R6 <00CCH> Port R6 output data On the initial RESET, R60 can’t be used digital input port, because this port is selected as an analog input port by ADCM register. To use this port as a digital I/O port, change the value of lower 4 bits of ADCM(address 0E8H). On the other hand,R6 port, all eight pins can not be used as digital I/O port simultaneously. At least one pin is used as an analog input. UNUSED PORTS All unused ports should be set properly that current flow through port doesn't exist. First consider the setting the port as an input mode. Be sure that there is no current flow after considering its relationship with external circuit. In input mode, the pin impedance viewing from external MCU is very high that the current doesn’t flow. But input voltage level should be VSS or VDD. Be careful that if unspecified voltage, i.e. if unfirmed level voltage is applied to input pin, there can be little current ( max. 1mA at 2V) flow. If it is not appropriate to set as an input mode, then set to output mode considering there is no current flow. Setting to High or Low is decided considering its relationship with external circuit. For example, if there is external pull-up resistor then it is set to output mode, i.e. to High, and if there is external pull-down register, it is set to low. 55 HYUNDAI MicroElectronics 3.8. TERMINAL TYPES PIN TERMINAL TYPE Vdd Xin Xout Xin Vss Vss Xout STOP RESET MP MP 1 MUX 0 Data Bus R00 ~ R07 Data Bus Data REG. Data Bus Direction REG. Vdd Vss MUX Data Bus Rd Data Bus Rd 56 GMS81508/16 MP Vdd Address Bus R10 ~ R27 R20 ~ R27 MUX Data Bus Data REG. Data Bus Direction REG. Vss MUX Data Bus Rd From R30 ... Rd From R31 ... Wt From R32 ... R/W MP From R33 ... C From R34 ... SYNC Vdd From R35 ... BAK R30 R31 R32 R33 R34 R35 MUX Data Bus Data REG. Data Bus Direction REG. Vss MUX Data Bus Rd MP Vdd R36 R37 Data Bus Data REG. Data Bus Direction REG. Vss MUX Data Bus Rd to BRQ to HALT 57 HYUNDAI MicroElectronics Selection Vdd R40/INT0 R41/INT1 R42/INT2 R43/INT3 R44/EC0 R45/EC2 R50/Sin Data Bus Data REG. Data Bus Direction REG. Vss MUX Data Bus INT0 INT1 To R42 INT2 To R43 INT3 To R44 EC0 To R45 EC2 To R50 Sin To R40 To R41 Rd From R46 ... T1O From R47 ... T3O From R51 ... Sout R46/T1O R47/T3O R51/Sout R54/WDTO R55/BUZ R56/PWM0 R57/PWM1 From R54 ... WDTO Selection From R55 ... BUZ Vdd From R56 ... PWM0 MUX From R57 ... PWM1 Data Bus Data REG. Data Bus Direction REG. Vss MUX Data Bus Rd Selection Vdd sck o R52/Sclk MUX Data Bus Data REG. Data Bus Direction REG. MUX exck Data Bus MUX Rd sck i 58 Vss GMS81508/16 Selection Srdy Vdd Srdy o R53/Srdy MUX Data Bus Data REG. Data Bus Direction REG. Vss MUX Data Bus Rd Srdy in R60/AN0 R61/AN1 R62/AN2 R63/AN3 Data Bus Rd To A/D Converter Vdd R64/AN4 R65/AN5 R66/AN6 R67/AN7 Data Bus Data REG. Data Bus Direction REG. Vss MUX Data Bus Rd To A/D Converter 59 HYUNDAI MicroElectronics 4. ELECTRICAL CHARACTERISTICS 4.1. ABOULUTE MAXIMUM RATINGS Parameter Supply Voltage Input Voltage Storage Temperature Symbol Unit Ratings Vdd V -0.3 ~ 7.0 Vi V -0.3 ~ Vdd+0.3 Tstg °C -40 ~ 125 4.2. RECOMMENDED OPERATING CONDITIONS Parameter Symbol Unit Specifications Min. Typ. Max. Supply Voltage Vdd V 4.5 5.5 Operating Frequency fXin MHz 1 8 Operating Temperature Topr °C -20 85 4.3. A/D CONVERTER CHARACTERISTICS ( Vdd = 5V Parameter Pin Symbol 10%, Vss = 0, ,f (Xin) = 8 ) SPECIFICATION Unit Min. Analog Input Range AN0~AN7 VAIN Accuracy LSB Conversion Time Analog Power Suppiy Input Range 60 V AVref Tconv Vref V Vss Typ. ETC Max. Vref 3 20 Vdd GMS81508/16 4.4. DC CHARACTERISTICS , Ta = -2085,f (Xin) = 8 ) ( Vdd =5.0V±10%,Vss = 0 Parameter Symbol Pin Test Condition Unit Specifications Min. RESET,,R4,R5,R6 "H" Input voltage "L" Input voltage Vih Vil Typ. Max. 0.8Vdd Vdd 0.7Vdd Vdd Xin 0.9Vdd Vdd RESET,R4,R5,R6 0 0.12Vdd 0 0.3Vdd 0 0.1Vdd R0,R1,R2,R3 V R0,R1,R2,R3 V Xin "H" Input Leakage Current Iih all input pins Vi = Vdd -5 5 "L" Input Leakage Current Iil all input pins Vi = Vss -5 5 "H" output Voltage Voh R0,R1,R2,R3,R4,R5 Ioh = -2mA V Vdd-1 R0,R1,R2,R3,R4,R5 Iol = 5mA V "L" output Voltage Power Operating Idd Current STOP Istop Hysteresis VT+ ~ V T- all input = Vss RESET, V EC2,EC0,Sin,Sclk,INT0~3 RAM Data Retention Vram Vdd at clock stop 1.0 V 20 40 20 100 0.3 0.8 0.3 0.8 2.0 61 HYUNDAI MicroElectronics 4.5. AC CHARACTERISTICS 4.5.1. Input Conditions , Ta = -20 85,f (Xin) = 8 ) ( Vdd = 5.0V±10%, Vss = 0 Parameter Pin Operating Frequency Symbol Xin System Clock Unit SPECIFICATION MIN. TYP. MAX. fcp MHz 1 - 8 tsys ns 500 - 250 tST ms Oscillation Stabilization Time Xin, Xout External Clock Pulse Width Xin tcpw ns External Clock Transition Time Xin trcp,tfcp ns Interrupt Pulse Width INT0~INT3 tIW tsys 2 RESET Input "L" Width RESET tRST tsys 8 Event Counter Input Pulse Width EC0,EC2 tECW tsys 2 Event Counter Transition Time EC0,EC2 trEC, tfEC ns 1/fcp tcpw 20 100 20 20 Timing Chart tcpw Vdd-0.5V 0.5 V Xin trcp INT3 INT2 INT1 INT0 tIW 0.8 Vdd 0.2 Vdd tRST RESET EC0 EC2 62 tfcp tIW 0.2 Vdd tECW tECW 0.8 Vdd 0.8 Vdd 0.2 Vdd trEC tfEC ETC GMS81508/16 4.5.2. Serial Transfer , Ta = -20 85,f (Xin) = 8 ) ( Vdd = 5.0V±10%, Vss = 0 Parametet Pin Symbol Unit SPECIFICATION etc MIN. TYP. MAX. Serial Input Clock Pulse Sclk tscyc ns 2tsys+200 - 8 Serial Input Clock Pulse Width Sclk tsckw ns tsys+70 - 8 Serial Input Clock Pulse Transition Time Sclk tfsck,trsck ns - 30 Sin Input Pulse Transition Time Sin tfsin,trsin ns - 30 Sin Input Setup time(Exnternal Sclk) Sin tsus ns 100 - Sin Input Setup time(Internal Sclk) Sin tsus ns 200 - Sin Input Hold Time Sin ths ns tsys+70 - Serial Output Clock Cycle Time Sclk tscyc ns 4tsys - Serial Output Clock Transition Time Sclk tsckw ns 2tsys-30 - Serial Output Clock Transition Time Sclk tfsck,trsck ns Serial Output Delay Time Sout trEC, tfEC ns - 16tsys 30 100 Serial I/O Timing Chart tscyc tfsck Sclk trsck tsckW tsckW 0.8 Vdd 0.2 Vdd tsus ths 0.2 Vdd 0.8 Vdd Sin tfsin trsin tds Sout 0.2 Vdd 0.8 Vdd 63 HYUNDAI MicroElectronics 4.5.3. Microprocessor Mode I/O Timing , Ta = -20 85,f (Xin) = 8 ) ( Vdd = 5.0V±10%, Vss = 0 Parameter Pin Control Clock Output Width C Address Output Delay Time Symbol Unit SPECIFICATION MIN. TYP. 90 - etc MAX. tCL ns A0 ~ A15 tdCA ns - 80 Data Output Delay Time D0 ~ D7 tdCD ns - 180 Data Output Hold Time D0 ~ D7 thw ns - 20 Data Input Setup Time D0 ~ D7 tsuR ns 80 - Data Input Hold Time D0 ~ D7 thR ns 15 - Rd Output Delay Time Rd tdRd tsys - 90 Wt Output Delay Time Wt tdWt tsys - 130 R/W Output Delay Time R/W tdRW tsys - 50 sync Output Delay Time SYNC tdsync tsys - 50 Timing Chart tsys tcw tcw 0.8Vdd C 0.2Vdd 0.8Vdd 0.2Vdd tdCA A0~A15 0.8Vdd 0.2Vdd tdCD thW write mode D0~D7 tstR read mode D0~D7 tdRd Rd 0.2Vdd tdWt Wt 0.2Vdd tdRW R/W 0.8Vdd 0.2Vdd tdsync 0.8Vdd SYNC 64 0.2Vdd thR GMS81508/16 4.5.4. Bus Holding Timing , Ta = -20 85,f (Xin) = 8 ) ( Vdd = 5.0V±10%, Vss = 0 Parameter Pin Symbol Unit SPECIFICATION MIN. TYP. 100 - etc MAX. BRQ Setup Time BRQ tSUB tsys BAK Delay Time BAK tdBA tsys - 50 BAK Release Delay Time BAK tdRBA tsys - 220 Bus(Address,Data) Control Release Delay Time D0 ~ D7 A0 ~ A15 Rd,Wt,R/W tdRA tsys - 210 Timing Chart Instruction Ececution Holding Cycle Instruction Ececution C 0.2Vdd 0.2Vdd SYNC tsuB BRQ tsuB 0.2Vdd 0.2Vdd tdRBA tdBA 0.8Vdd BAQ D0~D7 A0~A15 Rd Wt R/W tdRA Hi-Z 0.8Vdd 0.2Vdd 65 HYUNDAI MicroElectronics 5. INSTRUCTION SET 1. ARITHMETIC/ LOGIC OPERATION NO. MNEMONIC OP BYTE CYCLE CODE NO NO FLAG NVGBHIZC OPERATION 1 ADC #imm 04 2 2 2 ADC dp 05 2 3 3 ADC dp + X 06 2 4 4 ADC !abs 07 3 4 5 ADC !abs + Y 15 3 5 6 ADC [ dp + X ] 16 2 6 7 ADC [ dp ] + Y 17 2 6 8 ADC {X} 14 1 3 9 AND #imm 84 2 2 10 AND dp 85 2 3 11 AND dp + X 86 2 4 12 AND !abs 87 3 4 13 AND !abs + Y 95 3 5 14 AND [ dp + X ] 96 2 6 15 AND [ dp ] + Y 97 2 6 16 AND {X} 94 1 3 17 ASL A 08 1 2 18 ASL dp 09 2 4 19 ASL dp + X 19 2 5 20 ASL !abs 18 3 5 21 CMP #imm 44 2 2 22 CMP dp 45 2 3 23 CMP dp + X 46 2 4 24 CMP !abs 47 3 4 25 CMP !abs + Y 55 3 5 26 CMP [ dp + X ] 56 2 6 27 CMP [ dp ] + Y 57 2 6 28 CMP {X} 54 1 3 29 CMPX #imm 5E 2 2 30 CMPX dp 6C 2 3 31 CMPX !abs 7C 3 4 32 CMPY #imm 7E 2 2 33 CMPY dp 8C 2 3 34 CMPY !abs 9C 3 4 35 COM 2C 2 4 1’S Complement 36 DAA DF 1 3 Decimal adjust for addition N-----ZC 37 DAS CF 1 3 Decimal adjust for substraction N-----ZC 66 dp Add with carry. A (A) (M) C NV--H-ZC Logical AND A ( A ) ( M ) N-----Z- Arithmetic shift left C 7 6 5 4 3 2 1 0 ”0” N-----ZC Compare accumulator contents with memory contents (A) (M) N-----ZC Compare X contents with memory contents ( X) (M) N-----ZC Compare Y contents with memory contents ( Y) (M) N-----ZC : ( dp ) ( dp ) N-----Z- GMS81508/16 NO. MNEMONIC OP BYTE CYCLE CODE NO NO FLAG NVGBHIZC OPERATION 38 DEC A A8 1 2 Deccrement 39 DEC dp A9 2 4 40 DEC dp + X B9 2 5 41 DEC !abs B8 3 5 N-----Z- 42 DEC X AF 1 2 N-----Z- 43 DEC Y BE 1 2 44 DIV 9B 1 12 Divide : 45 EOR #imm A4 2 2 Exclusive OR 46 EOR dp A5 2 3 47 EOR dp + X A6 2 4 48 EOR !abs A7 3 4 49 EOR !abs + Y B5 3 5 50 EOR [ dp + X ] B6 2 6 51 EOR [ dp ] + Y B7 2 6 52 EOR {X} B4 1 3 53 INC A 88 1 2 54 INC dp 89 2 4 55 INC dp + X 99 2 5 N-----Z- 56 INC !abs 98 3 5 N-----Z- 57 INC X 8F 1 2 N-----Z- 58 INC Y 9E 1 2 59 LSR A 48 1 2 60 LSR dp 49 2 4 (M) 1 M N-----Z- N-----ZYA / X Q: A, Increment N-----Z7 6 dp + X 59 2 5 58 3 5 63 MUL 5B 1 9 Multiply Logical OR #imm 64 2 2 65 2 3 66 OR dp + X 66 2 4 67 OR !abs 67 3 4 68 OR !abs + Y 75 3 5 69 OR [ dp + X ] 76 2 6 70 OR [ dp ] + Y 77 2 6 71 OR { X } 74 1 3 72 ROL A 28 1 2 73 ROL dp 29 2 4 74 ROL dp + X 39 2 5 75 ROL !abs 38 3 5 76 ROR A 68 1 2 77 ROR dp 69 2 4 78 ROR dp + X 79 2 5 79 ROR !abs 78 3 5 5 4 3 2 1 0 C N-----ZC ”0” !abs dp N-----Z- Logical shift right LSR OR N-----ZC ( M ) 1 M LSR OR NV--H-Z- N-----Z- 62 65 R: Y (A)⊕(M) A 61 64 N-----ZN-----Z- A : YA Y A N-----Z- ( A ) ( M ) N-----Z- Rotate left through carry C 7 6 5 4 3 2 1 0 N-----ZC Rotate right through carry 7 6 5 4 3 2 1 0 C N-----ZC 67 NO. MNEMONIC OP BYTE CYCLE CODE NO NO 80 SBC #imm 24 2 2 81 SBC dp 25 2 3 82 SBC dp + X 26 2 4 83 SBC !abs 27 3 4 84 SBC !abs + Y 35 3 5 85 SBC [ dp + X ] 36 2 6 86 SBC [ dp ] + Y 37 2 6 87 SBC {X} 34 1 3 88 TST dp 4C 2 3 89 XCN CE 1 5 FLAG NVGBHIZC OPERATION Substract with carry A ( A ) ( M ) ( C ) NV--HZC Test memory contents for negative or zero ( dp ) 00H Exchange nibbles within the accumulator A ∼A A ∼A0 7 4 N-----ZN-----Z- 3 2. REGISTER / MEMORY OPERATION NO. MNEMONIC OP BYTE CYCLE CODE NO NO FLAG NVGBHIZC OPERATION 1 LDA #imm C4 2 2 2 LDA dp C5 2 3 3 LDA dp + X C6 2 4 4 LDA !abs C7 3 4 5 LDA !abs + Y D5 3 5 6 LDA [ dp + X ] D6 2 6 7 LDA [ dp ] + Y D7 2 6 8 LDA { X } D4 1 3 9 LDA { X }+ DB 1 4 X- register auto-increment : A 10 LDM E4 3 5 Load memory with immediate data : ( M ) 11 LDX #imm 1E 2 2 Load X-register 12 LDX dp CC 2 3 13 LDX dp + Y CD 2 4 14 LDX !abs DC 3 4 15 LDY #imm 3E 2 2 16 LDY dp C9 2 3 17 LDY dp + X D9 2 4 18 LDY !abs D8 3 4 19 STA dp E5 2 3 20 STA dp + X E6 2 4 21 STA !abs E7 3 4 22 STA !abs + Y F5 3 5 23 STA [ dp + X ] F6 2 6 24 STA [ dp ] + Y F7 2 6 25 STA { X } F4 1 3 26 STA { X }+ FB 1 4 dp,#imm OP 68 BYTE CYCLE Load accumulator A (M) N-----Z- X ( M ) , X X 1 imm (M) -------- N-----Z- Load Y-register Y (M) N-----Z- Store accumulator contents in memoy (M) A -------- X- register auto-increment : ( M ) A, X X 1 FLAG GMS81508/16 NO. MNEMONIC CODE NO NO NVGBHIZC OPERATION 27 STX dp EC 2 4 28 STX dp + Y ED 2 5 Store X-register contents in memoy 29 STX !abs FC 3 5 30 STY dp E9 2 4 31 STY dp + X F9 2 5 32 STY !abs F8 3 5 33 TAX E8 1 2 Transfer accumulator contents to X-register : A 34 TAY 9F 1 2 Transfer accumulator contents to Y-register : Y 35 TSPX AE 1 2 36 TXA C8 1 2 37 TXSP 8E 1 2 38 TYA BF 1 2 39 XAX EE 1 4 40 XAY DE 1 4 (M) X -------- Store Y-register contents in memoy (M) Y -------- X N-----Z- A N-----ZTransfer stack-pointer contents to X-register : X N-----Zsp Transfer X-register contents to accumulator: A X N-----ZTransfer X-register contents to stack-pointer: sp X N-----ZTransfer Y-register contents to accumulator: A Y N-----ZExchange X-register contents with accumulator :X -------A Exchange Y-register contents with accumulator :Y -------A 41 XMA dp BC 2 5 42 XMA dp+X AD 2 6 43 XMA {X} BB 1 5 44 XYX FE 1 4 Exchange memory contents with accumulator (M) A N-----Z- Exchange X-register contents with Y-register : Y -------- X 3. 16-BIT OPERATION OP NO. MNEMONIC BYTE CYCLE CODE NO NO 1 ADDW dp 1D 2 5 2 CMPW dp 5D 2 4 3 DECW dp BD 2 6 4 INCW dp 9D 2 6 5 LDYA dp 7D 2 5 6 STYA dp DD 2 5 7 SUBW 3D 2 5 dp OPERATION 16-Bits add without carry YA ( YA ) ( dp +1 ) ( dp ) Compare YA contents with memory pair contents : (YA)(dp+1)(dp) Decrement memory pair ( dp+1)( dp) ( dp+1) ( dp)1 Increment memory pair ( dp+1) ( dp) ( dp+1) ( dp ) 1 Load YA YA ( dp +1 ) ( dp ) Store YA ( dp +1 ) ( dp ) YA 16-Bits substact without carry YA ( YA )( dp +1) ( dp) FLAG NVGBHIZC NV--H-ZC N-----ZC N-----ZN-----ZN-----Z-------NV--H-ZC 69 HYUNDAI MicroElectronics 4. BIT MANIPULATION MNEMONIC NO. 1 AND1 2 AND1B M.bit 3 BIT 4 BIT !abs 5 CLR1 6 CLRA1 7 8 OP BYTE CYCLE CODE NO NO ( C ) ( M .bit ) : C ( C ) ( M .bit ) 8B 3 4 Bit AND C-flag 8B 3 4 Bit AND C-flag and NOT 0C 2 4 Bit test A with memory : 1C 3 5 dp.bit y1 2 4 A.bit 2B 2 2 CLRC 20 1 2 CLRG 40 1 2 M.bit dp 9 CLRV 10 EOR1 11 EOR1B 12 LDC CB 3 4 13 LDCB M.bit CB 3 4 14 NOT1 M.bit 4B 3 5 15 OR1 M.bit 6B 3 5 16 OR1B M.bit 6B 3 5 17 SET1 dp.bit x1 2 4 18 SETA1 A.bit 0B 2 2 19 SETC A0 1 2 20 SETG C0 1 2 21 STC EB 3 6 22 TCLR1 !abs 5C 3 6 23 TSET1 !abs 3C 3 6 M.bit M.bit M.bit M.bit 80 1 2 AB 3 5 AB 3 5 FLAG NVGBHIZC OPERATION Z :C (A) (M), N ( M ) , V( M ) 7 : ( M.bit ) Test and set bits with A (M), (M) A : ( M ) ( A ) -------C MM----Z- 6 “0” Clear A bit : ( A.bit ) “0” Clear C-flag : C “0” Clear G-flag : G “0” Clear V-flag : V “0” Bit exclusive-OR C-flag : C ( C ) ⊕ ( M .bit ) Bit exclusive-OR C-flag and NOT : C( C ) ⊕ (M .bit) Load C-flag : C ( M .bit ) Load C-flag with NOT : C ( M .bit ) Bit complement : ( M .bit ) ( M .bit ) Bit OR C-flag : C ( C ) ( M .bit ) Bit OR C-flag and NOT : C ( C ) ( M .bit ) Set bit : ( M.bit ) “1” Set A bit : ( A.bit ) “1” Set C-flag : C “1” Set G-flag : G “1” Store C-flag : ( M .bit ) C Test and clear bits with A : A ( M ) , ( M ) ( M ) ( A ) Clear bit -------C ---------------------0 --0-----0--0---------C -------C -------C -------C --------------C -------C ---------------------1 --1-----------N-----ZN-----Z- 5. BRANCH / JUMP OPERATION NO. MNEMONIC OP BYTE CYCLE CODE NO NO y2 2 4/6 OPERATION 1 BBC A.bit,rel 2 BBC dp.bit,rel y3 3 5/7 if ( bit ) 3 BBS A.bit,rel x2 2 4/6 Branch if bit set : 4 BBS dp.bit,rel x3 3 5/7 if ( bit ) 5 BCC rel 50 2 2/4 6 BCS rel D0 2 2/4 7 BEQ D0 2 2/4 70 rel Branch if bit clear : FLAG NVGBHIZC ( pc ) rel -------- 1 , then pc ( pc ) rel Branch if carry bit clear if ( C )0 , then pc( pc ) rel Branch if carry bit set if ( C )1 , then pc( pc ) rel Branch if equal if ( Z ) 1 , then pc ( pc ) rel -------- 0 , then pc ---------------------- GMS81508/16 NO. MNEMONIC OP BYTE CYCLE CODE NO NO 8 BMI rel 90 2 2/4 9 BNE rel 70 2 2/4 10 BPL rel 10 2 2/4 11 BRA rel 2F 2 4 12 BVC rel 30 2 2/4 13 BVS rel B0 2 2/4 14 CALL !abs 3B 3 8 15 CALL 5F 2 8 [dp] FLAG NVGBHIZC OPERATION Branch if minus if ( N ) 1 , then pc ( pc ) rel Branch if not equal if ( Z ) 0 , then Branch if minus if ( N ) 0 , then pc ( pc ) rel Branch always pc ( pc ) rel Branch if overflow bit clear if (V)0 , then pc( pc) rel Branch if overflow bit set if (V)1 , then pc( pc ) rel ------------------------------------------- Subroutine call ( pc ), spsp - 1, M( sp) ( pc ), sp sp -------if !abs, pc abs ; if [dp], pc ( dp ), pc M( sp) - 1, H L L H ( dp+1 ) . 16 CBNE dp,rel FD 3 5/7 17 CBNE dp+X,rel 8D 3 6/8 Compare and branch if not equal : 18 DBNE dp,rel AC 3 5/7 19 DBNE Y,rel 7B 2 4/6 20 JMP !abs 1B 3 3 21 JMP [!abs] 1F 3 5 22 JMP [dp] 3F 2 4 23 PCALL upage 4F 2 6 U-page call M( sp) ( pcH ), sp sp - 1, M( sp) ( pcL ), sp sp - 1, pcL ( upage ), pcH ”0FFH” . -------- 24 TCALL nA 1 8 Table call : (sp) ( pc H ), sp sp - 1, M( sp) ( pcL ),sp sp - 1, pcL (Table vector L), pcH (Table vector H) -------- if ( A ) if ( M ) then pc ( pc ) rel. 0, then pc ( pc ) rel. -------- Unconditional jump pc jump address n (M), Decrement and branch if not equal : -------- -------- 71 HYUNDAI MicroElectronics 6. CONTROL OPERATION & etc. MNEMONIC NO. 1 BRK OP BYTE CYCLE CODE NO NO 0F 1 8 FLAG NVGBHIZC OPERATION ---1-0-Software interrupt : B ”1”, M( sp) ( pc H ), sp sp - 1, M( s ) ( pcL ), sp sp - 1, M( sp) ( PSW ), sp sp -1, pcL ( 0FFDE H ) , pcH ( 0FFDFH) . “0” I “1” 2 DI 60 1 3 Disable interrups : I -----0-- 3 EI E0 1 3 Enable interrups : -----1-- 4 NOP FF 1 2 No operation 5 POP A 0D 1 4 6 POP X 2D 1 4 7 POP Y 4D 1 4 8 POP PSW 6D 1 4 9 PUSH A 0E 1 4 10 PUSH X 2E 1 4 11 PUSH Y 4E 1 4 12 PUSH PSW 6E 1 4 13 RET 6F 1 5 sp 1, A M( sp ) sp sp 1, X M( sp ) sp sp 1, Y M( sp ) sp sp 1, PSW M( sp ) M( sp ) A , sp sp 1 M( sp ) X , sp sp 1 M( sp ) Y , sp sp 1 M( sp ) PSW , sp sp 1 Return from subroutine spsp +1, pc M( sp ), sp sp +1, pc M( sp ) Return from interrupt sp sp +1, PSW M( sp ), spsp +1, pc M( sp ), sp sp +1, pc M( sp ) -------- sp -------- ( restored ) -------- -------- L H 14 RETI 7F 1 6 15 STOP 00 1 3 L 72 ( restored ) H Stop mode ( halt CPU, stop oscillator ) -------- GMS81508/16 HYUNDAI MicroElectronics 6. GMS81516AT (OTP) PROGRAMMING The GMS81516AT is one-time PROM (OTP) microcontroller with 16K bytes electrically programmable read only memory for the GMS81508/16 system evaluation, first production and fast mass production. To programming the OTP device, user can have two way. One is using the universal programmer which is support HME microcontrollers, other is using the general EPROM programmer. With these socket adapters, the GMS81516AT can easy be programming and verifying using Intel 27C256 EPROM mode on general-purpose PROM programmer. In assembler and file type, two files are generated after compiling. One is "*.HEX", another is "*.OTP". The "*.HEX" file is used for emulation in circuit emulator (CHOICE-Dr T M or CHOICE-Jr T M ) and "*.OTP" file is used for programming to the OTP device. Programming Procedure 1. Using the Universal programmer Third party universal programmer support to program the GMS81516AT microcontrollers and lists are shown as below. Manufacturer: A d v a n t e c h Web site: http://www.aec.com.tw Programmer: LabTool-48 Manufacturer: H i - L o s y s t e m s Web site: http://www.hilosystems.com.tw Programmer: ALL-11, GANG-08 Socket adapters are supported by third party programmer manufacturer. 2. Using the general EPROM(27C256) programmer The programming algorithm is simmilar with the standart EPROM 27C256. It gives some convience that user can use standard EPROM programmer. Make sure that 1ms programming pulse must be used, it generally called "Intelligent Mode". Do not use 100us programming pulse mode, "Quick Pulse Mode". When user use general EPROM programmer, socket adaper is essencially required. It convert pin to fit the pin of general 27C256 EPROM. Three type socket adapters are provided according to package variation as below table. Socket Adapter Package Type OA815A-64SD 64 pin SDIP OA815A-64QF-10 64 pin LQFP (10 x 10) OA815A-64QF 64 pin QFP (14 x 20) 1. Select the EPROM device and manufacturer on EPROM programmer (Intel 27C256). 2. Select the programming algorithm as an Intelligent mode (apply 1ms writing pulse), not a Quick pulse mode. 3. Load the file (*.OTP) to the programmer. 4. Set the programming address range as below table. Address Set Value Buffer start address 4000 H Buffer end address 7FFF H Device start address 4000 H 5. Mount the socket adapter with the GMS81516AT on the PROM programmer. 6. Start the PROM programmer to programming/ verifying. GMS81516AT PROGRAMMING MANUAL HYUNDAI MicroElectronics GMS81516AT EPROM PROGRAMMING DEVICE OVERVIEW The GMS81516AT is a high-performance CMOS 8-bit microcontroller with 16K bytes of EPROM. The device is one of GMS800 family. The HME GMS81516AT is a powerful microcontroller which provides a highly flexible and cost effective solution to many embedded control applications. The GMS81516AT provides the following standard features: 16K bytes of EPROM, 448 bytes of RAM, 56 I/O lines, 16-bit or 8-bit timer/counter, a precision analog to digital converter, PWM, on-chip oscillator and clock circuitry. PIN CONFIGURATION 64SDIP GMS81516AT 2 GMS81516AT EPROM PROGRAMMING HYUNDAI MicroElectronics 64QFP 64LQFP 3 HYUNDAI MicroElectronics GMS81516AT EPROM PROGRAMMING 64SDIP Package for GMS81516AT Pin No. 1 MCU Mode OTP Mode Pin No. 33 MCU Mode R27 I/O OTP Mode VDD - VDD - A15 I 2 MP I V PP - 34 R26 I/O A14 I 3 AVSS I (1) I 35 R25 I/O A13 I 4 AVREF I (1) I 36 R24 I/O A12 I 5 R67/AN7 I/O (1) I 37 R23 I/O A11 I 6 R66/AN6 I/O (1) I 38 R22 I/O A10 I 7 R65/AN5 I/O (1) I 39 R21 I/O A9 I 8 R64/AN4 I/O (1) I 40 R20 I/O A8 I 9 R63/AN3 I (1) I 41 R17 I/O A7 I 10 R62/AN2 I (1) I 42 R16 I/O A6 I 11 R61/AN1 I (1) I 43 R15 I/O A5 I 12 R60/AN0 I (1) I 44 R14 I/O A4 I 13 R57/PWM1 I/O (1) I 45 R13 I/O A3 I 14 R56/PWM0 I/O (1) I 46 R12 I/O A2 I 15 R55/BUZ I/O (1) I 47 R11 I/O A1 I 16 R54/WDTO I/O (1) I 48 R10 I/O A0 I 17 R53/SRDY I/O (1) I 49 R07 I/O O7 I/O 18 R52/SCLK I/O (1) I 50 R06 I/O O6 I/O 19 R51/SOUT I/O (1) I 51 R05 I/O O5 I/O 20 R50/SIN I/O (1) I 52 R04 I/O O4 I/O 21 R47/T3O I/O (2) I 53 R03 I/O O3 I/O 22 R46/T1O I/O (2) I 54 R02 I/O O2 I/O 23 R45/EC2 I/O CE I 55 R01 I/O O1 I/O 24 R44/EC0 I/O OE I 56 R00 I/O O0 I/O 25 R43/INT3 I/O (1) I 57 R37 I/O (1) I 26 R42/INT2 I/O (1) I 58 R36 I/O (1) I 27 R41/INT1 I/O (1) I 59 R35 I/O (1) I 28 R40/INT0 I/O (1) I 60 R34 I/O (1) I 29 RESET I (1) I 61 R33 I/O (1) I 30 X IN I (1) I 62 R32 I/O (1) I 31 XOUT O (3) O 63 R31 I/O (1) I 32 V SS - V SS - 64 R30 I/O (1) I NOTES: (1) These pins must be connected to V SS , because these pins are input ports during programming, program verify and reading (2) These pins must be connected to V D D . (3) X O U T pin must be opened during programming. 4 I/O: Input/Output Pin I: Input Pin O: Output Pin GMS81516AT EPROM PROGRAMMING HYUNDAI MicroElectronics 64QFP Package for GMS81516AT Pin No. MCU Mode OTP Mode (1) Pin No. I 33 MCU Mode R21 OTP Mode 1 R65/AN5 I/O I/O A9 I 2 R64/AN4 I/O (1) I 34 R20 I/O A8 I 3 R63/AN3 I (1) I 35 R17 I/O A7 I 4 R62/AN2 I (1) I 36 R16 I/O A6 I 5 R61/AN1 I (1) I 37 R15 I/O A5 I 6 R60/AN0 I (1) I 38 R14 I/O A4 I 7 R57/PWM1 I/O (1) I 39 R13 I/O A3 I 8 R56/PWM0 I/O (1) I 40 R12 I/O A2 I 9 R55/BUZ I/O (1) I 41 R11 I/O A1 I 10 R54/WDTO I/O (1) I 42 R10 I/O A0 I 11 R53/SRDY I/O (1) I 43 R07 I/O O7 I/O 44 R06 I/O O6 I/O 12 R52/SCLK I/O (1) I 13 R51/SOUT I/O (1) I 45 R05 I/O O5 I/O 14 R50/SIN I/O (1) I 46 R04 I/O O4 I/O 15 R47/T3O I/O (2) I 47 R03 I/O O3 I/O 16 R46/T1O I/O (2) I 48 R02 I/O O2 I/O 17 R45/EC2 I/O CE I 49 R01 I/O O1 I/O I/O 18 R44/EC0 I/O OE I 50 R00 I/O O0 19 R43/INT3 I/O (1) I 51 R37 I/O (1) I 20 R42/INT2 I/O (1) I 52 R36 I/O (1) I 21 R41/INT1 I/O (1) I 53 R35 I/O (1) I 22 R40/INT0 I/O (1) I 54 R34 I/O (1) I 23 RESET I (1) I 55 R33 I/O (1) I 24 X IN I (1) I 56 R32 I/O (1) I 25 XOUT O (3) O 57 R31 I/O (1) I 26 V SS - V SS - 58 R30 I/O (1) I 27 R27 I/O A15 I 59 VDD - VDD - 28 R26 I/O A14 I 60 MP I V PP I 29 R25 I/O A13 I 61 A V SS I (1) 30 R24 I/O A12 I 62 AV R E F I (1) I 31 R23 I/O A11 I 63 R67/AN7 I/O (1) I 32 R22 I/O A10 I 64 R66/AN6 I/O (1) I NOTES: (1) These pins must be connected to V SS , because these pins are input ports during programming, program verify and reading (2) These pins must be connected to V D D . (3) X O U T pin must be opened during programming. 5 I/O: Input/Output Pin I: Input Pin O: Output Pin HYUNDAI MicroElectronics GMS81516AT EPROM PROGRAMMING 64LQFP Package for GMS81516AT Pin No. 1 MCU Mode R63/AN3 OTP Mode I (1) Pin No. MCU Mode OTP Mode I 33 R17 I/O A7 I 2 R62/AN2 I (1) I 34 R16 I/O A6 I 3 R61/AN1 I (1) I 35 R15 I/O A5 I 4 R60/AN0 I (1) I 36 R14 I/O A4 I 5 R57/PWM1 I/O (1) I 37 R13 I/O A3 I 6 R56/PWM0 I/O (1) I 38 R12 I/O A2 I 7 R55/BUZ I/O (1) I 39 R11 I/O A1 I 8 R54/WDTO I/O (1) I 40 R10 I/O A0 I 9 R53/SRDY I/O (1) I 41 R07 I/O O7 I/O 10 R52/SCLK I/O (1) I 42 R06 I/O O6 I/O 11 R51/SOUT I/O (1) I 43 R05 I/O O5 I/O 12 R50/SIN I/O (1) I 44 R04 I/O O4 I/O 13 R47/T3O I/O (2) I 45 R03 I/O O3 I/O 14 R46/T1O I/O (2) I 46 R02 I/O O2 I/O 15 R45/EC2 I/O CE I 47 R01 I/O O1 I/O 16 R44/EC0 I/O OE I 48 R00 I/O O0 I/O 17 R43/INT3 I/O (1) I 49 R37 I/O (1) I 18 R42/INT2 I/O (1) I 50 R36 I/O (1) I 19 R41/INT1 I/O (1) I 51 R35 I/O (1) I 20 R40/INT0 I/O (1) I 52 R34 I/O (1) I 21 RESET I (1) I 53 R33 I/O (1) I 22 X IN I (1) I 54 R32 I/O (1) I 23 XOUT O (3) O 55 R31 I/O (1) I 24 V SS - V SS - 56 R30 I/O (1) I - 25 R27 I/O A15 I 57 VDD - VDD 26 R26 I/O A14 I 58 MP I VPP - 27 R25 I/O A13 I 59 A V SS I (1) I 29 R24 I/O A12 I 60 AV R E F I (1) I 29 R23 I/O A11 I 61 R67/AN7 I/O (1) I 30 R22 I/O A10 I 62 R66/AN6 I/O (1) I 31 R21 I/O A9 I 63 R65/AN5 I/O (1) I 32 R20 I/O A8 I 64 R64/AN4 I/O (1) I NOTES: (1) These pins must be connected to V SS , because these pins are input ports during programming, program verify and reading (2) These pins must be connected to V D D . (3) X O U T pin must be opened during programming. 6 I/O: Input/Output Pin I: Input Pin O: Output Pin GMS81516AT EPROM PROGRAMMING HYUNDAI MicroElectronics PIN FUNCTION (OTP Mode) V PP (Program Voltage) V P P is the input for the program voltage for programming the EPROM. CE ( Chip Enable) CE is the input for programming and verifying internal EPROM. OE (Output Enable) OE is the input of data output control signal for verify. A 0 ~A 15 (Address Bus) A 0 ~A 15 are address input pins for internal EPROM. O 0 ~O 7 (EPROM Data Bus) These are data bus for internal EPROM. PROGRAMMING The GMS81516AT has address A 0 ~A 15 pins. Therefore, the programmer just program the data (from 4000 H to 7FFF H ) into the GMS81516AT OTP device, during addresses A 14 ,A 15 must be pulled to a logic high. When the programmer write the data from 4000 H to 7FFF H , consequently, the data actually will be written into addresses C000 H to FFFF H of the OTP device. 1. The data format to be programmed is made up of Motorola S1 format. Ex) "Motorola S1" format; S0080000574154434880 S1244000E1FF3BFF04A13F8F06E101711B821B1BE01D1B3B191BF6181BF01C1BFF081BFF0AE0 S12440211BF5091BFF0B1BFF3F1B003E1B003D1B003C1BFF3B1B003A1BFF391BFF381BFF353D : : S1057FF2983FB2 S1057FFEFF3F3F S9030000FC 2. Down load above data into programmer from PC. 3. Programming the data from address 4000 H to 7FFF H into the OTP MCU, the data must be turned over respectively, and then record the data. When read the data, it also must be turned over. Ex) 00(00000000) →FF(11111111), 76(01110110) →89(10001001), FF (11111111)→00(00000000) etc. 4. Of course, the check sum is result of the sum of whole data from address 4000 H to 7FFF H in the file (not reverse data of OTP MCU). * When GMS81516AT shipped, the blank data of GMS81516AT is initially 00 H (not FF H ). 7 HYUNDAI MicroElectronics GMS81516AT EPROM PROGRAMMING Programming Flow GMS81516AT xxxxxxxx.OTP Address Address C000 H 4000 H Program Verify Reading Program area Down Loading File Type: Universal Programmer 16 K BYTES Motorola S-format 7FFF H FFFF H Programming Example Data 1E 00 C4 00 FC 5E C0 70 : : : : 67 C0 : 00 C0 Data Address C000 H C001 H C002 H C003 H C004 H C005 H C006 H C007 H : : : : FFF2 H FFF3 H : FFFE H FFFF H File xxxxxxxx.OTP Programmer Buffer GMS81516AT device Program Reading Verify Address E1 FF 3B FF 04 A1 3F 8F : : : : 98 3F : FF 3F 4000 H 4001 H 4002 H 4003 H 4004 H 4005 H 4006 H 4007 H : : : : 7FF2 H 7FF3 H : 7FFE H 7FFF H Data Down Loading Up Loading E1 FF 3B FF 04 A1 3F 8F : : : : 98 3F : FF 3F Address 4000 H 4001 H 4002 H 4003 H 4004 H 4005 H 4006 H 4007 H : : : : 7FF2 H 7FF3 H : 7FFE H 7FFF H Checksum = E1+FF+3B+FF+04+A1+3F+8F+ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ + 98+3F+ ⋅ ⋅ ⋅ ⋅ +FF+3F 8 GMS81516AT EPROM PROGRAMMING HYUNDAI MicroElectronics DEVICE OPERATION MODE (T A = 25 °C ± 5 °C) Mode Read CE OE A0~A15 VPP VDD O 0~ O 7 X VDD 5.0V DOUT X Output Disable V IH V IH X VDD 5.0V Hi-Z Programming V IL V IH X V PP VDD D IN X V PP VDD DOUT Program Verify X NOTES: 1. X = Either V IL or V IH 2. See DC Characteristics Table for V D D and V P P voltages during programming. DC CHARACTERISTICS (V S S =0 V, T A = 25 °C ± 5 °C) Symbol Item Min Typ Max Unit V VPP Intelligent Programming 12.0 - 13.0 V D D (1) Intelligent Programming 5.75 - 6.25 V I P P (2) V P P supply current 50 mA I D D (2) V D D supply current 30 mA V IH Input high voltage V IL Input low voltage VOH Output high voltage VOL Output low voltage I IL 0.8 V D D 0.2 V D D V V I O H = -2.5 mA 0.4 V I O L = 2.1 mA 5 uA NOTES: 1. V D D must be applied simultaneously or before V PP and removed simultaneously or after V P P . 2. The maximum current value is with outputs O 0 to O 7 unloaded. 9 CE=V IL V V D D -1.0 Input leakage current Test condition HYUNDAI MicroElectronics GMS81516AT EPROM PROGRAMMING SWITCHING WAVEFORMS WAVEFORM INPUTS OUTPUTS Must be steady W ill be steady May change from H to L W ill be changing from H to L May change from L to H W ill be changing from L to H Do not care any change permitted Changing state unknown Does not apply Center line is high impedance "Off" state READING WAVEFORMS V IH Addresses Address Valid V IL V IH (2) OE V IL t AS tO E tD H V IH High-Z Output Valid Output V IL NOTES: 1. The input timing reference level is 1.0 V for a V IL and 4.0V for a V IH at V D D =5.0V 2. To read the output data, transition requires on the O E from the high to the low after address setup time t A S . 10 GMS81516AT EPROM PROGRAMMING HYUNDAI MicroElectronics PROGRAMMING ALGORITHM WAVEFORMS Program Verify Program V IH Addresses Address Stable V IL tA S tA H V IH Data High-Z Data In Stable V IL Data out Valid tD H tD S 12.5V VPP V DD tV P S 6.0V VDD 5.0V tV D S V IH CE V IL tO E S tP W tO E V IH OE V IL tO P W NOTES: 1. The input timing reference level is 1.0 V for a V IL and 4.0V for a V IH at V D D =5.0V 11 tD F P HYUNDAI MicroElectronics GMS81516AT EPROM PROGRAMMING AC READING CHARACTERISTICS (V S S =0 V, T A = 25 °C ± 5 °C) Symbol Item t AS Address setup time tO E Data output delay time tD H Data hold time Min Typ Max Unit 2 Test condition us 200 ns 0 ns NOTES: 1. V D D must be applied simultaneously or before V PP and removed simultaneously or after V P P . AC PROGRAMMING CHARACTERISTICS (V S S =0 V, T A = 25 °C ± 5 °C; See DC Characteristics Table for V D D and V P P voltages.) Symbol t AS Item Min Typ Max Unit Address set-up time 2 us tO E S O E set-up time 2 us tD S Data setup time 2 us tA H Address hold time 0 us tD H Data hold time 1 us tD F P Output disable delay time 0 us tV P S V PP setup time 2 us tV D S V D D setup time 2 us tP W Program pulse width 0.95 CE pulse width when over programming 2.85 tO P W tO E 1.0 Data output delay time Condition* (Note 1) 1.05 ms Intelligent 78.75 ms (Note 2) 200 ns *AC CONDITIONS OF TEST Input Rise and Fall Times (10% to 90%) . . . . 20 ns Input Pulse Levels . . . . . . . . . . . . . . . 0.45V to 4.55V Input Timing Reference Level . . . . . . . . . 1.0V to 4.0V Output Timing Reference Level . . . . . . . . 1.0V to 4.0V NOTES: 1. V D D must be applied simultaneously or before V PP and removed simultaneously or after V P P . 2. The length of the overprogram pulse may vary from 2.85 msec to 78.75 msec as a function of the iteration counter value X Refer to page 13. 12 GMS81516AT EPROM PROGRAMMING HYUNDAI MicroElectronics Intelligent Programming Algorithm START ADDRESS= FIRST LOCATION V D D = 6.0V V PP = 12.5V X=0 PROGRAM ONE 1 ms PULSE INCREMENT X YES X = 25 ? NO FAIL VERIFY BYTE VERIFY ONE BYTE FAIL PASS PASS PROGRAM ONE PULSE OF 3X msec DURATION INCREMENT ADDRESS NO LAST ADDRESS ? YES V D D = V PP = 5.0V COMPARE ALL BYTES TO ORIGINAL DATA FAIL PASS DEVICE PASSED 13 DEVICE FAILED