SN74ALS236 64 × 4 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY SDAS107C – OCTOBER 1986 – REVISED APRIL 1998 D D D D D DW OR N PACKAGE (TOP VIEW) Asynchronous Operation Organized as 64 Words by 4 Bits Data Rates up to 30 MHz 3-State Outputs Package Options Include Plastic Small-Outline Package (DW), Plastic J-Leaded Chip Carriers (FN), and Standard Plastic 300-mil DIPs (N) NC IR SI D0 D1 D2 D3 GND description The SN74ALS236 is a 256-bit memory utilizing advanced low-power Schottky IMPACT technology. It features high speed with fast fall-through times and is organized as 64 words by 4 bits. A first-in, first-out (FIFO) memory is a storage device that allows data to be written into and read from its array at independent data rates. The SN74ALS236 is designed to process data at rates up to 30 MHz in a bit-parallel format, word by word. 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC SO OR Q0 Q1 Q2 Q3 RST IR NC NC VCC SO FN PACKAGE (TOP VIEW) SI D0 NC D1 D2 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 OR Q0 NC Q1 Q2 D3 GND NC RST Q3 Data is written into memory on the rising edge of the shift-in (SI) input. When SI goes low, the first data word ripples through to the output (see Figure 1). As the FIFO fills up, the data words NC – No internal connection stack up in the order they were written. When the FIFO is full, additional shift-in pulses have no effect. Data is shifted out of memory on the falling edge of the shift-out (SO) input (see Figure 2). When the FIFO is empty, additional SO pulses have no effect. The last data word remains at the outputs until a new word falls through or reset (RST) goes low. Status of the SN74ALS236 FIFO memory is monitored by the output-ready (OR) and input-ready (IR) flags. When OR is high, valid data is available at the outputs. OR is low when SO is high and stays low when the FIFO is empty. IR is high when the inputs are ready to receive more data. IR is low when SI is high and stays low when the FIFO is full. When the FIFO is empty, input data is shifted to the output automatically when SI goes low. If SO is held high during this time, the OR flag pulses high, indicating valid data at the outputs (see Figure 3). When the FIFO is full, data is shifted in automatically by holding SI high and taking SO low. One propagation delay after SO goes low, IR goes high. If SI is still high when IR goes high, data at the inputs is automatically shifted in. Since IR is normally low when the FIFO is full and SI is high, only a high-level pulse is seen on the IR output (see Figure 4). Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. IMPACT is a trademark of Texas Instruments Incorporated. Copyright 1998, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN74ALS236 64 × 4 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY SDAS107C – OCTOBER 1986 – REVISED APRIL 1998 description (continued) The FIFO must be reset after power up with a low-level pulse on the master reset (RST) input. This sets IR high and OR low, signifying that the FIFO is empty. Resetting the FIFO sets the outputs to a low logic level (see Figure 1). If SI is high when RST goes high, the input data is shifted in and IR goes low and remains low until SI goes low. If SI goes low before RST goes high, the input data is not shifted in and IR goes high. Data outputs are noninverting with respect to the data inputs. The SN74ALS236 is characterized for operation from 0°C to 70°C. logic symbol† FIFO 64 × 4 SI CTR 3 5 + /C1 G2 SO 15 14 3CT > 0 OR (CT > 0) G4 4– 2 2CT < 64 G3 IR (CT < 64) G5 CT = 0 9 R RST D0 D1 D2 D3 4 13 1D 5 12 6 11 7 10 Q0 Q1 Q2 Q3 † This symbol is in accordance with ANSI/IEEE Standard 91-1984 and IEC Publication 617-12. Pin numbers shown are for the DW and N packages. functional block diagram D0 D1 D2 D3 IR SI RST 4 5 6 7 2 3 FIFO Input Stage 62 × 4 Bit Register FIFO Output Stage InputControl Logic RegisterControl Logic OutputControl Logic 9 Pin numbers shown are for the DW and N packages. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 12 11 10 15 14 Q0 Q1 Q2 Q3 SO OR Word 63 Word 64 Q1 Q2 Q3 D1 D2 D3 RST • DALLAS, TEXAS 75265 3 SDAS107C – OCTOBER 1986 – REVISED APRIL 1998 SN74ALS236 64 × 4 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY POST OFFICE BOX 655303 SO OR IR SI Word 3 Word 2 Word 1 D0 Data Outputs Q0 Data Inputs logic diagram (positive logic) Words 4 – 62 Same as 3 or 63 SN74ALS236 64 × 4 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY SDAS107C – OCTOBER 1986 – REVISED APRIL 1998 timing diagram RST SI D3 – D0 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ W1 Don’t Care W2 W1 W2 W63 W64 W1 SO Word 1 Q3 – Q0 Word 2 Invalid† Word 1‡ Word 2 Word 3 IR OR Clear Shift In W1 Shift Out W2 Full Empty † The last data word shifted out of the FIFO remains at the output until a new word falls through or an RST pulse clears the FIFO. ‡ While the output data is considered valid only when the OR flag is high, the stored data remains at the outputs. Any additional words written into the FIFO stack up behind the first word and do not appear at the output until SO is taken low. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74ALS236 64 × 4 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY SDAS107C – OCTOBER 1986 – REVISED APRIL 1998 RST tsu SI D3 – D0 ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ th tsu tPLH IR tPHL tPLH Full tPHL tPLH Empty OR tpd tpd Q3 – Q0 NOTE A: SO is low. Figure 1. Master Reset and Data-In Waveforms SO tPLH OR tPHL tPLH IR Full td(SOL-QX) Q3 – Q0 tpd NOTE A: SI is low. Figure 2. Data-Out Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN74ALS236 64 × 4 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY SDAS107C – OCTOBER 1986 – REVISED APRIL 1998 ÎÎÎ ÎÎÎ D3 – D0 tsu th ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ SI SO tPLH OR tw Empty td(QV-ORH) Q3 – Q0 Invalid Figure 3. Data Fall-Through Waveforms SO SI IR tPLH tw Full Full ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ D3 – D0 Figure 4. Automatic Data-In Waveforms absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Package thermal impedance, θJA (see Note 2): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105°C/W FN package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values are with respect to GND. 2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace length of zero. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74ALS236 64 × 4 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY SDAS107C – OCTOBER 1986 – REVISED APRIL 1998 recommended operating conditions VCC VIH Supply voltage VIL Low-level input voltage IOH High level output current High-level IOL Low level output current Low-level TA MIN NOM MAX 4.5 5 5.5 High-level input voltage 2 V V 0.8 Q outputs – 2.6 IR and OR – 0.4 Q outputs 24 IR and OR 8 Operating free-air temperature UNIT 0 70 V mA mA °C electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK TEST CONDITIONS VCC = 4.5 V, MIN TYP† II = – 18 mA IOH = – 1 mA MAX UNIT – 1.2 V Any Q 5V VCC = 4 4.5 IR, OR VCC = 4.5 V, Any Q VCC = 4 4.5 5V IOL = 12 mA IOL = 24 mA 0.25 0.4 0.35 0.5 IR OR IR, 5V VCC = 4 4.5 IOL = 4 mA IOL = 8 mA 0.25 0.4 0.35 0.5 II IIH VCC = 5.5 V, VCC = 5.5 V, VI = 7 V VI = 2.7 V IIL IO‡ VCC = 5.5 V, VCC = 5.5 V, VI = 0.4 V VO = 2.25 V ICC VCC = 5 5.5 5V VOH VOL IOH = – 2.6 mA IOH = – 0.4 mA 2.4 3.2 2.7 3.4 V 0.1 – 30 V mA 20 µA – 0.1 mA –112 mA Low 100 145 High 97 142 mA † All typical values are at VCC = 5 V, TA = 25°C. ‡ The output conditions have been chosen to produce a current that closely approximates one-half of the true short-circuit output current, IOS. timing requirements over recommended operating conditions (unless otherwise noted) (see Figure 5) MIN fclock Clock frequency tw Pulse duration tsu Setup time before SI↑ ↑ th Hold time, data after SI↑ SI or SO SI or SO High or low 15 RST Low 15 Data RST • DALLAS, TEXAS 75265 UNIT 30 MHz ns 0 High (inactive) 15 17 POST OFFICE BOX 655303 MAX ns ns 7 SN74ALS236 64 × 4 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY SDAS107C – OCTOBER 1986 – REVISED APRIL 1998 switching characteristics (see Figure 5) PARAMETER FROM (INPUT) fmax tw‡ tw§ TO (OUTPUT) MIN 35 30 IR high 15 8 ns OR high 19 8 ns 6 13 SI↓ SI↓ tpd tPHL SO↓ tPLH tPLH¶ SO↓ UNIT SO Q valid after SO↓ tPLH tPLH¶ MAX 30 Q valid before OR↑ SI↓ MIN 35 td(SOL-QX) tpd tPHL MAX SI td(QV-ORH) tPHL tPLH Q SI↑ RST↓ POST OFFICE BOX 655303 12 4 ns ns 350 1000 20 26 8 30 16 21 6 25 OR 600 800 350 1000 ns Q 13 17 4 22 ns 23 27 7 33 20 24 6 30 OR SO↓ –5 800 IR SO↑ 9 MHz 600 IR 600 800 350 1000 OR 22 26 10 34 IR 17 21 6 27 14 17 5 19 tPHL Q 14 RST↓ † All typical values are at VCC = 5 V, TA = 25°C. ‡ The IR output pulse occurs when the FIFO is full, SI is high, and SO is pulsed (see Figure 4). § The OR output pulse occurs when the FIFO is empty, SO is high, and SI is pulsed (see Figure 3). ¶ Data throughput or fall-through times 8 TYP† • DALLAS, TEXAS 75265 ns ns ns ns ns ns SN74ALS236 64 × 4 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY SDAS107C – OCTOBER 1986 – REVISED APRIL 1998 PARAMETER MEASUREMENT INFORMATION 7V PARAMETER Open S1 ten R1 = 500 Ω From Output Under Test CL = 50 pF (see Note A) tdis Test Point tpd R2 = 500 Ω S1 tPZH tPZL tPHZ tPLZ Open Closed Open Closed tPLH Open Open tPHL LOAD CIRCUIT FOR 3-STATE OUTPUTS 3.5 V High-Level Pulse 1.3 V 0.3 V tw 3.5 V Timing Input 1.3 V 0.3 V th tsu 1.3 V 1.3 V 0.3 V VOLTAGE WAVEFORMS PULSE DURATION 1.3 V 1.3 V 3.5 V Low-Level Pulse 3.5 V Data Input 1.3 V 0.3 V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 3.5 V Output Control 3.5 V Input (see Note C) 1.3 V 1.3 V 0.3 V tPZL 1.3 V tPLZ 0.3 V tPLH In-Phase Output tPHL VOH 1.3 V VOL 1.3 V Out-of-Phase Output 3.5 V Waveform 1 S1 Closed (see Note B) tPLH tPHL VOH 1.3 V 1.3 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES 1.3 V 1.3 V tPZH Waveform 2 S1 Open (see Note B) tPHZ VOL 0.3 V VOH 1.3 V 0.3 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Zo = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time with one transition per measurement. Figure 5. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 SN74ALS236 64 × 4 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY SDAS107C – OCTOBER 1986 – REVISED APRIL 1998 APPLICATION INFORMATION IR SO IR SO IR SO SI D0 D1 OR Q0 Q1 SI D0 D1 OR Q0 Q1 SI D0 D1 OR Q0 Q1 D2 Q2 D2 Q2 D2 Q2 D3 Q3 D3 Q3 D3 Q3 RST IR RST SI RST IR SO IR SO IR SO SI D0 D1 OR Q0 Q1 SI D0 D1 OR Q0 Q1 SI D0 D1 OR Q0 Q1 D2 Q2 D2 Q2 D2 Q2 D3 Q3 D3 Q3 D3 Q3 RST RST OR RST IR SO IR SO IR SO SI D0 D1 OR Q0 Q1 SI D0 D1 OR Q0 Q1 SI D0 D1 OR Q0 Q1 D2 Q2 D2 Q2 D2 Q2 D3 Q3 D3 Q3 D3 Q3 RST SO RST RST RST Figure 6. Word-Width Expansion: 192 × 12 Bits 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. 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