PHILIPS PHN1011

Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
FEATURES
PHN1011
SYMBOL
• ’Trench’ technology
• Low on-state resistance
• Fast switching
• High thermal cycling performance
• Low-profile surface mount
package
• Logic level compatible
QUICK REFERENCE DATA
VDSS = 25 V
d
ID = 11 A
RDS(ON) ≤ 11 mΩ (VGS = 10 V)
g
RDS(ON) ≤ 13.5 mΩ (VGS = 5 V)
s
GENERAL DESCRIPTION
PINNING
N-channel enhancement mode
logic level field-effect power
transistor in a surface mounting
plastic package using ’trench’
technology. The combination of
very low on-state resistance and
low switching losses make this
device the optimum choice in high
speed computer motherboard d.c.
to d.c. converters.
SOT96-1 (SO8)
PIN
1-3
DESCRIPTION
8
7
6
5
1
2
3
4
source
4
gate
5-8
drain
pin 1 index
The PHN1011 is supplied in the
SOT96-1 (SO8) surface mounting
package
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL
PARAMETER
CONDITIONS
VDSS
VDGR
Drain-source voltage
Drain-gate voltage
VGS
VGSM
ID
Gate-source voltage (DC)
Gate-source voltage (pulse peak
value)
Drain current (tp ≤ 10 s)
Tj = 25 ˚C to 150˚C
Tj = 25 ˚C to 150˚C;
RGS = 20 kΩ
-
IDM
Ptot
Drain current (pulse peak value)
Total power dissipation
Tj, Tstg
Operating junction and storage
temperature
Ta = 25 ˚C
Ta = 70 ˚C
Ta = 25 ˚C
Ta = 25 ˚C
Ta = 70 ˚C
-
MIN.
MAX.
UNIT
-
25
25
V
V
-
± 15
± 20
V
V
- 55
11
9
44
2.5
1.6
150
A
A
A
W
W
˚C
THERMAL RESISTANCES
SYMBOL PARAMETER
CONDITIONS
Rth j-a
Surface mounted, FR4 board, t ≤ 10 sec
Rth j-a
June 1999
Thermal resistance junction
to ambient
Thermal resistance junction
to ambient
Surface mounted, FR4 board
1
TYP.
MAX.
UNIT
-
50
K/W
150
-
K/W
Rev 1.100
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
PHN1011
ELECTRICAL CHARACTERISTICS
Tj= 25˚C unless otherwise specified
SYMBOL PARAMETER
V(BR)DSS
VGS(TO)
Drain-source breakdown
voltage
Gate threshold voltage
CONDITIONS
MIN.
VGS = 0 V; ID = 0.25 mA;
Tj = -55˚C
VDS = VGS; ID = 1 mA
Tj = 150˚C
Tj = -55˚C
RDS(ON)
gfs
IGSS
IDSS
Drain-source on-state
resistance
VGS = 10 V; ID = 10 A
VGS = 5 V; ID = 5 A
VGS = 5 V; ID = 5 A; Tj = 150˚C
Forward transconductance
VDS = 25 V; ID = 10 A
Gate source leakage current VGS = ±5 V; VDS = 0 V
Zero gate voltage drain
VDS = 25 V; VGS = 0 V;
current
Tj = 150˚C
TYP. MAX. UNIT
25
22
1
0.6
12
-
1.5
9
11
36
10
0.05
-
2
2.3
11
13.5
23
100
10
500
V
V
V
V
V
mΩ
mΩ
mΩ
S
nA
µA
µA
Qg(tot)
Qgs
Qgd
Total gate charge
Gate-source charge
Gate-drain (Miller) charge
ID = 25 A; VDD = 15 V; VGS = 5 V
-
26
6
9.4
-
nC
nC
nC
td on
tr
td off
tf
Turn-on delay time
Turn-on rise time
Turn-off delay time
Turn-off fall time
VDD = 15 V; ID = 25 A;
VGS = 10 V; RG = 5 Ω
Resistive load
-
7
50
82
59
15
75
120
75
ns
ns
ns
ns
Ld
Ls
Internal drain inductance
Internal source inductance
Drain leads to centre of die
Source leads to source bond pad
-
1
3
-
nH
nH
Ciss
Coss
Crss
Input capacitance
Output capacitance
Feedback capacitance
VGS = 0 V; VDS = 20 V; f = 1 MHz
-
1700
475
300
-
pF
pF
pF
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
Tj = 25˚C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
IS
Ta = 25 ˚C, tp ≤ 10 s
VSD
Continuous source current
(body diode)
Pulsed source current (body
diode)
Diode forward voltage
trr
Qrr
Reverse recovery time
Reverse recovery charge
ISM
June 1999
MIN.
TYP. MAX. UNIT
-
-
11
A
-
-
44
A
IF = 10 A; VGS = 0 V
-
0.95
1.2
V
IF = 10 A; -dIF/dt = 100 A/µs;
VGS = 0 V; VR = 25 V
-
83
0.1
-
ns
µC
2
Rev 1.100
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
PHN1011
Normalised Power Derating, Ptot (%)
Transient thermal impedance, Zth j-mb (K/W)
100
100
D = 0.5
90
0.2
80
10
0.1
70
0.05
0.02
60
1
50
P
D
40
30
D = tp/T
tp
single pulse
0.1
20
T
10
0.01
1E-06
0
0
20
40
60
80
100
120
140
1E-05
1E-04
1E-03
160
1E-02
1E-01
1E+00
1E+01
Pulse width, tp (s)
Ambient temperature, Ta (C)
Fig.1. Normalised power dissipation.
PD% = 100⋅PD/PD 25 ˚C = f(Ta)
Fig.4. Transient thermal impedance.
Zth j-a = f(t); parameter D = tp/T
Drain Current, ID (A)
50
Normalised Current Derating, ID (%)
120
5V
VGS = 10 V
Tj = 25 C
45
4.5 V
3V
40
100
35
80
2.8 V
30
25
60
2.6 V
20
40
15
20
2.4 V
10
2.2 V
5
2V
0
0
20
40
60
80
100
120
140
0
160
0
Ambient temperature, Ta (C)
Fig.2. Normalised continuous drain current.
ID% = 100⋅ID/ID 25 ˚C = f(Ta); conditions: VGS ≥ 5 V
100
0.6
0.8
1
1.2
1.4
Drain-Source Voltage, VDS (V)
1.6
1.8
2
Drain-Source On Resistance, RDS(on) (Ohms)
tp = 10 us
10
0.4
Fig.5. Typical output characteristics, Tj = 25 ˚C.
ID = f(VDS); parameter VGS
Peak Pulsed Drain Current, IDM (A)
RDS(on) = VDS/ ID
0.2
0.1
2.2 V
100 us
0.09
1 ms
0.08
10 ms
0.07
2.6 V
2.4 V
Tj = 25 C
2.8V
0.06
100 ms
1
3V
0.05
D.C.
0.04
0.03
0.1
0.02
VGS =4.5 V
5V
0.01
10V
0.01
0
0.1
1
10
Drain-Source Voltage, VDS (V)
100
0
Fig.3. Safe operating area. Ta = 25 ˚C
ID & IDM = f(VDS); IDM single pulse; parameter tp
June 1999
5
10
15
20
25
30
Drain Current, ID (A)
35
40
45
50
Fig.6. Typical on-state resistance, Tj = 25 ˚C.
RDS(ON) = f(ID); parameter VGS
3
Rev 1.100
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
PHN1011
Threshold Voltage, VGS(TO) (V)
Drain current, ID (A)
2.25
50
VDS > ID X RDS(ON)
45
2
40
1.75
35
1.5
maximum
typical
30
1.25
25
1
minimum
20
0.75
15
10
0.5
150 C
Tj = 25 C
5
0.25
0
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
0
5
-60
-40
-20
0
Gate-source voltage, VGS (V)
60
80
100
120
140
160
180
Fig.10. Gate threshold voltage.
VGS(TO) = f(Tj); conditions: ID = 0.25 mA; VDS = VGS
Transconductance, gfs (S)
Drain current, ID (A)
1.0E-01
VDS > ID X RDS(ON)
45
40
Junction Temperature, Tj (C)
Fig.7. Typical transfer characteristics.
ID = f(VGS) ; conditions: VDS = 25 V; parameter Tj
50
20
VDS = 5 V
Tj = 25 C
40
1.0E-02
35
150 C
30
1.0E-03
25
minimum
20
typical
maximum
1.0E-04
15
10
1.0E-05
5
0
1.0E-06
0
5
10
15
20
25
Drain current, ID (A)
30
35
40
0
Fig.8. Typical transconductance, Tj = 25 ˚C.
gfs = f(ID); conditions: VDS = 25 V
2
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0.5
1
1.5
2
Gate-source voltage, VGS (V)
2.5
3
Fig.11. Sub-threshold drain current.
ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS
Normalised On-state Resistance
Capacitances, Ciss, Coss, Crss (pF)
10000
Ciss
1000
Coss
Crss
100
-60
-40
-20
0
20
40
60
80
100
Junction temperature, Tj (C)
120
140
160
180
0.1
Fig.9. Normalised drain-source on-state resistance.
a = RDS(ON)/RDS(ON)25 ˚C = f(Tj)
June 1999
1
10
Drain-Source Voltage, VDS (V)
100
Fig.12. Typical capacitances, Ciss, Coss, Crss.
C = f(VDS); conditions: VGS = 0 V; f = 1 MHz
4
Rev 1.100
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
PHN1011
Source-Drain Diode Current, IF (A)
50
Gate-source voltage, VGS (V)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
VGS = 0 V
ID = 25A
45
Tj = 25 C
40
VDD = 15 V
35
30
150 C
25
Tj = 25 C
20
15
10
5
0
0
5
10
15
20
25
30
Gate charge, QG (nC)
35
40
45
50
0
0.2
0.3 0.4
0.5
0.6
0.7
0.8
0.9
1
1.1 1.2
1.3
1.4
1.5
Source-Drain Voltage, VSDS (V)
Fig.13. Typical turn-on gate-charge characteristics.
VGS = f(QG); parameter VDS
June 1999
0.1
Fig.14. Typical reverse diode current.
IF = f(VSDS); conditions: VGS = 0 V; parameter Tj
5
Rev 1.100
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
PHN1011
MECHANICAL DATA
SO8: plastic small outline package; 8 leads; body width 3.9 mm
SOT96-1
D
E
A
X
c
y
HE
v M A
Z
5
8
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
1
L
4
e
detail X
w M
bp
0
2.5
5 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
max.
A1
A2
mm
inches
UNIT
A3
bp
c
D (1)
E (2)
1.75
0.25
0.10
1.45
1.25
0.25
0.49
0.36
0.25
0.19
5.0
4.8
0.069
0.010 0.057
0.004 0.049
0.01
0.019 0.0100
0.014 0.0075
0.20
0.19
e
HE
4.0
3.8
1.27
6.2
5.8
0.16
0.15
0.050
L
Lp
Q
1.05
1.0
0.4
0.7
0.6
0.244
0.039 0.028
0.041
0.228
0.016 0.024
v
w
y
Z (1)
0.25
0.25
0.1
0.7
0.3
0.01
0.01
0.004
0.028
0.012
θ
o
8
0o
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT96-1
076E03S
MS-012AA
EIAJ
EUROPEAN
PROJECTION
ISSUE DATE
95-02-04
97-05-22
Fig.15. SOT96 surface mounting package.
Notes
1. This product is supplied in anti-static packaging. The gate-source input must be protected against static
discharge during transport or handling.
2. Refer to Integrated Circuit Packages, Data Handbook IC26.
3. Epoxy meets UL94 V0 at 1/8".
June 1999
6
Rev 1.100
Philips Semiconductors
Product specification
TrenchMOS transistor
Logic level FET
PHN1011
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and
operation of the device at these or at any other conditions above those given in the Characteristics sections of
this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
 Philips Electronics N.V. 1999
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the
copyright owner.
The information presented in this document does not form part of any quotation or contract, it is believed to be
accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under patent or other
industrial or intellectual property rights.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices or systems where malfunction of these
products can be reasonably expected to result in personal injury. Philips customers using or selling these products
for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting
from such improper use or sale.
June 1999
7
Rev 1.100