TLC7524C, TLC7524E, TLC7524I 8-BIT MULTIPLYING DIGITAL-TO-ANALOG CONVERTERS SLAS061C – SEPTEMBER 1986 – REVISED NOVEMBER 1998 D D D D D, N, OR PW PACKAGE (TOP VIEW) Easily Interfaced to Microprocessors On-Chip Data Latches Monotonic Over the Entire A/D Conversion Range Segmented High-Order Bits Ensure Low-Glitch Output Interchangeable With Analog Devices AD7524, PMI PM-7524, and Micro Power Systems MP7524 Fast Control Signaling for Digital Signal-Processor Applications Including Interface With TMS320 CMOS Technology OUT1 OUT2 GND DB7 DB6 DB5 DB4 DB3 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 RFB REF VDD WR CS DB0 DB1 DB2 FN PACKAGE (TOP VIEW) KEY PERFORMANCE SPECIFICATIONS Resolution Linearity error Power dissipation at VDD = 5 V Setting time Propagation delay time 1 OUT2 OUT1 NC RFB REF D D D 8 Bits 1/2 LSB Max 5 mW Max 100 ns Max 80 ns Max GND DB7 NC DB6 DB5 description 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 VDD WR NC CS DB0 DB4 DB3 NC DB2 DB1 The TLC7524C, TLC7524E, and TLC7524I are CMOS, 8-bit, digital-to-analog converters (DACs) designed for easy interface to most popular microprocessors. 4 NC–No internal connection The devices are 8-bit, multiplying DACs with input latches and load cycles similar to the write cycles of a random access memory. Segmenting the high-order bits minimizes glitches during changes in the most significant bits, which produce the highest glitch impulse. The devices provide accuracy to 1/2 LSB without the need for thin-film resistors or laser trimming, while dissipating less than 5 mW typically. Featuring operation from a 5-V to 15-V single supply, these devices interface easily to most microprocessor buses or output ports. The 2- or 4-quadrant multiplying makes these devices an ideal choice for many microprocessor-controlled gain-setting and signal-control applications. The TLC7524C is characterized for operation from 0°C to 70°C. The TLC7524I is characterized for operation from – 25°C to 85°C. The TLC7524E is characterized for operation from – 40°C to 85°C. AVAILABLE OPTIONS PACKAGE TA SMALL OUTLINE PLASTIC DIP (D) PLASTIC CHIP CARRIER (FN) PLASTIC DIP (N) SMALL OUTLINE (PW) 0°C to 70°C TLC7524CD TLC7524CFN TLC7524CN TLC7524CPW – 25°C to 85°C TLC7524ID TLC7524IFN TLC7524IN TLC7524IPW – 40°C to 85°C TLC7524ED TLC7524EFN TLC7524EN – Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 1998, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 TLC7524C, TLC7524E, TLC7524I 8-BIT MULTIPLYING DIGITAL-TO-ANALOG CONVERTERS SLAS061C – SEPTEMBER 1986 – REVISED NOVEMBER 1998 functional block diagram REF R 15 2R R 2R R 2R 2R 2R 16 S-1 S-2 S-3 S-8 R 1 2 CS WR 12 3 Data Latches 13 4 DB7 (MSB) 5 DB6 6 DB5 RFB OUT1 OUT2 GND 11 DB0 (LSB) Data Inputs Terminal numbers shown are for the D or N package. absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 16.5 V Digital input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to VDD + 0.3 V Reference voltage, Vref . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 25 V Peak digital input current, II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 µA Operating free-air temperature range, TA: TLC7524C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C TLC7524I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 25°C to 85°C TLC7524E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 85°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C Case temperature for 10 seconds, TC: FN package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D, N, or PW package . . . . . . . . . . . 260°C 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLC7524C, TLC7524E, TLC7524I 8-BIT MULTIPLYING DIGITAL-TO-ANALOG CONVERTERS SLAS061C – SEPTEMBER 1986 – REVISED NOVEMBER 1998 recommended operating conditions VDD = 5 V NOM MAX MIN Supply voltage, VDD 4.75 5 5.25 VDD = 15 V NOM MAX MIN 14.5 ± 10 Reference voltage, Vref High-level input voltage, VIH 15 2.4 V 0.8 40 CS hold time, th(CS) V V 13.5 Low-level input voltage, VIL CS setup time, tsu(CS) 15.5 ± 10 UNIT 1.5 V 40 ns 0 0 ns Data bus input setup time, tsu(D) 25 25 ns Data bus input hold time, th(D) 10 10 ns Pulse duration, WR low, tw(WR) 40 TLC7524C Operating free-air temperature, TA 40 ns 0 70 0 70 TLC7524I – 25 85 – 25 85 TLC7524E – 40 85 – 40 85 °C electrical characteristics over recommended operating free-air temperature range, Vref = ±10 V, OUT1 and OUT2 at GND (unless otherwise noted) PARAMETER IIH IIL IIk Ikg TEST CONDITIONS High-level input current Low-level input current g Output leakage current VDD = 5 V TYP MAX MIN VI = VDD VI = 0 µA µA – 10 – 10 OUT1 ± 400 ± 200 OUT2 DB0–DB7 at VDD, Vref = ± 10 V WR, CS at 0 V, ± 400 ± 200 Quiescent DB0–DB7 at VIHmin or VILmax Standby DB0–DB7 at 0 V or VDD kSVS Supply voltage sensitivity, ∆gain/∆VDD ∆VDD = ± 10% Ci Input capacitance, DB0–DB7, WR, CS VI = 0 nA 0.01 OUT2 DB0 DB7 at 0 V DB0–DB7 V, WR CS at 0 V WR, DB0 DB7 at VDD, DB0–DB7 WR CS at 0 V WR, OUT1 OUT2 1 2 mA 500 500 µA 0.04 %FSR/% 0.16 0.005 5 OUT1 Output capacitance 10 WR, CS at 0 V, Supply current Reference input impedance (REF to GND) 5 POST OFFICE BOX 655303 UNIT 10 DB0–DB7 at 0 V, Vref = ± 10 V IDD Co VDD = 15 V TYP MAX MIN • DALLAS, TEXAS 75265 5 30 30 120 120 120 120 30 30 20 5 20 pF pF kΩ 3 TLC7524C, TLC7524E, TLC7524I 8-BIT MULTIPLYING DIGITAL-TO-ANALOG CONVERTERS SLAS061C – SEPTEMBER 1986 – REVISED NOVEMBER 1998 operating characteristics over recommended operating free-air temperature range, Vref = ±10 V, OUT1 and OUT2 at GND (unless otherwise noted) PARAMETER TEST CONDITIONS VDD = 5 V MIN TYP MAX VDD = 15 V TYP MIN MAX UNIT ± 0.5 ± 0.5 LSB Linearity error Gain error See Note 1 ± 2.5 ± 2.5 LSB Settling time (to 1/2 LSB) See Note 2 100 100 ns Propagation delay from digital input to 90% of final analog output current See Note 2 80 80 ns Feedthrough at OUT1 or OUT2 Vref = ±10 V (100-kHz sinewave) WR and CS at 0 V, DB0–DB7 at 0 V 0.5 0.5 %FSR TA = 25°C to MAX ± 0.004 ± 0.001 NOTES: 1. Gain error is measured using the internal feedback resistor. Nominal full-scale range (FSR) = Vref – 1 LSB. 2. OUT1 load = 100 Ω, Cext = 13 pF, WR at 0 V, CS at 0 V, DB0 – DB7 at 0 V to VDD or VDD to 0 V. Temperature coefficient of gain operating sequence tsu(CS) th(CS) CS tw(WR) WR ÎÎÎ ÎÎÎ tsu(D) DB0–DB7 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 th(D) %FSR/°C TLC7524C, TLC7524E, TLC7524I 8-BIT MULTIPLYING DIGITAL-TO-ANALOG CONVERTERS SLAS061C – SEPTEMBER 1986 – REVISED NOVEMBER 1998 PRINCIPLES OF OPERATION voltage-mode operation It is possible to operate the current-multiplying DAC in these devices in a voltage mode. In the voltage mode, a fixed voltage is placed on the current output terminal. The analog output voltage is then available at the reference voltage terminal. Figure 1 is an example of a current-multiplying DAC, which is operated in voltage mode. R R R REF (Analog Output Voltage) 2R 2R 2R 0 2R 1 R OUT1 (Fixed Input Voltage) OUT2 Figure 1. Voltage Mode Operation The relationship between the fixed-input voltage and the analog-output voltage is given by the following equation: VO = VI (D/256) where VO = analog output voltage VI = fixed input voltage D = digital input code converted to decimal In voltage-mode operation, these devices meet the following specification: PARAMETER Linearity error at REF TEST CONDITIONS VDD = 5 V, OUT1 = 2.5 V, POST OFFICE BOX 655303 OUT2 at GND, • DALLAS, TEXAS 75265 MIN TA = 25°C MAX UNIT 1 LSB 5 TLC7524C, TLC7524E, TLC7524I 8-BIT MULTIPLYING DIGITAL-TO-ANALOG CONVERTERS SLAS061C – SEPTEMBER 1986 – REVISED NOVEMBER 1998 PRINCIPLES OF OPERATION The TLC7524C, TLC7524E, and TLC7524I are 8-bit multiplying DACs consisting of an inverted R-2R ladder, analog switches, and data input latches. Binary-weighted currents are switched between the OUT1 and OUT2 bus lines, thus maintaining a constant current in each ladder leg independent of the switch state. The high-order bits are decoded. These decoded bits, through a modification in the R-2R ladder, control three equally-weighted current sources. Most applications only require the addition of an external operational amplifier and a voltage reference. The equivalent circuit for all digital inputs low is seen in Figure 2. With all digital inputs low, the entire reference current, Iref, is switched to OUT2. The current source I/256 represents the constant current flowing through the termination resistor of the R-2R ladder, while the current source IIkg represents leakage currents to the substrate. The capacitances appearing at OUT1 and OUT2 are dependent upon the digital input code. With all digital inputs high, the off-state switch capacitance (30 pF maximum) appears at OUT2 and the on-state switch capacitance (120 pF maximum) appears at OUT1. With all digital inputs low, the situation is reversed as shown in Figure 2. Analysis of the circuit for all digital inputs high is similar to Figure 2; however, in this case, Iref would be switched to OUT1. The DAC on these devices interfaces to a microprocessor through the data bus and the CS and WR control signals. When CS and WR are both low, analog output on these devices responds to the data activity on the DB0–DB7 data bus inputs. In this mode, the input latches are transparent and input data directly affects the analog output. When either the CS signal or WR signal goes high, the data on the DB0–DB7 inputs are latched until the CS and WR signals go low again. When CS is high, the data inputs are disabled regardless of the state of the WR signal. These devices are capable of performing 2-quadrant or full 4-quadrant multiplication. Circuit configurations for 2-quadrant or 4-quadrant multiplication are shown in Figure 3 and Figure 4. Table 1 and Table 2 summarize input coding for unipolar and bipolar operation respectively. RFB R OUT1 30 pF IIkg Iref REF OUT2 I/256 120 pF IIkg Figure 2. TLC7524 Equivalent Circuit With All Digital Inputs Low 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLC7524C, TLC7524E, TLC7524I 8-BIT MULTIPLYING DIGITAL-TO-ANALOG CONVERTERS SLAS061C – SEPTEMBER 1986 – REVISED NOVEMBER 1998 PRINCIPLES OF OPERATION Vref VDD RA = 2 kΩ (see Note A) RB C (see Note B) RFB DB0–DB7 OUT1 – OUT2 + Output CS WR GND NOTES: A. RA and RB used only if gain adjustment is required. B. C phase compensation (10-15 pF) is required when using high-speed amplifiers to prevent ringing or oscillation. Figure 3. Unipolar Operation (2-Quadrant Multiplication) VDD Vref 20 kΩ RA = 2 kΩ (see Note A) RB CS WR – C (see Note B) RFB DB0–DB7 20 kΩ Output OUT1 – OUT2 + + 10 kΩ 5 kΩ GND NOTES: A. RA and RB used only if gain adjustment is required. B. C phase compensation (10-15 pF) is required when using high-speed amplifiers to prevent ringing or oscillation. Figure 4. Bipolar Operation (4-Quadrant Operation) Table 1. Unipolar Binary Code DIGITAL INPUT (see Note 3) MSB ANALOG OUTPUT LSB Table 2. Bipolar (Offset Binary) Code DIGITAL INPUT (see Note 4) MSB ANALOG OUTPUT LSB 11111111 – Vref (255/256) 11111111 10000001 – Vref (129/256) 10000001 Vref (127/128) Vref (1/128) 10000000 – Vref (128/256) = – Vref/2 10000000 0 01111111 – Vref (127/256) 01111111 – Vref (1/128) 00000001 – Vref (1/256) 00000001 – Vref (127/128) 00000000 0 00000000 – Vref NOTE 3: LSB = 1/256 (Vref) NOTE 4: LSB = 1/128 (Vref) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 TLC7524C, TLC7524E, TLC7524I 8-BIT MULTIPLYING DIGITAL-TO-ANALOG CONVERTERS SLAS061C – SEPTEMBER 1986 – REVISED NOVEMBER 1998 PRINCIPLES OF OPERATION microprocessor interfaces D0–D7 Data Bus Z–80A DB0–DB7 WR TLC7524 WR OUT1 OUT2 CS IORQ Decode Logic Address Bus A0–A15 Figure 5. TLC7524 – Z-80A Interface Data Bus D0–D7 6800 DB0–DB7 φ2 WR TLC7524 OUT1 OUT2 CS VMA A0–A15 Decode Logic Address Bus Figure 6. TLC7524 – 6800 Interface 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLC7524C, TLC7524E, TLC7524I 8-BIT MULTIPLYING DIGITAL-TO-ANALOG CONVERTERS SLAS061C – SEPTEMBER 1986 – REVISED NOVEMBER 1998 PRINCIPLES OF OPERATION microprocessor interfaces (continued) A8–A15 Address Bus 8051 Decode Logic 8-Bit Latch CS WR ALE TLC7524 DB0–DB7 OUT1 OUT2 WR AD0–AD7 Adress/Data Bus Figure 7. TLC7524 – 8051 Interface POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK. 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