TI SN74LVC02A

SN54LVC02A, SN74LVC02A
QUADRUPLE 2-INPUT POSITIVE-NOR GATES
SCAS280I – JANUARY 1993 – REVISED OCTOBER 1998
D
D
D
D
D
SN54LVC02A . . . J OR W PACKAGE
SN74LVC02A . . . D, DB, OR PW PACKAGE
(TOP VIEW)
1Y
1A
1B
2Y
2A
2B
GND
1
14
2
13
3
12
4
11
5
10
6
9
7
8
VCC
4Y
4B
4A
3Y
3B
3A
SN54LVC02A . . . FK PACKAGE
(TOP VIEW)
1B
NC
2Y
NC
2A
description
4
2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
4B
NC
4A
NC
3Y
2B
GND
NC
3A
3B
The SN54LVC02A quadruple 2-input positiveNOR gate is designed for 2.7-V to 3.6-V VCC
operation and the SN74LVC02A quadruple
2-input positive-NOR gate is designed for 1.65-V
to 3.6-V VCC operation.
3
4Y
D
EPIC  (Enhanced-Performance Implanted
CMOS) Submicron Process
Typical VOLP (Output Ground Bounce)
< 0.8 V at VCC = 3.3 V, TA = 25°C
Typical VOHV (Output VOH Undershoot)
> 2 V at VCC = 3.3 V, TA = 25°C
Inputs Accept Voltages to 5.5 V
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
Latch-Up Performance Exceeds 250 mA Per
JESD 17
Package Options Include Plastic
Small-Outline (D), Shrink Small-Outline
(DB), Thin Shrink Small-Outline (PW)
Packages, Ceramic Flat (W), Chip Carriers
(FK), and DIPs (J)
1A
1Y
NC
VCC
D
NC – No internal connection
The ’LVC02A devices perform the Boolean
function Y = A + B or Y = A • B in positive logic.
Inputs can be driven from either 3.3-V or 5-V
devices. This feature allows the use of these
devices as translators in a mixed 3.3-V/5-V
system environment.
The SN54LVC02A is characterized for operation
over the full military temperature range of –55°C
to 125°C. The SN74LVC02A is characterized for
operation from –40°C to 85°C.
FUNCTION TABLE
(each gate)
INPUTS
A
B
OUTPUT
Y
H
X
L
X
H
L
L
L
H
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
Copyright  1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303
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1
SN54LVC02A, SN74LVC02A
QUADRUPLE 2-INPUT POSITIVE-NOR GATES
SCAS280I – JANUARY 1993 – REVISED OCTOBER 1998
logic symbol†
1A
1B
2A
2B
3A
3B
4A
4B
2
≥1
3
1
1Y
5
4
6
2Y
8
10
9
3Y
11
13
12
4Y
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, DB, J, PW, and W packages.
logic diagram, each gate (positive logic)
A
Y
B
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡
Supply-voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6.5 V
Input-voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6.5 V
Output-voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θJA (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127°C/W
DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The value of VCC is provided in the recommended operating conditions table.
3. The package thermal impedance is calculated in accordance with JESD 51.
2
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SN54LVC02A, SN74LVC02A
QUADRUPLE 2-INPUT POSITIVE-NOR GATES
SCAS280I – JANUARY 1993 – REVISED OCTOBER 1998
recommended operating conditions (see Note 4)
SN54LVC02A
VCC
VIH
Supply voltage
High-level input voltage
Operating
Data retention only
VIL
VI
VO
IOH
IOL
Low-level input voltage
MAX
MIN
MAX
2
3.6
1.65
3.6
1.5
1.5
UNIT
V
0.65 × VCC
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 1.65 V to 1.95 V
SN74LVC02A
MIN
V
1.7
2
2
0.35 × VCC
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
0.7
0.8
V
0.8
Input voltage
0
5.5
0
5.5
V
Output voltage
0
VCC
0
VCC
–4
V
High level output current
High-level
Low level output current
Low-level
VCC = 1.65 V
VCC = 2.3 V
VCC = 2.7 V
VCC = 3 V
–8
–12
–12
–24
–24
VCC = 1.65 V
VCC = 2.3 V
VCC = 2.7 V
VCC = 3 V
mA
4
8
12
12
24
24
mA
TA
Operating free-air temperature
–55
125
–40
85
°C
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
SN54LVC02A, SN74LVC02A
QUADRUPLE 2-INPUT POSITIVE-NOR GATES
SCAS280I – JANUARY 1993 – REVISED OCTOBER 1998
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
2.7 V to 3.6 V
IOH = –4 mA
IOH = –8 mA
∆ICC
1.2
V
1.7
2.7 V
2.2
2.2
3V
2.4
2.4
3V
2.2
2.2
1.65 V to 3.6 V
IOL = 100 µA
UNIT
VCC–0.2
2.3 V
IOH = –24 mA
II
ICC
SN74LVC02A
TYP†
MAX
MIN
VCC–0.2
1.65 V
IOH = –12
12 mA
VOL
MIN
1.65 V to 3.6 V
IOH = –100
100 µA
VOH
SN54LVC02A
TYP†
MAX
VCC
0.2
2.7 V to 3.6 V
0.2
IOL = 4 mA
IOL = 8 mA
1.65 V
0.45
2.3 V
0.7
IOL = 12 mA
IOL = 24 mA
2.7 V
0.4
0.4
3V
0.55
0.55
VI = 5.5 V or GND
VI = VCC or GND,
3.6 V
±5
±5
µA
3.6 V
10
10
µA
500
500
µA
IO = 0
One input at VCC – 0.6 V,
Other inputs at VCC or GND
Ci
VI = VCC or GND
† All typical values are at VCC = 3.3 V, TA = 25°C.
2.7 V to 3.6 V
3.3 V
5
V
5
pF
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 3)
SN54LVC02A
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tpd
A or B
Y
VCC = 2.7 V
MIN
VCC = 3.3 V
± 0.3 V
MAX
MIN
MAX
5.4
1
4.4
UNIT
ns
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figures 1 through 3)
SN74LVC02A
PARAMETER
tpd
FROM
(INPUT)
TO
(OUTPUT)
A or B
Y
VCC = 1.8 V
VCC = 2.5 V
± 0.2 V
TYP
MIN
MAX
13.4
1
7.4
VCC = 2.7 V
MIN
VCC = 3.3 V
± 0.3 V
UNIT
MAX
MIN
MAX
5.4
1
4.4
ns
1
ns
tsk(o)‡
‡ Skew between any two outputs of the same package switching in the same direction
operating characteristics, TA = 25°C
PARAMETER
Cpd
4
Power dissipation capacitance per gate
TEST
CONDITIONS
VCC = 1.8 V
TYP
VCC = 2.5 V
TYP
VCC = 3.3 V
TYP
UNIT
f = 10 MHz
7.5
8.5
9.5
pF
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN54LVC02A, SN74LVC02A
QUADRUPLE 2-INPUT POSITIVE-NOR GATES
SCAS280I – JANUARY 1993 – REVISED OCTOBER 1998
PARAMETER MEASUREMENT INFORMATION
VCC = 1.8 V ± 0.15 V
2 × VCC
S1
1 kΩ
From Output
Under Test
Open
GND
CL = 30 pF
(see Note A)
1 kΩ
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
Open
LOAD CIRCUIT
tw
VCC
Timing
Input
VCC/2
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
VCC/2
0V
tPLH
Output
Control
(low-level
enabling)
tPLZ
VCC
VCC/2
VCC/2
VOL
Output
Waveform 2
S1 at Open
(see Note B)
VOL + 0.15 V
VOL
tPHZ
tPZH
VOH
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VCC/2
VCC
VCC/2
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
0V
0V
tsu
Output
VCC
VCC/2
Input
VCC/2
VOH
VOH – 0.15 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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SN54LVC02A, SN74LVC02A
QUADRUPLE 2-INPUT POSITIVE-NOR GATES
SCAS280I – JANUARY 1993 – REVISED OCTOBER 1998
PARAMETER MEASUREMENT INFORMATION
VCC = 2.5 V ± 0.2 V
2 × VCC
S1
500 Ω
From Output
Under Test
Open
GND
CL = 30 pF
(see Note A)
500 Ω
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
Timing
Input
VCC/2
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
VCC/2
0V
tPLH
Output
Control
(low-level
enabling)
tPLZ
VCC
VCC/2
VCC/2
VOL
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.15 V
VOL
tPHZ
tPZH
VOH
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VCC/2
VCC
VCC/2
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
0V
0V
tsu
Output
VCC
VCC/2
Input
VCC/2
VOH
VOH – 0.15 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 2. Load Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN54LVC02A, SN74LVC02A
QUADRUPLE 2-INPUT POSITIVE-NOR GATES
SCAS280I – JANUARY 1993 – REVISED OCTOBER 1998
PARAMETER MEASUREMENT INFORMATION
VCC = 2.7 V AND 3.3 V ± 0.3 V
6V
S1
500 Ω
From Output
Under Test
Open
GND
CL = 50 pF
(see Note A)
500 Ω
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
6V
GND
tw
LOAD CIRCUIT
2.7 V
2.7 V
Timing
Input
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
th
2.7 V
Data
Input
1.5 V
1.5 V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
1.5 V
1.5 V
0V
tPLH
tPHL
VOH
1.5 V
2.7 V
Output
Control
(low-level
enabling)
1.5 V
1.5 V
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
tPLZ
3V
Output
Waveform 1
S1 at 6 V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
1.5 V
0V
tPZL
2.7 V
Output
Input
1.5 V
1.5 V
tsu
Input
1.5 V
1.5 V
tPZH
VOL + 0.3 V
VOL
tPHZ
1.5 V
VOH – 0.3 V
VOH
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 3. Load Circuit and Voltage Waveforms
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• DALLAS, TEXAS 75265
7
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