CSD25302Q2 www.ti.com SLPS234A – NOVEMBER 2009 – REVISED OCTOBER 2010 P-Channel NexFET™ Power MOSFET FEATURES 1 • • • • • • • PRODUCT SUMMARY Ultralow Qg and Qgd Low Thermal Resistance Avalanche Rated Pb Free Terminal Plating RoHS Compliant Halogen Free SON 2-mm × 2-mm Plastic Package VDS Drain to Source Voltage –20 V Qg Gate Charge Total (–4.5V) 2.6 nC Qgd Gate Charge Gate to Drain RDS(on) VGS(th) Drain to Source On Resistance mΩ VGS = –2.5V 56 mΩ VGS = –4.5V 39 mΩ –0.65 V ORDERING INFORMATION Battery Management Load Management Battery Protection Device Package Media CSD25302Q2 SON 2-mm × 2-mm Plastic Package 13-Inch Reel Qty Ship 3000 Tape and Reel ABSOLUTE MAXIMUM RATINGS DESCRIPTION TA = 25°C unless otherwise stated The device has been designed to deliver the lowest on resistance and gate charge in the smallest outline possible with excellent thermal characteristics in an ultra low profile. Low on resistance coupled with the extremely small footprint and low profile make the device ideal for battery operated space constrained applications. Top View S nC 71 Threshold Voltage APPLICATIONS • • • 0.5 VGS = –1.8V VALUE UNIT VDS Drain to Source Voltage –20 V VGS Gate to Source Voltage ±8 V Continuous Drain Current, TC = 25°C –5 A Continuous Drain Current(1) –5 A IDM Pulsed Drain Current, TA = 25°C(2) –20 A PD Power Dissipation 2.4 W TJ, TSTG Operating Junction and Storage Temperature Range –55 to 150 °C ID (1) Package Limited (2) Pulse duration 10 µs, duty cycle ≤2% 1 6 S 5 S 4 D S S 2 G 3 D P0112-01 RDS(on) vs VGS GATE CHARGE 6 ID = −3A 125 −VGS − Gate Voltage − V RDS(on) − On-State Resistance − mΩ 150 100 TC = 125°C 75 50 5 ID = −3A VDS = −10V 4 3 2 1 25 TC = 25°C 0 1 2 3 4 5 6 −VGS − Gate to Source Voltage − V 7 8 G006 0 0.0 0.5 1.0 1.5 2.0 Qg − Gate Charge − nC 2.5 3.0 G003 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2009–2010, Texas Instruments Incorporated CSD25302Q2 SLPS234A – NOVEMBER 2009 – REVISED OCTOBER 2010 www.ti.com ELECTRICAL CHARACTERISTICS TA = 25°C, unless otherwise specified PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Static Characteristics BVDSS Drain to Source Voltage VGS = 0V, IDS = –250mA IDSS Drain to Source Leakage VGS = 0V, VDS = –16V IGSS Gate to Source Leakage VDS = 0V, VGS = ±8V VGS(th) Gate to Source Threshold Voltage VDS = VGS, IDS = –250mA RDS(on) Drain to Source On Resistance gfs Transconductance –20 V –1 mA –100 nA –0.65 –0.9 V VGS = –1.8V, IDS = –3.0A 71 92 mΩ VGS = –2.5V, IDS = –3.0A 56 70 mΩ VGS = –4.5V, IDS = –3.0A 39 49 mΩ –0.5 VDS = –10V, IDS = –3.0A 12.3 S Dynamic Characteristics CISS Input Capacitance COSS Output Capacitance CRSS Reverse Transfer Capacitance Qg Gate Charge Total (–4.5V) Qgd Gate Charge – Gate to Drain Qgs Gate Charge Gate to Source Qg(th) Gate Charge at Vth QOSS Output Charge td(on) Turn On Delay Time tr Rise Time td(off) Turn Off Delay Time tf Fall Time VGS = 0V, VDS = –10V, f = 1MHz VDS = –10V, IDS = –3.0A VDS = –13V, VGS = 0V VDS = –10V, VGS = –4.5V, IDS = –3.0A, RG = 2Ω 270 350 pF 120 150 pF 40 55 pF 2.6 3.4 nC 0.5 nC 0.54 nC 0.2 nC 2.3 nC 3.2 ns 13.2 ns 8.6 ns 1.3 ns Diode Characteristics VSD Diode Forward Voltage Qrr Reverse Recovery Charge trr Reverse Recovery Time IDS = –3.0A, VGS = 0V –0.8 Vdd= –13V, IF = –3.0A, di/dt = 300A/ms –1.0 V 2.5 nC 8.8 ns THERMAL CHARACTERISTICS TA = 25°C, unless otherwise specified PARAMETER RqJC Thermal Resistance Junction to Case (1) RqJA Thermal Resistance Junction to Ambient (1) (2) (1) (2) 2 2 MIN TYP MAX UNIT 8.6 °C/W 66 °C/W 2 RqJC is determined with the device mounted on a 1-inch (6.45-cm ), 2-oz. (0.071-mm thick) Cu pad on a 1.5-inch × 1.5-inch (3.81-cm × 3.81-cm), 0.06-inch (1.52-mm) thick FR4 PCB. RqJC is specified by design, whereas RqJA is determined by the user’s board design. Device mounted on FR4 material with 1-inch2 (6.45-cm2), 2-oz. (0.071-mm thick) Cu. Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated CSD25302Q2 www.ti.com SLPS234A – NOVEMBER 2009 – REVISED OCTOBER 2010 GATE GATE Source Source Max RqJA = 66°C/W when mounted on 1 inch2 (6.45 cm2) of 2-oz. (0.071-mm thick) Cu. Max RqJA = 207°C/W when mounted on minimum pad area of 2-oz. (0.071-mm thick) Cu. DRAIN DRAIN M0161-02 M0161-01 TYPICAL MOSFET CHARACTERISTICS TA = 25°C, unless otherwise specified ZθJA − Normalized Thermal Impedance 10 1 0.5 0.3 0.1 Duty Cycle = t1/t2 0.1 0.05 P 0.01 0.02 0.01 t1 t2 Single Pulse 0.001 0.0001 0.001 Typical RθJA = 166°C/W (min Cu) TJ = P × ZθJA × RθJA 0.01 0.1 1 10 100 tP − Pulse Duration − s 1k G012 Figure 1. Transient Thermal Impedance Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback 3 CSD25302Q2 SLPS234A – NOVEMBER 2009 – REVISED OCTOBER 2010 www.ti.com TYPICAL MOSFET CHARACTERISTICS (continued) 5.0 5.0 4.5 4.5 4.0 4.0 3.5 −ID − Drain Current − A −ID − Drain Current − A TA = 25°C, unless otherwise specified VGS = −4.5V 3.0 VGS = −3.5V 2.5 VGS = −2.5V 2.0 VGS = −2V 1.5 1.0 VGS = −1.8V VDS = −5V 3.5 TC = 125°C 3.0 2.5 TC = 25°C 2.0 1.5 1.0 TC = −55°C 0.5 0.5 0.0 0.0 0.0 0.5 0.2 0.4 0.6 0.8 1.0 −VDS − Drain to Source Voltage − V 0.7 1.3 1.5 G002 Figure 3. Transfer Characteristics 6 0.4 ID = −3A VDS = −10V f = 1MHz VGS = 0V C − Capacitance − nF −VGS − Gate Voltage − V 1.1 −VGS − Gate to Source Voltage − V G001 Figure 2. Saturation Characteristics 5 0.9 4 3 2 0.3 COSS = CDS + CGD 0.2 CISS = CGD + CGS CRSS = CGD 0.1 1 0 0.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 Qg − Gate Charge − nC 0 5 G004 150 RDS(on) − On-State Resistance − mΩ −VGS(th) − Threshold Voltage − V 20 Figure 5. Capacitance 0.9 ID = −250µA 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 ID = −3A 125 100 TC = 125°C 75 50 25 TC = 25°C 0 −25 25 75 125 175 TC − Case Temperature − °C Figure 6. Threshold Voltage vs. Temperature 4 15 −VDS − Drain to Source Voltage − V G003 Figure 4. Gate Charge 0.0 −75 10 Submit Documentation Feedback G005 1 2 3 4 5 6 −VGS − Gate to Source Voltage − V 7 8 G006 Figure 7. On-State Resistance vs. Gate to Source Voltage Copyright © 2009–2010, Texas Instruments Incorporated CSD25302Q2 www.ti.com SLPS234A – NOVEMBER 2009 – REVISED OCTOBER 2010 TYPICAL MOSFET CHARACTERISTICS (continued) TA = 25°C, unless otherwise specified 10 1.4 ID = −3A VGS = −4.5V −ISD − Source to Drain Current − A Normalized On-State Resistance 1.6 1.2 1.0 0.8 0.6 0.4 0.2 0.0 −75 −25 25 75 125 175 TC − Case Temperature − °C 1 0.1 TC = 125°C 0.01 TC = 25°C 0.001 0.0001 0.0 0.2 0.4 0.6 0.8 1.0 −VSD − Source to Drain Voltage − V G007 Figure 8. Normalized On-State Resistance vs. Temperature G008 Figure 9. Typical Diode Forward Voltage 100 6 −ID − Drain Current − A −ID − Drain Current − A 5 10 1ms 1 0.1 0.01 0.01 10ms Area Limited by RDS(on) 100ms 1s 1 3 2 1 Single Pulse Typical RθJA = 166°C/W (min Cu) 0.1 4 DC 10 −VD − Drain Voltage − V Figure 10. Maximum Safe Operating Area Copyright © 2009–2010, Texas Instruments Incorporated 100 G009 0 −50 −25 0 25 50 75 100 125 150 175 TC − Case Temperature − °C G011 Figure 11. Maximum Drain Current vs. Temperature Submit Documentation Feedback 5 CSD25302Q2 SLPS234A – NOVEMBER 2009 – REVISED OCTOBER 2010 www.ti.com MECHANICAL DATA Q2 Package Dimensions D2 D K3 K1 K K2 4 4 5 6 8 K4 E 7 E1 E2 5 E3 6 Pin 1 Dot 2 3 3 L 1 Top View 2 1 Pin 1 ID e b D1 Pinout A A1 C Bottom View Source 1, 2, 5, 6, 8 Gate 3 Drain 4, 7 Front View M0175-01 DIM MILLIMETERS MIN NOM MAX MIN NOM MAX A 0.700 0.750 0.800 0.028 0.030 0.032 A1 0.000 0.050 0.000 b 0.250 0.350 0.010 0.300 C 0.203 TYP D 2.000 TYP D1 0.900 0.950 D2 0.300 TYP E 2.000 TYP E1 0.900 1.000 0.002 0.012 0.080 TYP 1.000 0.036 0.038 0.080 TYP 1.100 0.036 0.040 0.280 TYP 0.0112 TYP 0.470 TYP 0.0188 TYP e 0.650 BSC 0.026 TYP K 0.280 TYP 0.0112 TYP K1 0.350 TYP 0.014 TYP K2 0.200 TYP 0.008 TYP K3 0.200 TYP 0.008 TYP 0.470 TYP 0.200 Submit Documentation Feedback 0.25 0.040 0.012 TYP E3 L 0.014 0.008 TYP E2 K4 6 INCHES 0.044 0.0188 TYP 0.300 0.008 0.010 0.0121 Copyright © 2009–2010, Texas Instruments Incorporated CSD25302Q2 www.ti.com SLPS234A – NOVEMBER 2009 – REVISED OCTOBER 2010 Recommended PCB Pattern 1.40 0.85 1.05 0.22 2.30 1.10 0.65 TYP 1 0.46 0.40 TYP 0.25 M0167-01 Note: All dimensions are in mm, unless otherwise specified. For recommended circuit layout for PCB designs, see application note SLPA005 – Reducing Ringing through PCB Layout Techniques. Q2 Tape and Reel Information 4.00 ±0.10 Ø 1.50 ±0.10 4.00 ±0.10 Ø 1.00 ±0.25 1.00 ±0.05 2.30 ±0.05 10° Max 3.50 ±0.05 8.00 +0.30 –0.10 1.75 ±0.10 2.00 ±0.05 0.254 ±0.02 2.30 ±0.05 10° Max M0168-01 Notes: 1. Measured from centerline of sprocket hole to centerline of pocket 2. Cumulative tolerance of 10 sprocket holes is ±0.20 3. Other material available 4. Typical SR of form tape Max 108 OHM/SQ 5. All dimensions are in mm, unless otherwise specified. Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback 7 CSD25302Q2 SLPS234A – NOVEMBER 2009 – REVISED OCTOBER 2010 www.ti.com REVISION HISTORY Changes from Original (November 2009) to Revision A • 8 Page Deleted the Package Marking Information section ............................................................................................................... 8 Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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