TI SN65LVDS307ZQCT

SN65LVDS307
www.ti.com
SLLS834 – MAY 2007
PROGRAMMABLE 27-BIT PARALLEL-TO-SERIAL TRANSMITTER
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
FlatLink™ 3G Serial-Interface Technology
Compatible With FlatLink™3G Receivers Such
as SN65LVDS308
Input Supports Video Interfaces up to 24-Bit
RGB Data and 3 Control Bits Received Over
Two Differential Data Lines
SubLVDS Differential Voltage Levels
Up to 810-Mbps Data Throughput
Three Operating Modes to Conserve Power
– Active-Mode QVGA, 60 fps, 17.4 mW (typ)
– Active-Mode VGA, 60 fps, 28.8 mW (typ)
– Shutdown Mode ≈ 0.9 µW (typ)
– Standby Mode ≈ 0.9 µW (typ)
1.8-V Supply Voltage
ESD Rating > 3 kV (HBM)
Pixel Clock Range of 4 MHz–30 MHz
Failsafe on All CMOS Inputs
4-mm × 4-mm MicroStar Junior™µBGA®
Package With 0,5-mm Ball Pitch
Very Low EMI
FPC
cabling
typically
interconnects
the
SN65LVDS307 with the display. Compared to
parallel signaling, the SN65LVDS307 outputs
significantly reduce the EMI of the interconnect by
over 20 dB.
The SN65LVDS307 supports three power modes
(shutdown, standby, and active) to conserve power.
When transmitting, the PLL locks to the incoming
pixel clock, PCLK, and generates an internal
high-speed clock at the line rate of the data lines.
The parallel data are latched on the rising or falling
edge of PCLK, as selected by the external control
signal CPOL. The serialized data is presented on the
serial outputs D0 and D1, together with a recreated
PCLK that is generated from the internal high-speed
clock and output on CLK. If PCLK stops, the device
enters a standby mode to conserve power.
Flatlinkä3G
LCD
Driver
LVDS308
APPLICATIONS
CLK
•
•
•
LVDS307
Host-Controller to Display-Module Interface
Mobile Phones and Smart Phones
Portable Multimedia Players
DESCRIPTION
The SN65LVDS307 serializer device converts 27
parallel data inputs to one or two sub-low-voltage
differential signaling (SubLVDS) serial outputs. It
loads a shift register with 24 pixel bits and 3 control
bits from the parallel CMOS input interface. In
addition to the 27 data bits, the device adds a parity
bit and two reserved bits into a 30-bit data word.
Each word is latched into the device by the pixel
clock (PCLK). The parity bit (odd parity) allows a
receiver to detect single bit errors. The serial shift
register is uploaded at 30 or 15 times the pixel-clock
data rate, depending on the number of serial links
used. A copy of the pixel clock is output on a
separate differential output.
1
2
3
4
5
6
7
8
9
*
0
#
DATA
Application
Processor
with
RGB
Video
Interface
M0056-03
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
FlatLink, MicroStar Junior are trademarks of Texas Instruments.
µBGA is a registered trademark of Tessera, Inc..
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007, Texas Instruments Incorporated
SN65LVDS307
www.ti.com
SLLS834 – MAY 2007
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
DESCRIPTION (CONTINUED)
The link select line, LS, controls whether one or two serial links are used. The TXEN input may be used to put
the SN65LVDS307 in a shutdown mode. The SN65LVDS307 enters an active standby mode if the input clock,
PCLK, stops. This minimizes power consumption without the need for controlling an external terminal. The
SN65LVDS307 is characterized for operation over ambient air temperatures of –40°C to 85°C. All CMOS inputs
offer failsafe to protect the input from damage during power up and to avoid current flow into the device inputs
during power up. An input voltage of up to 2.165 V can be applied to all CMOS inputs while VDD is between 0 V
and 1.65 V.
Bit29
8
R[0:7]
Bit28 = 0
8
Bit27 = 0
G[0:7]
8
B[0:7]
[0..26]
HS
VS
DE
´15
1
2 ´ 15-Bit or 1 ´ 30-Bit Parallel-to-Serial Conversion
Parity
Calc
¸15
D0+
SubLVDS
D0–
D1+
SubLVDS
D1–
1
PCLK
CLK+
SubLVDS
´30
0
¸30
0
CLK–
LS
Low-Frequency
Detector
Standby, Shutdown and
Channel-Mode Controller
TXEN
Glitch
Supression
B0237-01
Figure 1. Functional Block Diagram
2
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SLLS834 – MAY 2007
PINOUT – TOP VIEW
ZQC PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
GND
G2
G4
G6
R0
R1
R3
B7
G1
G3
G7
R2
R6
GND
VDD
B6
G5
R4
R5
VDD
B5
B4
B3
G0
R7
GNDPLLD
LS
B1
B2
VS
D1+
VDDPLLD
PCLK
B0
GND
TST
D1–
A
B
C
D
E
GNDPLLA GNDLVDS
F
D0–
CLK+
(Tie to GND)
G
DE
HS
TXEN
D0+
CLK–
VDDPLLA VDDLVDS
P0063-01
Table 1. Numeric Terminal List
TERMINAL
SIGNAL
TERMINAL
SIGNAL
TERMINAL
SIGNAL
TERMINAL
SIGNAL
A1
GND
B7
GND
D6
GNDPLLD
F5
CLKP
A2
G2
C1
VDD
D7
LS
F6
TST
A3
G4
C2
B6
E1
B1
F7
D1–
A4
G6
C3
–
E2
B2
G1
HS
A5
R0
C4
G5
E3
VS
G2
DE
A6
R1
C5
R4
E4
GNDPLLA
G3
TXEN
A7
R3
C6
R5
E5
GNDLVDS
G4
D0+
B1
B7
C7
VDD
E6
D1+
G5
CLKN
B2
G1
D1
B5
E7
VDDPLLD
G6
VDDPLLA
B3
G3
D2
B4
F1
PCLK
G7
VDDLVDS
B4
G7
D3
B3
F2
B0
B5
R2
D4
G0
F3
GND
B6
R6
D5
R7
F4
D0–
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SLLS834 – MAY 2007
Table 2. Terminal Functions
NAME
I/O
D0+, D0–
D1+, D1–
DESCRIPTION
SubLVDS data link (active during normal operation)
SubLVDS out
SubLVDS data link (active during normal operation when LS = high; high impedance if LS =
low)
CLK+, CLK–
SubLVDS intput pixel clock; clock polarity is fixed.
R0–R7
Red pixel data (8)
G0–G7
Green pixel data (8)
B0–B7
Blue pixel data (8)
HS
Horizontal sync
VS
Vertical sync
DE
Data enable
PCLK
Input pixel clock (rising clock polarity)
LS
CMOS in
Link select (determines active SubLVDS data links and PLL range); see Table 3.
Disables the CMOS drivers and turns off the PLL, putting device in shutdown mode
1 – Transmitter enabled
0 – Transmitter disabled (shutdown)
TXEN
Note: The TXEN input incorporates glitch-suppression logic to avoid device malfunction on
short input spikes. It is necessary to pull TXEN high for longer than 10 µs to enable the
transmitter. It is necessary to pull the TXEN input low for longer than 10 µs to disable the
transmitter. At power up, the transmitter is enabled immediately if TXEN = 1 and disabled if
TXEN = 0.
TST
Test (TI internal use only); tie this pin permanently to GND.
VDD
Supply voltage
GND
Supply ground
VDDLVDS
SubLVDS I/O supply voltage
GNDLVDS
VDDPLLA
SubLVDS ground
PLL analog supply voltage
GNDPLLA
PLL analog GND
VDDPLLD
PLL digital supply voltage
GNDPLLD
PLL digital GND
(1)
4
Power supply (1)
For a multilayer PCB, it is recommended to keep one common GND layer underneath the device and connect all ground terminals
directly to this plane.
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FUNCTIONAL DESCRIPTION
SERIALIZATION MODES
The SN65LVDS307 transmitter has two modes of operation controlled by link-select terminal LS. Table 3 shows
the serializer modes of operation.
Table 3. Logic Table: Link Select Operating Modes
LS
Mode of Operation
Data-Link Status
0
1-channel mode, 1ChM (30-bit serialization rate)
D0 active; D1 high-impedance
1
2-channel mode, 2ChM (15-bit serialization rate)
D0, D1 active
1-CHANNEL MODE
While LS is held low, the SN65LVDS307 transmits payload data over a single SubLVDS data pair, D0. The PLL
locks to PCLK and internally multiplies the clock by a factor of 30. The internal high-speed clock is used to
serialize (shift out) the data payload on D0. Two reserved bits and the parity bit are added to the data frame.
Figure 2 illustrates the timing and the mapping of the data payload into the 30-bit frame. The internal high-speed
clock is divided by a factor of 30 to recreate the pixel clock, and presented on the SubLVDS CLK output. While
in this mode, the PLL can lock to a clock that is in the range of 4 MHz through 15 MHz. This mode is intended
for smaller video display formats (e.g. QVGA to HVGA) that do not require the full bandwidth capabilities of the
SN65LVDS307.
CLK–
CLK+
D0+/– CHANNEL res res CP R7 R6 R5 R4 R3 R2 R1 R0 G7 G6 G5 G4 G3 G2 G1 G0 B7 B6 B5 B4 B3 B2 B1 B0 VS HS DE res res CP R7 R6
T0161-01
Figure 2. Data and Clock Output in 1-Channel Mode (LS = Low).
2-CHANNEL MODE
While LS is held high, the SN65LVDS307 transmits payload data over two SubLVDS data pairs, D0 and D1. The
PLL locks to PCLK and internally multiplies it by a factor of 15. The internal high-speed clock is used to serialize
the data payload on D0 and D1. Two reserved bits and the parity bit are added to the data frame. Figure 3
illustrates the timing and the mapping of the data payload into the 30-bit frame and how the frame becomes split
into the two output channels. The internal high-speed clock is divided by 15 to recreate the pixel clock and
presented on SubLVDS CLK. The PLL can lock to a clock that is in the range of 8 MHz through 30 MHz in this
mode. Typical applications for using the 2-channel mode are HVGA and VGA displays.
CLK–
CLK +
D0+/– Channel CP R7 R6 R5 R4 R3 R2 R1 R0 G7 G6 G5 G4 VS res CP R7 R6
D1+/– Channel res G3 G2 G1 G0 B7 B6 B5 B4 B3 B2 B1 B0 HS DE res G3 G2
T0162-01
Figure 3. Data and Clock Output in 2-Channel Mode (LS = High).
POWER-DOWN MODES
The SN65LVDS307 transmitter has two power-down modes to facilitate efficient power management.
Shutdown Mode
The SN65LVDS307 enters shutdown mode when the TXEN terminal is asserted low. This turns off all
transmitter circuitry, including the CMOS input, PLL, serializer, and SubLVDS transmitter output stage. All
outputs are high-impedance. Current consumption in shutdown mode is nearly zero.
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Standby Mode
The SN65LVDS307 enters the standby mode if TXEN is high and the PCLK input signal frequency is less than
500 kHz. All circuitry except the PCLK input monitor is shut down, and all outputs enter the high-impedance
state. The current consumption in standby mode is very low. When the PCLK input signal is completely stopped,
the IDD current consumption is less than 10 µA. The PCLK input must not be left floating.
NOTE:
A floating (left open) CMOS input allows leakage currents to flow from VDD to GND.
To prevent large leakage current, a CMOS gate must be kept at a valid logic level,
either VIH or VIL. This can be achieved by applying an external voltage of VIH or VIL to
all SN65LVDS307 inputs.
ACTIVE MODES
When TXEN is high and the PCLK input clock signal is faster than 3 MHz, the SN65LVDS307 enters the active
mode. Current consumption in the active mode depends on operating frequency and the number of data
transitions in the data payload.
Acquire Mode (PLL Approaches Lock)
The PLL is enabled and attempts to lock to the input clock. All outputs remain in the high-impedance state.
When the PLL monitor detects stable PLL operation, the device switches from the acquire mode to the transmit
mode. For proper device operation, the pixel clock frequency must fall within the valid fPCLK range specified
under recommended operating conditions. If the pixel clock frequency is higher than 3 MHz but lower than
fPCLK(min), the SN65LVDS307 PLL is enabled. Under such conditions, it is possible for the PLL to lock
temporarily to the pixel clock, causing the PLL monitor to release the device into transmit mode. If this happens,
the PLL may or may not be properly locked to the pixel clock input, potentially causing data errors, frequency
oscillation, and PLL deadlock (loss of VCO oscillation).
Transmit Mode
After the PLL achieves lock, the device enters the normal transmit mode. The CLK terminal outputs a copy of
PCLK. Based on the selected mode of operation, the D0 and D1 outputs carry the serialized data. In 1-channel
mode, the D1 outputs remain in the high-impedance state.
PARITY BIT GENERATION
The SN65LVDS307 transmitter calculates the parity of the transmit data word and sets the parity bit accordingly.
The parity bit covers the 27-bit data payload consisting of 24 bits of pixel data plus VS, HS and DE. The two
reserved bits are not included in the parity generation. Odd-parity bit signaling is used. The transmitter sets the
parity bit if the sum of the 27 data bits results in an even number of ones. The parity bit is cleared otherwise.
This allows the receiver to verify parity and detect single bit errors.
6
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STATUS DETECT AND OPERATING MODES FLOW DIAGRAM
The SN65LVDS307 switches between the power saving and active modes in the following way:
Power Up
TXEN = 1
PCLK Input Inactive
TXEN Low
for > 10 ms
Power Up
TXEN = 0
Shutdown
Mode
Standby
Mode
TXEN High
for > 10 ms
PCLK Stops or Lost
TXEN Low
for > 10 ms
PCLK Stops or Lost
PCLK Input Active
Power Up
TXEN = 1
PCLK Active
TXEN Low
for > 10 ms
Transmit
Mode
PLL Achieved Lock
Acquire
Mode
F0017-02
Figure 4. Status Detect and Operating Modes Flow Diagram
Table 4. Status Detect and Operating Modes Descriptions
Mode
Characteristics
Conditions
TXEN is low for longer than 10 µs. (1) (2)
Shutdown mode
Least amount of power consumption (most circuitry turned
off); all outputs are high-impedance.
Standby mode
Low power consumption (only clock activity circuit active; PLL TXEN is high for longer than 10 µs; PCLK input
is disabled to conserve power); all outputs are
signal is missing or inactive. (2)
high-impedance.
Acquire mode
PLL tries to achieve lock; all outputs are high-impedance.
TXEN is high; PCLK input monitor detected input
activity.
Transmit mode
Data transfer (normal operation); transmitter serializes data
and transmits data on serial output; unused outputs remain
high-impedance.
TXEN is high and PLL is locked to incoming clock.
(1)
(2)
In shutdown mode, all SN65LVDS307 internal switching circuits (e.g., PLL, serializer, etc.) are turned off to minimize power
consumption. The input stage of any input terminal remains active.
Leaving inputs unconnected can cause random noise to toggle the input stage and potentially harm the device. All CMOS inputs must
be tied to a valid logic level, VIL or VIH, during shutdown or standby mode.
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Table 5. Operating Mode Transitions
MODE TRANSITION
Shutdown → standby
USE CASE
TRANSITION SPECIFICS
Drive TXEN high to enable
transmitter
1. TXEN high > 10 µs
2. Transmitter enters standby mode.
a. All outputs are high-impedance.
b. Transmitter turns on clock input monitor.
Standby → acquire
Transmitter activity detected
1. PCLK input monitor detects clock input activity.
2. Outputs remain high-impedance.
3. PLL circuit is enabled.
Acquire → transmit
Link is ready to transfer data
1. PLL is active and approaches lock.
2. PLL achieved lock within twakeup.
3. Parallel data input latches into shift register.
4. CLK output turns on.
5. Selected data outputs turn on and send out first serial data bit.
Transmit → standby
Request transmitter to enter
standby mode by stopping
PCLK
1. PCLK input monitor detects missing PCLK.
2. Transmitter indicates standby, putting all outputs into high-impedance.
3. PLL shuts down.
4. PCLK activity input monitor remains active.
Transmit/standby →
shutdown
Turn off transmitter
1. TXEN pulled low for longer than tpwrdn.
2. Transmitter indicates standby, putting output CLK+ and CLK– into
high-impedance state.
3. Transmitter puts all other outputs into high-impedance state.
4. Most IC circuitry is shut down for least power consumption.
ORDERING INFORMATION
PART NUMBER
Package
SHIPPING METHOD
SN65LVDS307ZQCR
ZQC
Reel
ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VDD (2), VDDPLLA, VDDPLLD, VDDLVDS
Voltage range at any input When VDDx > 0 V
or output terminal
When VDDx ≤ 0 V
Human-body model (3) (all terminals)
Electrostatic discharge
Charged-device model (4) (all terminals)
Machine
model (5)
(all terminals)
Continuous power dissipation
(1)
(2)
(3)
(4)
(5)
8
VALUE
UNIT
–0.3 to 2.175
V
–0.5 to 2.175
V
–0.5 to VDD + 2.175
V
±3
kV
±500
±200
V
See Dissipation Ratings table
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to the GND terminals.
In accordance with JEDEC Standard 22, Test Method A114-A.
In accordance with JEDEC Standard 22, Test Method C101.
In accordance with JEDEC Standard 22, Test Method A115-A
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DISSIPATION RATINGS
(1)
(2)
PACKAGE
CIRCUIT
BOARD MODEL
TA < 25°C
DERATING FACTOR (1)
ABOVE TA = 25°C
TA = 85°C
POWER RATING
ZQC
Low-K (2)
496 mW
6.21 mW/°C
124 mW
This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.
In accordance with the low-K thermal metric definitions of EIA/JESD51-2.
THERMAL CHARACTERISTICS
PARAMETER
PD
TEST CONDITIONS
Typical
VDDx = 1.8 V, TA = 25°C, 2-channel
mode
Maximum
VDDx = 1.95 V, TA = –40°C
Device power dissipation
VALUE
PCLK at 4 MHz
14.4
PCLK at 30 MHz
38.2
PCLK at 4 MHz
22.3
PCLK = 30 MHz
50.2
UNIT
mW
mW
RECOMMENDED OPERATING CONDITIONS (1)
VDD
VDDPLLA
VDDPLLD
VDDLVDS
VDDn(PP)
fPCLK
Supply voltages
Supply voltage noise
magnitude 50 MHz (all
supplies)
Pixel clock frequency
MIN
NOM
MAX
UNIT
1.65
1.8
1.95
V
100
mV
Test setup see Figure 10
f(noise) = 1Hz to 2 GHz
1-channel transmit mode, see Figure 2
4
15
2-channel transmit mode, see Figure 3
8
30
0.5
3
Frequency threshold, standby mode to active
mode (2), see Figure 14
MHz
tH × fPCLK
PCLK input duty cycle
0.33
0.67
TA
Operating free-air
temperature
–40
85
°C
5
ps-rms
jitter (3)
tjit(per)PCLK
PCLK RMS period
tjit(TJ)PCLK
PCLK total jitter
tjit(CC)PCLK
PCLK peak
cycle-to-cycle jitter (4)
Measured on PCLK input
0.05/fPCLK
s
0.02/fPCLK
s
VDD
V
0.3 VDD
V
PCLK, R[0:7], G[0:7], B[0:7], VS, HS, DE, PCLK, LS, TXEN
VIH
High-level input voltage
VIL
Low-level input voltage
tDS
Data setup time prior to
PCLK transition
tDH
(1)
(2)
(3)
(4)
Data hold time after PCLK
transition
0.7 VDD
2
ns
2
ns
f(PCLK) = 30 MHz; see Figure 6
Unused single-ended inputs must be held high or low to prevent them from floating.
PCLK input frequencies lower than 500 kHz force the SN65LVDS307 into standby mode. Input frequencies between 500 kHz and 3
MHz may or may not activate the SN65LVDS307. Input frequencies beyond 3 MHz activate the SN65LVDS307.
Period jitter is the deviation in cycle time of a signal with respect to the ideal period over a random sample of 100,000 cycles.
Cycle-to-cycle jitter is the variation in cycle time of a signal between adjacent cycles over a random sample of 1,000 adjacent cycle
pairs.
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DEVICE ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
1ChM
IDD
2ChM
MIN
VDD = VDDPLLA = VDDPLLD = VDDLVDS,
RL(PCLK) = RL(Dx) = 100 Ω, VIH = VDD, VIL = 0 V,
TXEN at VDD,
alternating 1010 serial bit pattern
fPCLK = 4 MHz
9
11.4
fPCLK = 6 MHz
10.6
12.6
fPCLK = 15 MHz
16
18.8
VDD = VDDPLLA = VDDPLLD = VDDLVDS,
RL(PCLK) = RL(Dx) = 100 Ω, VIH = VDD, VIL = 0 V,
TXEN at VDD,
typical power test pattern (see Table 7)
fPCLK = 4 MHz
8
fPCLK = 6 MHz
8.9
fPCLK = 15 MHz
14
VDD = VDDPLLA = VDDPLLD = VDDLVDS,
RL(PCLK) = RL(Dx) = 100 Ω, VIH = VDD, VIL = 0 V,
TXEN at VDD,
alternating 1010 serial bit pattern
fPCLK = 8 MHz
13.7
fPCLK = 22 MHz
18.4
22
fPCLK = 30 MHz
21.4
25.8
VDD = VDDPLLA = VDDPLLD = VDDLVDS,
RL(PCLK) = RL(Dx) = 100 Ω, VIH = VDD, VIL = 0 V,
TXEN at VDD,
typical power test pattern (see Table 8)
fPCLK = 8 MHz
11.5
Standby mode
Shutdown mode
(1)
TYP (1) MAX
UNIT
mA
mA
15.9
mA
fPCLK = 22 MHz
16
fPCLK = 30 MHz
19.1
VDD = VDDPLLA =
VDDPLLD = VDDLVDS,
RL(PCLK) = RL(Dx) = 100 Ω,
VIH = VDD, VIL = 0 V, all
inputs held static high or
static low
0.61
10
µA
0.55
10
µA
mA
All typical values are at 25°C and with 1.8-V supply unless otherwise noted.
OUTPUT ELECTRICAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP (1)
MAX
UNIT
SubLVDS Output (D0+, D0–, D1+, D1–, CLK+, and CLK–)
VOC(SS)M
Steady-state common-mode output voltage
VOCM(SS)
Change in steady-state common-mode output voltage
VOCM(PP)
Peak-to-peak common mode output voltage
|VOD|
Differential output voltage magnitude
|VDx+ – VDx– |, |VCLK+ – VCLK– |
∆|VOD|
Change in differential output voltage between logic states
ZOD(CLK)
Differential small-signal output impedance
TXEN at VDD
IOSD
Differential short-circuit output current
VOD = 0 V, fPCLK = 28 MHz
IOS
Short circuit output current (2)
VO = 0 V or VDD
High-impedance state output current
VO = 0 V or VDD(max),
TXEN at GND
IOZ
(1)
(2)
Output load see Figure 8
0.8
0.9
–10
100
150
–10
1
V
10
mV
75
mV
200
mV
10
mV
10
mA
Ω
210
5
mA
–3
3
MIN
TYP (1) MAX
µA
All typical values are at 25°C and with 1.8-V supply, unless otherwise noted.
All SN65LVDS307 outputs tolerate shorts to GND or VDD without device damage.
INPUT ELECTRICAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
UNIT
R[0:7], G[0:7], B[0:7], VS, HS, DE, PCLK, LS, TXEN
IIH
High-level input current
VIN = 0.7 × VDD
–200
200
IIL
Low-level input current
VIN = 0.3 × VDD
–200
200
CIN
Input capacitance
(1)
10
1.5
All typical values are at 25°C and with 1.8-V supply, unless otherwise noted.
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SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TYP (1)
MIN
MAX
tr
20%-to-80% differential
output signal rise time
See Figure 7 and Figure 8
250
500
tf
20%-to-80% differential
output signal fall time
See Figure 7 and Figure 8
250
500
fBW
PLL bandwidth (3-dB cutoff
frequency)
Tested from PCLK input to
CLK output, See Figure 5 (2)
tpd(L)
Propagation delay time,
input to serial output (data
latency Figure 9)
TXEN at VDD, VIH = VDD,
VIL = GND, RL = 100 Ω
tH × fCLK0
Output CLK duty cycle
tGS
TXEN glitch suppression
pulse duration (3)
VIH = VDD, VIL = GND, TXEN toggles between VIL and VIH,
see Figure 12 and Figure 13.
tpwrup
Enable time from power
down (↑TXEN)
Time from TXEN pulled high to CLK and Dx outputs
enabled and transmit valid data; see Figure 13
tpwrdn
Disable time from active
mode (↓TXEN)
TXEN is pulled low during transmit mode; time
measurement until output is disabled and PLL is shut
down; see Figure 13
twakup
Enable time from standby
(↕PCLK)
TXEN at VDD; device in standby; time measurement from
PCLK starts switching to CLK and Dx outputs enabled and
transmit valid data; see Figure 13
tsleep
Disable time from active
mode (PCLK stopping)
TXEN at VDD; device is transmitting; time measurement
from PCLK input signal halt until CLK + Dx outputs are
disabled and PLL is disabled; see Figure 13
(3)
fPCLK = 22 MHz
0.082 fPCLK
fPCLK = 30 MHz
0.078 fPCLK
1-channel mode
0.8/fPCLK
1/fPCLK
1.2/fPCLK
2-channel mode
1/fPCLK
1.21/fPCLK
1.5/fPCLK
1-channel mode
0.45
0.50
0.55
2-channel mode
0.49
0.53
0.58
MHz
s
10
µs
0.24
2
ms
0.5
11
µs
0.23
2
ms
0.4
100
µs
3.8
All typical values are at 25°C and with 1.8-V supply unless otherwise noted.
The maximum limit is based on statistical analysis of the device performance over process, voltage, and temperature ranges. This
parameter is functionality tested only on automatic test equipment (ATE).
The TXEN input incorporates glitch-suppression circuitry to disregard short input pulses. tGS is the duration of either a high-to-low or
low-to-high transition that is suppressed.
12
PLL BW (% of PCLK Frequency) − %
ps
11
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
9.0
4 MHz:
8.5%
9%
9
8.5 %
8
8.1 %
7.6 %
7
6
4
0
100
200
300
400
f − PLL Frequency − MHz
500
Spec
Limit
2 ChM
Spec
Limit
1 ChM
8.0
7.5
15
MHz:
7.6%
7.0
30 MHz:
7.6%
6.5
TX PLL BW
5
8 MHz:
8.5%
8.5
RX PLL BW
10
PLL Bandwidth − %
(1)
(2)
UNIT
6.0
600
0
G001
5
10
15
20
25
30
f − PCLK Frequency − MHz
35
40
G002
Figure 5. SN65LVDS307 PLL Bandwidth (Also Showing the SN65LVDS308 PLL Bandwidth)
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TIMING CHARACTERISTICS
PARAMETER
tPPOSX
Output pulse position,
↕serial data to ↑CLK; see
(1) (2) and Figure 11
TEST CONDITIONS
MIN
1ChM: x = 0..29, fPCLK = 15 MHz; TXEN
at VDD, VIH = VDD, VIL = GND, RL =
100 Ω, test pattern as in Table 11 (3)
x
- 330 ps
30 × fPCLK
x
+ 330 ps
30 × fPCLK
x – 0.1845
30 × fPCLK
x + 0.1845
30 × fPCLK
x
- 330 ps
15 × fPCLK
x
+ 330 ps
15 × fPCLK
x – 0.1845
15 × fPCLK
x + 0.1845
15 × fPCLK
1ChM: x = 0..29,
fPCLK = 4 MHz to 15 MHz
2ChM: x = 0..14, fPCLK = 30 MHz
TXEN at VDD, VIH = VDD, VIL = GND,
RL = 100 Ω, test pattern as in Table 12 (3)
2ChM: x = 0..14,
fPCLK = 8 MHz to 30 MHz
(1)
(2)
(3)
(4)
(4)
(4)
TYP
MAX
ps
This number also includes the high-frequency random and deterministic PLL clock jitter that is not traceable by the SN65LVDS308
receiver PLL; tPPosx represents the total timing uncertainty of the transmitter necessary to calculate the jitter budget when combined
with the SN65LVDS308 receiver.
The pulse position min/max variation is given with a bit error rate target of 10–12; the measurement estimates the random jitter
contribution to the total jitter by multiplying the random RMS jitter by a factor of 14; measurements of the total jitter are taken with > 1012
samples.
The minimum and maximum limits are based on statistical analysis of the device performance over process, voltage, and temperature
ranges. This parameter is functionality tested only on automatic test equipment (ATE).
These minimum and maximum limits are simulated only.
PARAMETER MEASUREMENT INFORMATION
t DS
VIH
R[7:0], G[7:0], B[7:0];
VS, HS, DE, LS, TXEN
VIL
t DH
VIH
PCLK
VIL
tR
T0249-01
Figure 6. Setup/Hold Time
VOD
150 mV (Nom)
tf
tr
80%
0V
20%
–150 mV (Nom)
T0167-02
Figure 7. Rise and Fall Time Definitions
12
UNIT
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PARAMETER MEASUREMENT INFORMATION (continued)
R1 = 49.9 W
CLK+, Dx+
VDx+ or VCLK+
975 mV (Nom)
VDx– or VCLK–
825 mV (Nom)
VOD
VOCM
CLK–, Dx–
VOCM
R2 = 49.9 W
SN65LVDS307
C3 = 1 pF
C1 = 1 pF
VOCM(pp)
VOCM(ss)
C2 = 1 pF
NOTES:
A. 20-MHz output test pattern on all differential outputs (CLK, D0, and D1):
this is achieved by: 1. Device is set to 2-channel mode.
2. fPCLK = 20 MHz
3. Inputs R[7:3] = B[7:3] connected to VDD, all other data inputs set to GND.
B. C1, C2, and C3 include instrumentation and fixture capacitance, tolerance ±20%; C, R1, and R2 tolerance ±1%
C. The measurement of VOCM(pp) and VOC(ss) are taken with test equipment bandwidth >1 GHz.
S0263-01
Figure 8. Driver Output Voltage Test Circuit and Definitions
CMOS
Data In
pixel (n)
pixel (n+1)
R7(n−1)
R7(n)
R7(n+1)
R6(n−1)
R6(n)
R6(n+1)
VDD /2
PCLK
t PROP
CLK−
CLK+
D0+
CP R7 R6
CP R7 R6
pixel (n−1)
pixel (n−2)
R7(n−1)
R6(n−1)
R7(n)
R6(n)
T0258-01
Figure 9. tpd(L) Propagation Delay Input to Output (LS = 0)
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PARAMETER MEASUREMENT INFORMATION (continued)
1
1
Noise
Generator
100 mV
VDDPLLA
2
SN65LVDS307
VDDPLLD
VDD
10 mF
VDDLVDS
GND
1.8-V
Supply
Note: The generator regulates the
noise amplitude at point 1 to the
target amplitude given under the table
Recommended Operating Conditions
S0216-03
Figure 10. Power Supply Noise Test Setup
tCLK+
CLK–
CLK+
Current Cycle
D[0:m]±
Bit 0
Bit1
Next Cycle
Bitx
Bit2
Bit0
Bit1
tPPOS0
tPPOS1
Note:
1-Channel Mode: x = 0...29; m = 0
2-Channel Mode: x = 0...14; m = 1
tPPOS2
tPPOSx
T0250-01
Figure 11. tSK(0) SubLVDS Output Pulse Position Measurement
TXEN
VDD/2
tGS
PCLK
VCO Internal Signal
PLL Approaches Lock
tpwrup
CLK
D0, D1
T0251-01
Figure 12. Transmitter Behavior While Approaching Sync
14
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PARAMETER MEASUREMENT INFORMATION (continued)
3 ms
<20 ns
Glitch Shorter
Than tGS Will Be
Ignored
2 ms
Less Than 20 ns
Spike Will be
Rejected
Glitch Shorter
Than tGS Will Be
Ignored
TXEN
tpwrup
tpwrdn
CLK+
tGS
ICC
tGS
PCLK
Transmitter Disabled
(OFF)
Transmitter Aquires Lock
Transmitter Enabled
(ON)
Transmitter
Turns OFF
Transmitter
Disabled
(OFF)
T0252-01
Figure 13. Transmitter Enable Glitch Suppression Time
PCLK
twakeup
tsleep
CLK+
Transmitter Disabled
(OFF)
Transmitter Aquires Lock,
Outputs Still Disabled
Transmitter Enabled,
Output Data Valid
Transmitter
Enabled,
Output Data
Valid
Transmitter
Disabled
(OFF)
T0253-01
Figure 14. Standby Detection
Power Consumption Tests
Table 6 shows an example test pattern word.
Table 6. Example Test Pattern Word
7
Word
R[7:4], R[3:0], G[7:4], G[3:0], B[7:4], B[3:0], 0, VS, HS, DE
1
0x7C3E1E7
C
3
E
1
R7 R6 R5 R4 R3 R2 R1 R0 G7 G6 G5 G4 G3 G2 G1 G0 B7
0
1
1
1
1
1
0
0
0
0
1
1
1
1
1
0
E
7
B6
B5
B4
B3
B2
B1
B0
0
0
0
1
1
1
1
0
0
0
VS HS DE
1
1
1
Typical IC Power-Consumption Test Pattern
The typical power-consumption test pattern consists of 16 30-bit transmit words in 1-channel mode, eight 30-bit
transmit words in 2-channel mode. The pattern repeats itself throughout the entire measurement. It is assumed
that every possible transmit code on RGB inputs has the same probability to occur during typical device
operation.
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Table 7. Typical IC Power-Consumption Test Pattern,
1-Channel Mode
Word
Test Pattern:
R[7:4], R[3:0], G[7:4], G[3:0], B[7:4], B[3:0], 0, VS, HS, DE
1
0x0000007
2
0xFFF0007
3
0x01FFF47
4
0xF0E07F7
5
0x7C3E1E7
6
0xE707C37
7
0xE1CE6C7
8
0xF1B9237
9
0x91BB347
10
0xD4CCC67
11
0xAD53377
12
0xACB2207
13
0xAAB2697
14
0x5556957
15
0xAAAAAB3
16
0xAAAAAA5
Table 8. Typical IC Power-Consumption Test Pattern,
2-Channel Mode
Word
Test Pattern:
R[7:4], R[3:0], G[7:4], G[3:0], B[7:4], B[3:0], 0, VS, HS, DE
1
0x0000001
2
0x03F03F1
3
0xBFFBFF1
4
0x1D71D71
5
0x4C74C71
6
0xC45C451
7
0xA3AA3A5
8
0x5555553
Maximum Power Consumption Test Pattern
The maximum (or worst-case) power consumption of the SN65LVDS307 is tested using the two different test
patterns shown in Table 9. Test patterns consists of sixteen 30-bit transmit words in 1-channel mode, eight
30-bit transmit words in 2-channel mode. The pattern repeats itself throughout the entire measurement. It is
assumed that every possible transmit code on RGB inputs has the same probability to occur during typical
device operation.
Table 9. Worst-Case Power-Consumption
Test Pattern 1
Word
16
Test Pattern:
R[7:4], R[3:0], G[7:4], G[3:0], B[7:4], B[3:0], 0, VS, HS, DE
1
0xAAAAAA5
2
0x5555555
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Table 10. Worst-Case Power-Consumption
Test Pattern 2
Word
Test Pattern:
R[7:4], R[3:0], G[7:4], G[3:0], B[7:4], B[3:0], 0, VS, HS, DE
1
0x0000000
2
0xFFFFFF7
Output Skew Pulse Position and Jitter Performance
The following test patterns are used to measure the output skew pulse position and the jitter performance of the
SN65LVDS307. The jitter test patterns stress the interconnect for worst-case ISI. Each pattern is self-repeating
for the duration of the test.
Table 11. Transmit Jitter Test Pattern, 1-Channel Mode
Word
Test Pattern:
R[7:4], R[3:0], G[7:4], G[3:0], B[7:4], B[3:0], 0, VS, HS, DE
1
0x0000001
2
0x0000031
3
0x00000F1
4
0x00003F1
5
0x0000FF1
6
0x0003FF1
7
0x000FFF1
8
0x0F0F0F1
9
0x0C30C31
10
0x0842111
11
0x1C71C71
12
0x18C6311
13
0x1111111
14
0x3333331
15
0x2452413
16
0x22A2A25
17
0x5555553
18
0xDB6DB65
19
0xCCCCCC1
20
0xEEEEEE1
21
0xE739CE1
22
0xE38E381
23
0xF7BDEE1
24
0xF3CF3C1
25
0xF0F0F01
26
0xFFF0001
27
0xFFFC001
28
0xFFFF001
29
0xFFFFC01
30
0xFFFFF01
31
0xFFFFFC1
32
0xFFFFFF1
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Table 12. Transmit Jitter Test Pattern, 2-Channel Mode
Word
18
Test Pattern:
R[7:4], R[3:0], G[7:4], G[3:0], B[7:4], B[3:0], 0, VS, HS, DE
1
0x0000001
2
0x000FFF3
3
0x8008001
4
0x0030037
5
0xE00E001
6
0x00FF001
7
0x007E001
8
0x003C001
9
0x0018001
10
0x1C7E381
11
0x3333331
12
0x555AAA5
13
0x6DBDB61
14
0x7777771
15
0x555AAA3
16
0xAAAAAA5
17
0x5555553
18
0xAAA5555
19
0x8888881
20
0x9242491
21
0xAAA5571
22
0xCCCCCC1
23
0xE3E1C71
24
0xFFE7FF1
25
0xFFC3FF1
26
0xFF81FF1
27
0xFE00FF1
28
0x1FF1FF1
29
0xFFCFFC3
30
0x7FF7FF1
31
0xFFF0007
32
0xFFFFFF1
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TYPICAL CHARACTERISTICS
POWERDOWN, STANDBY SUPPLY CURRENT
vs TEMPERATURE
SUPPLY CURRENT IDD vs TEMPERATURE
1
20
IDD − Supply Current − mA
IDDQ − Supply Current − µA
2-Channel Mode, 22 MHz (VGA)
Standby Current
Power−Down Current
0.1
−50
−30
−10
10
30
50
T − Temperature − °C
70
15
2-Channel Mode, 11 MHz (HVGA)
10
5
0
−50
90
−30
G003
Figure 15.
10
30
50
T − Temperature − °C
70
90
G004
Figure 16.
SUPPLY CURRENT vs PCLK FREQUENCY
DIFFERENTIAL OUTPUT SWING vs PCLK FREQUENCY
200
VOD − Differential Output Swing − mV
30
IDD − Supply Current − mA
−10
25
20
2-Channel Mode
15
10
1-Channel Mode
5
190
85°C
180
170
–40°C
160
25°C
150
140
130
120
110
100
0
5
10
15
20
f − PCLK Frequency − MHz
25
30
0
5
G005
10
15
20
f − PCLK Frequency − MHz
25
G006
Figure 17.
Figure 18.
PLL BANDWIDTH
CYCLE-TO-CYCLE OUTPUT JITTER
vs PCLK FREQUENCY
10.0
30
500
9.5
Spec Limit
1 ChM
4 MHz: 8.5% Spec Limit 2 ChM 8 MHz: 8.5%
8.5
400
CC Output Jitter − ps
PLL Bandwidth − %
9.0
8.0
7.5
Spec Limit 1
ChM
15 MHz: 7.6%
7.0
Spec Limit 2
ChM
30 MHz: 7.6%
6.5
6.0
300
200
100
2-ChM
5.5
1-Channel Mode
5.0
2-Channel Mode
0
0
5
10
15
20
25
30
f − PCLK Frequency − MHz
35
40
0
G007
Figure 19.
5
10
15
20
f − PCLK Frequency − MHz
25
30
G008
Figure 20.
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TYPICAL CHARACTERISTICS (continued)
CYCLE-TO-CYCLE OUTPUT JITTER
vs TEMPERATURE
OUTPUT PULSE POSITION vs TEMPERATURE
120
tPPOS − Output Pulse Position − ps
CC Output Jitter − ps
200
2-Channel Mode,
f(PCLK) = 11 MHz
150
100
1-Channel Mode,
f(PCLK) = 22 MHz
50
0
−50
−25
0
25
50
T − Temperature − °C
75
2-Channel Mode,
11 MHz (VGA)
100
80
60
2-Channel Mode,
22 MHz (HVGA)
40
20
0
−50
100
−25
0
25
50
T − Temperature − °C
G009
Figure 21.
OUTPUT RETURN LOSS
Output Common-Mode Noise Rejection − dB
Output Return Loss − dB
D0
−10
D1
−15
500
1000
f − Frequency − MHz
1500
0
−5
D0
CLK
−10
D1
−15
−20
2000
0
500
G011
1000
f − Frequency − MHz
Figure 23.
Figure 24.
CROSSTALK
0
Isolation − dB
−20
−40
D0 to D1
−60
−80
−100
0
500
1000
f − Frequency − MHz
1500
Figure 25.
20
G010
OUTPUT COMMON MODE NOISE REJECTION
−5
0
100
Figure 22.
0
CLK
75
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G013
1500
2000
G012
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APPLICATION INFORMATION
Preventing Increased Leakage Currents in Control Inputs
A floating (left open) CMOS input allows leakage currents to flow from VDD to GND. Do not leave any CMOS
input unconnected or floating. Every input must be connected to a valid logic level, VIH or VIL, while power is
supplied to VDD. This also minimizes the power consumption of standby and power-down modes.
Power Supply Design Recommendation
For a multilayer PCB, it is recommended to keep one common GND layer underneath the device and connect all
ground terminals directly to this plane.
Decoupling Recommendation
The SN65LVDS307 was designed to operate reliably in a constricted environment with other digital switching
ICs. In cell phone designs, the SN65LVDS307 often shares a power supply with other ICs. The SN65LVDS307
can operate with power-supply noise as specified in Recommend Operating Conditions. To minimize the
power-supply noise floor, provide good decoupling near the SN65LVDS307 power terminals. The use of four
ceramic capacitors (2 × 0.01 µF and 2 × 0.1 µF) provides good performance. At the very least, it is
recommended to install one 0.1-µF and one 0.01-µF capacitor near the SN65LVDS307. To avoid large current
loops and trace inductance, the trace length between decoupling capacitor and IC power inputs terminals must
be minimized. Placing the capacitor underneath the SN65LVDS307 on the bottom of the PCB is often a good
choice.
VGA Application
Figure 26 shows a possible implementation of a 640- × 480-pixel VGA display. The SN65LVDS307 interfaces to
the SN65LVDS308, which is the corresponding receiver device, to deserialize the data and drive the display
driver. The pixel clock rate of 22 MHz assumes ~20% blanking overhead and 60-Hz display refresh rate. The
application assumes 24-bit color resolution. Also shown is how the application processor provides a power-down
(reset) signal for both serializer and the display driver. The signal count over the flexible printed-circuit board
(FPC) could be further decreased by using the automatic standby detection feature on the SN65LVDS307
and/or SN65LVDS308 and pulling RXEN permanently high.
2 ´ 0.1 mF
2 ´ 0.1 mF
FPC
22 MHz
330 Mbps
D1+
D1–
330 Mbps
D1+
D1–
22 MHz
PCLK
R[7:0]
G[7:0]
B[7:0]
HS, VS, DE
RXEN
SN65LVDS308
TXEN
LS
SPI
RESET
SN65LVDS307
CLK+
CLK–
D0+
D0–
Video Mode Display
Driver
27
LCD With VGA
Resolution
R[7:0]
G[7:0]
B[7:0]
HS, VS, DE
GND
GND
ENABLE
27
GND
SPI
PCLK
D[23:0]
HS, VS, DE
1.8 V
CLK+
CLK–
D0+
D0–
22 MHz
Pixel CLK
1.8 V
VDDx
VDDx
Application
Processor
(e.g. OMAP)
2 ´ 0.01 mF
GND
2 ´ 0.01 mF
If no RESET signal is available,
TXEN and RXEN can also be
pulled high permanently with 1.8 V
a pull-up resistor to VDD
Serial Port Interface
(3-Wire IF)
If FPC wire count is critical, replace this
connection with a pull-up resistor at RXEN
3
B0178-02
Figure 26. Typical VGA Display Application
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APPLICATION INFORMATION (continued)
Typical Application Frequencies
The SN65LVDS307 supports pixel clock frequencies from 4 MHz to 30 MHz. Table 13 provides a few typical
display resolution examples. The blanking overhead is assumed to be 20%. Often, blanking overhead is smaller,
resulting in a lower data rate.
Table 13. Typical Application Data Rates and Serial Pair Usage
Display Screen
Resolution
Visible Pixel
Count
Blanking
Overhead
Display
Refresh Rate
[Hz]
Pixel Clock Frequency
[MHz]
90
Data Rate on
D0 With LS =
0
D0 and D1
With LS = 1
124 Mbps
240 × 320 (QVGA)
76,800
8.3
249 Mbps
240 × 320 (QVGA)
76,800
5.5
166 Mbps
–
640 × 200
128,000
9.2
276 Mbps
138 Mbps
352 × 416 (CIF+)
146,432
10.5
316 Mbps
158 Mbps
352 × 440
154,880
11.2
335 Mbps
167 Mbps
320 × 480 (HVGA)
153,600
5.5
166 Mbps
–
320 × 480 (HVGA)
153,600
11.1
332 Mbps
166 Mbps
800 × 250
200,000
14.4
432 Mbps
216 Mbps
640 × 320
204,800
14.7
442 Mbps
221 Mbps
640 × 480 (VGA)
307,200
22.1
–
332 Mbps
640 × 480 (VGA)
307,200
11.1
332 Mbps
166 Mbps
1024 × 320
327,680
23.6
–
354 Mbps
854 × 480 (WVGA)
409,920
29.5
–
443 Mbps
800 × 600 (SVGA)
480,000
17.3
–
259
1024 × 768 (XGA)
786,432
28.3
–
425
22
60
30
20%
60
30
60
30
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Calculation Example: HVGA Display
Display resolution:
480 × 320
Frame refresh rate:
58.4 Hz
Vertical visible pixels:
320 lines
Vertical front porch:
10 lines
Vertical sync:
5 lines
Vertical back porch:
3 lines
Horizontal visible pixels:
480 columns
Horizontal front porch:
20 columns
Horizontal sync:
5 columns
Horizontal back porch:
3 columns
Hsync = 5
HBP
The following calculation shows an example for a typical half-VGA display with the following parameters:
Visible Area = 480 Column
HFP = 20
Vsync = 5
VBP = 3
Visible Area
= 320 Lines
Visible Area
VFP = 10
Entire Display
M0086-01
Figure 27. HVGA Display Parameters
Calculation of the total number of pixels and blanking overhead:
Visible area pixel count:
480 × 320 = 153,600 pixels
Total frame pixel count:
(480 + 20 + 5 + 3) × (320 + 10 + 5 + 3) = 171,704 pixels
Blanking overhead:
(171,704 – 153,600) ÷ 153,600 ≈ 11.8%
The application requires following serial-link parameters:
Pixel clock frequency:
171,704 × 58.4 Hz = 10 MHz
Serial data rate:
1-channel mode: 10 MHz × 30 bits/channel = 300 Mbps
2-channel mode: 10 MHz × 15 bits/channel = 150 Mbps
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23
PACKAGE OPTION ADDENDUM
www.ti.com
18-May-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
SN65LVDS307ZQCR
ACTIVE
BGA MI
CROSTA
R JUNI
OR
ZQC
48
2500 Green (RoHS &
no Sb/Br)
SNAGCU
Level-3-260C-168 HR
SN65LVDS307ZQCT
ACTIVE
BGA MI
CROSTA
R JUNI
OR
ZQC
48
250
SNAGCU
Level-3-260C-168 HR
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
Green (RoHS &
no Sb/Br)
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
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Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-May-2007
TAPE AND REEL INFORMATION
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
Device
17-May-2007
Package Pins
Site
Reel
Diameter
(mm)
Reel
Width
(mm)
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
W
Pin1
(mm) Quadrant
SN65LVDS307ZQCR
ZQC
48
TAI
330
12
4.3
4.3
1.5
12
12
PKGORN
T1TR-MS
P
SN65LVDS307ZQCT
ZQC
48
TAI
330
12
4.3
4.3
1.5
12
12
PKGORN
T1TR-MS
P
TAPE AND REEL BOX INFORMATION
Device
Package
Pins
Site
Length (mm)
Width (mm)
Height (mm)
SN65LVDS307ZQCR
ZQC
48
TAI
342.9
336.6
20.64
SN65LVDS307ZQCT
ZQC
48
TAI
342.9
336.6
20.64
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
17-May-2007
Pack Materials-Page 3
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