SN54LV221A, SN74LV221A DUAL MONOSTABLE MULTIVIBRATORS WITH SCHMITT-TRIGGER INPUTS SCLS450 – DECEMBER 1999 D D D D D D description The ’LV221A devices are dual multivibrators designed for 2-V to 5.5-V VCC operation. Each multivibrator has a negative-transition-triggered (A) input and a positive-transition-triggered (B) input, either of which can be used as an inhibit input. These edge-triggered multivibrators feature output pulse-duration control by three methods. In the first method, the A input is low and the B input goes high. In the second method, the B input is high and the A input goes low. In the third method, the A input is low, the B input is high, and the clear (CLR) input goes high. SN54LV221A . . . J OR W PACKAGE SN74LV221A . . . D, DB, DGV, NS, OR PW PACKAGE (TOP VIEW) 1A 1B 1CLR 1Q 2Q 2Cext 2Rext/Cext GND 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC 1Rext/Cext 1Cext 1Q 2Q 2CLR 2B 2A SN54LV221A . . . FK PACKAGE (TOP VIEW) 1B 1A NC VCC 1R ext /C ext D EPIC (Enhanced-Performance Implanted CMOS) Process Schmitt-Trigger Circuitry on A, B, and CLR Inputs for Slow Input Transition Rates Edge Triggered From Active-High or Active-Low Gated Logic Inputs Overriding Clear Terminates Output Pulse Glitch-Free Power-Up Reset on Outputs Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) Package Options Include Plastic Small-Outline (D, NS), Shrink Small-Outline (DB), Thin Very Small-Outline (DGV), and Thin Shrink Small-Outline (PW) Packages, Ceramic Flat (W) Packages, Chip Carriers (FK), and DIPs (J) 1CLR 1Q NC 2Q 2Cext 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 1Cext 1Q NC 2Q 2CLR 2R ext /Cext GND NC 2A 2B D NC – No internal connection The output pulse duration is programmable by selecting external resistance and capacitance values. The external timing capacitor must be connected between Cext and Rext/Cext(positive) and an external resistor connected between Rext/Cext and VCC. To obtain variable pulse durations, connect an external variable resistor between and Rext/Cext and VCC. The output pulse duration can also be reduced by taking CLR low. Pulse triggering occurs at a particular voltage level and is not directly related to the transition time of the input pulse. The A, B, and CLR inputs have Schmitt triggers with sufficient hysteresis to handle slow input transition rates with jitter-free triggering at the outputs. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC is a trademark of Texas Instruments Incorporated. Copyright 1999, Texas Instruments Incorporated UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54LV221A, SN74LV221A DUAL MONOSTABLE MULTIVIBRATORS WITH SCHMITT-TRIGGER INPUTS SCLS450 – DECEMBER 1999 description (continued) Once triggered, the outputs are independent of further transitions of the A and B inputs and are a function of the timing components, or the output pulses can be terminated by the overriding clear. Input pulses may be of any duration relative to the output pulse. Output pulse duration can be varied by choosing the appropriate timing components. Output rise and fall times are TTL compatible and independent of pulse duration. Typical triggering and clearing sequences are illustrated in the input/output timing diagram. The variance in output pulse duration from device to device typically is less than ±0.5% for given external timing components. An example of this distribution for the ’LV221A is shown in Figure 8. Variations in output pulse duration versus supply voltage and temperature are shown in Figure 5. During power up, Q outputs will be in the high state, and Q outputs will be in the low state. The outputs will be glitch free without applying a reset pulse. Pin assignments are identical to those of the ’AHC123A and ’AHCT123A devices, so the ’LV221A can be substituted for those devices not using the retrigger feature. The SN54LV221A is characterized for operation over the full military temperature range of –55°C to 125°C. The SN74LV221A is characterized for operation from –40°C to 85°C. For additional application information on multivibrators, see the application report Designing With The SN74AHC123A and SN74AHCT123A, literature number SCLA014. FUNCTION TABLE (each multivibrator) INPUTS CLR A OUTPUTS B Q Q FUNCTION L X X L H Reset H H X L H Inhibit H X L L H H L ↑ Outputs enabled H ↑† # H Outputs enabled Inhibit L H Outputs enabled † This condition is true only if the output of the latch formed by the NAND gate has been conditioned to the logic 1 state prior to CLR going high. This latch is conditioned by taking either A high or B low while CLR is inactive (high). 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54LV221A, SN74LV221A DUAL MONOSTABLE MULTIVIBRATORS WITH SCHMITT-TRIGGER INPUTS SCLS450 – DECEMBER 1999 logic symbol† 1A 1B 1 & 2 13 1CLR 3 14 1Cext 15 1Rext/Cext 2A 2B R 1Q CX RX/CX 9 & 10 5 11 2CLR 2Cext 2Rext/Cext 1Q 4 6 7 12 R 2Q 2Q CX RX/CX † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the D, DB, DGV, J, NS, PW, and W packages. logic diagram, each multivibrator (positive logic) Rext/Cext A Cext B Q CLR R POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Q 3 SN54LV221A, SN74LV221A DUAL MONOSTABLE MULTIVIBRATORS WITH SCHMITT-TRIGGER INPUTS SCLS450 – DECEMBER 1999 input/output timing diagram A B CLR Rext/Cext Q Q tw tw tw + trr absolute maximum ratings over operating free-air temperature (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Output voltage range in high or low state, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Output voltage range in power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Package thermal impedance, θJA (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82°C/W DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. This value is limited to 7 V maximum. 3. The package thermal impedance is calculated in accordance with JESD 51. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54LV221A, SN74LV221A DUAL MONOSTABLE MULTIVIBRATORS WITH SCHMITT-TRIGGER INPUTS SCLS450 – DECEMBER 1999 recommended operating conditions (see Note 4) SN54LV221A VCC VIH Supply voltage High level input voltage High-level VCC = 2 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V MAX 2 5.5 VCC × 0.7 VCC × 0.7 VCC = 2 V VCC = 2.3 V to 2.7 V 0 Output voltage 0 Rextt External timing resistance Cext External timing capacitance ∆t/∆VCC TA Power-up ramp rate 5.5 VCC × 0.7 VCC × 0.7 Input voltage Low level output current Low-level 2 VCC × 0.7 VCC × 0.7 VI VO IOL MAX 1.5 Low level input voltage Low-level High level output current High-level MIN 1.5 VIL IOH SN74LV221A MIN VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V 0.5 0.5 VCC × 0.3 VCC × 0.3 VCC = 2 V VCC = 2.3 V to 2.7 V VCC –50 0 VCC × 0.3 5.5 0 –2 VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V VCC –50 –6 –6 –12 VCC = 2 V VCC = 2.3 V to 2.7 V 50 50 2 2 VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V 6 6 12 12 5k 5k 1k 1k No restriction –55 V µA –40 mA µA mA pF 1 125 V Ω No restriction 1 Operating free-air temperature V –2 –12 VCC = 2 V VCC ≥ 3 V V V VCC × 0.3 VCC × 0.3 VCC × 0.3 5.5 UNIT ms/V 85 °C NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN54LV221A, SN74LV221A DUAL MONOSTABLE MULTIVIBRATORS WITH SCHMITT-TRIGGER INPUTS SCLS450 – DECEMBER 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER IOH = –50 µA IOH = –2 mA VOH IOL = 50 µA IOL = 2 mA IOL = 6 mA IOL = 12 mA Rext/Cext† ICC ICC VI = VCC or GND A B, A, B and CLR VI = VCC or GND Quiescent VI = VCC or GND, Active state (per circuit) Ioff VI = VCC or GND,, Rext/Cext = 0.5 VCC SN54LV221A VCC IO = 0 VI = VCC or GND TYP SN74LV221A MAX MIN 2.3 V VCC–0.1 2 VCC–0.1 2 3V 2.48 2.48 4.5 V 3.8 TYP MAX UNIT V 3.8 2 V to 5.5 V 0.1 0.1 2.3 V 0.4 0.4 3V 0.44 0.44 4.5 V 0.55 0.55 2 V to 5.5 V ±2.5 ±2.5 0V ±1 ±1 5.5 V ±1 ±1 5.5 V 20 20 2.3 V 220 220 3V 280 280 4.5 V 650 650 5.5 V 975 975 VI or VO = 0 to 5.5 V Ci MIN 2 V to 5.5 V IOH = –6 mA IOH = –12 mA VOL II TEST CONDITIONS 0V 5 3.3 V 1.9 1.9 5V 1.9 1.9 V µA µA µA µA pF † This test is performed with the terminal in the off-state condition. timing requirements over recommended operating free-air temperature range, VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1) TEST CONDITIONS tw Pulse duration MIN TA = 25°C TYP MAX SN54LV221A MIN MAX SN74LV221A MIN CLR 6 6.5 6.5 A or B trigger 6 6.5 6.5 MAX UNIT ns timing requirements over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) TEST CONDITIONS tw Pulse duration MIN TA = 25°C TYP MAX SN54LV221A MIN MAX SN74LV221A MIN CLR 5 5 5 A or B trigger 5 5 5 MAX UNIT ns timing requirements over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) TEST CONDITIONS tw Pulse duration MIN TA = 25°C TYP MAX MIN MAX SN74LV221A MIN CLR 5 5 5 A or B trigger 5 5 5 PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 6 SN54LV221A POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MAX UNIT ns SN54LV221A, SN74LV221A DUAL MONOSTABLE MULTIVIBRATORS WITH SCHMITT-TRIGGER INPUTS SCLS450 – DECEMBER 1999 switching characteristics over recommended operating free-air temperature range, VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1) PARAMETER tpd tpd TEST CONDITIONS TA = 25°C TYP MAX FROM (INPUT) TO (OUTPUT) A or B Q or Q 14.6* 31.4* 13.2* 25* MIN CL = 15 pF SN54LV221A MIN SN74LV221A MAX MIN MAX 1* 37* 1 37 1* 29.5* 1 29.5 CLR Q or Q CLR trigger Q or Q 15.2* 33.4* 1* 39* 1 39 A or B Q or Q 16.7 36 1 42 1 42 CLR Q or Q 15 32.8 1 34.5 1 34.5 CLR trigger Q or Q 17.4 38 1 44 1 44 203 260 90 100 110 90 110 0.9 1 1.1 0.9 1.1 tw† CL = 50 pF CL = 50 pF, Cext = 28 pF, Rext = 2 kΩ CL = 50 pF, Cext = 0.01 µF, Rext = 10 kΩ CL = 50 pF, Cext = 0.1 µF, Rext = 10 kΩ Q or Q ∆tw‡ 320 ns ns 320 ns 90 110 ms 0.9 1.1 ms ±1 CL = 50 pF UNIT % * On products compliant to MIL-PRF-38535, this parameter is not production tested. † tw = Duration of pulse at Q and Q outputs ‡ ∆tw = Output pulse duration variation (Q and Q) between circuits in same package switching characteristics over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) PARAMETER tpd tpd tw† FROM (INPUT) TO (OUTPUT) A or B Q or Q CLR Q or Q TEST CONDITIONS MIN TA = 25°C TYP MAX SN54LV221A SN74LV221A MIN MAX MIN MAX 10.2* 20.6* 1* 24* 1 24 CL = 15 pF 9.3* 15.8* 1* 18.5* 1 18.5 22.4* 1* 26* 1 26 CLR trigger Q or Q 10.6* A or B Q or Q 11.8 24.1 1 27.5 1 27.5 CLR Q or Q 10.6 19.3 1 22 1 22 CLR trigger Q or Q 12.3 25.9 1 29.5 1 29.5 186 240 90 100 110 90 110 0.9 1 1.1 0.9 1.1 Q or Q CL = 50 pF CL = 50 pF, Cext = 28 pF, Rext = 2 kΩ CL = 50 pF, Cext = 0.01 µF, Rext = 10 kΩ CL = 50 pF, Cext = 0.1 µF, Rext = 10 kΩ ∆tw‡ ±1 CL = 50 pF 300 UNIT ns ns 300 ns 90 110 ms 0.9 1.1 ms % * On products compliant to MIL-PRF-38535, this parameter is not production tested. † tw = Duration of pulse at Q and Q outputs ‡ ∆tw = Output pulse duration variation (Q and Q) between circuits in same package PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 SN54LV221A, SN74LV221A DUAL MONOSTABLE MULTIVIBRATORS WITH SCHMITT-TRIGGER INPUTS SCLS450 – DECEMBER 1999 switching characteristics over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) PARAMETER tpd tpd tw† TEST CONDITIONS TA = 25°C TYP MAX FROM (INPUT) TO (OUTPUT) A or B Q or Q 7.1* CLR Q or Q 6.5* CLR trigger Q or Q 7.3* A or B Q or Q CLR Q or Q CLR trigger Q or Q MIN MAX MIN MAX 12* 1* 14* 1 14 9.4* 1* 11* 1 11 12.9* 1* 15* 1 15 8.2 14 1 16 1 16 7.4 11.4 1 13 1 13 8.6 14.9 1 17 1 17 171 200 90 100 110 90 110 0.9 1 1.1 0.9 1.1 CL = 50 pF Q or Q ∆tw‡ SN74LV221A MIN CL = 15 pF CL = 50 pF, Cext = 28 pF, Rext = 2 kΩ CL = 50 pF, Cext = 0.01 µF, Rext = 10 kΩ CL = 50 pF, Cext = 0.1 µF, Rext = 10 kΩ SN54LV221A 240 ns ns 240 ns 90 110 ms 0.9 1.1 ms ±1 CL = 50 pF UNIT % * On products compliant to MIL-PRF-38535, this parameter is not production tested. † tw = Duration of pulse at Q and Q outputs ‡ ∆tw = Output pulse duration variation (Q and Q) between circuits in same package operating characteristics, TA = 25°C PARAMETER Cpd d Power dissipation capacitance TEST CONDITIONS CL = 50 pF, pF PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 f = 10 MHz VCC 3.3 V TYP 5V 51 50 UNIT pF SN54LV221A, SN74LV221A DUAL MONOSTABLE MULTIVIBRATORS WITH SCHMITT-TRIGGER INPUTS SCLS450 – DECEMBER 1999 PARAMETER MEASUREMENT INFORMATION From Output Under Test Test Point tw CL (see Note A) VCC Inputs or Outputs 50% VCC 50% VCC 0V LOAD CIRCUIT VOLTAGE WAVEFORMS PULSE DURATION VCC Input A (see Note B) 50% VCC 0V VCC Input B (see Note B) 50% VCC 50% VCC 0V 50% VCC VOH In-Phase Output 50% VCC In-Phase Output VOL VOH VOL 50% VCC Out-of-Phase Output VOLTAGE WAVEFORMS DELAY TIMES VOH 50% VCC VOL tPLH tPHL tPHL 50% VCC tPHL tPLH 0V tPLH Out-of-Phase Output VCC Input CLR (see Note B) 50% VCC VOH 50% VCC VOL VOLTAGE WAVEFORMS DELAY TIMES NOTES: A. CL includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr C. The outputs are measured one at a time with one input transition per measurement. + 3 ns, tf + 3 ns. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 SN54LV221A, SN74LV221A DUAL MONOSTABLE MULTIVIBRATORS WITH SCHMITT-TRIGGER INPUTS SCLS450 – DECEMBER 1999 APPLICATION INFORMATION caution in use To prevent malfunctions due to noise, connect a high-frequency capacitor between VCC and GND, and keep the wiring between the external components and Cext and Rext/Cext terminals as short as possible. power-down considerations Large values of Cext can cause problems when powering down the ’LV221A because of the amount of energy stored in the capacitor. When a system containing this device is powered down, the capacitor can discharge from VCC through the protection diodes at pin 2 or pin 14. Current through the input protection diodes must be limited to 30 mA; therefore, the turn-off time of the VCC power supply must not be faster than t = VCC × Cext/30 mA. For example, if VCC = 5 V and Cext = 15 pF, the VCC supply must turn off no faster than t = (5 V) × (15 pF)/30 mA = 2.5 ms. Usually, this is not a problem because power supplies are heavily filtered and cannot discharge at this rate. When a more rapid decrease of VCC to zero occurs, the ’LV221A can sustain damage. To avoid this possibility, use external clamping diodes. output pulse duration The output pulse duration, tw, is determined primarily by the values of the external capacitance (CT) and timing resistance (RT). The timing components are connected as shown in Figure 2. VCC RT CT To Rext/Cext Terminal To Cext Terminal Figure 2. Timing-Component Connections The pulse duration is given by: tw +K RT CT (1) if CT is ≥ 1000 pF, K = 1.0 or if CT is < 1000 pF, K can be determined from Figure 7 where: tw RT CT K = pulse duration in ns = external timing resistance in kΩ = external capacitance in pF = multiplier factor Equation 1 and Figure 3 or 4 can be used to determine values for pulse duration, external resistance, and external capacitance. 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54LV221A, SN74LV221A DUAL MONOSTABLE MULTIVIBRATORS WITH SCHMITT-TRIGGER INPUTS SCLS450 – DECEMBER 1999 APPLICATION INFORMATION† OUTPUT PULSE DURATION vs EXTERNAL TIMING CAPACITANCE OUTPUT PULSE DURATION vs EXTERNAL TIMING CAPACITANCE 1.00E+07 1.00E+07 VCC = 4.5 V TA = 25°C 1.00E+06 t w – Output Pulse Duration – ns t w – Output Pulse Duration – ns VCC = 3 V TA = 25°C RT = 1 MΩ 1.00E+05 RT = 100 kΩ 1.00E+04 RT = 10 kΩ 1.00E+03 1.00E+06 RT = 1 MΩ 1.00E+05 RT = 100 kΩ 1.00E+04 RT = 10 kΩ 1.00E+03 RT = 1 kΩ 1.00E+02 101 RT = 1 kΩ 102 103 104 105 1.00E+02 101 102 103 104 105 CT – External Timing Capacitance – pF CT – External Timing Capacitance – pF Figure 3 Figure 4 VARIATION IN OUTPUT PULSE DURATION vs TEMPERATURE 14% Variation in Output Pulse Duration 12% 10% 8% tw = 866 ns at: VCC = 5 V RT = 10 kΩ CT = 50 pF TA = 25°C VCC = 2.5 V VCC = 3 V VCC = 3.5 V VCC = 4 V VCC = 5 V 6% VCC = 6 V VCC = 7 V 4% 2% 0% –2% –4% –6% –60 –40 –20 0 20 40 60 80 100 120 140 160 180 Temperature – °C Figure 5 † Operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 SN54LV221A, SN74LV221A DUAL MONOSTABLE MULTIVIBRATORS WITH SCHMITT-TRIGGER INPUTS SCLS450 – DECEMBER 1999 APPLICATION INFORMATION† OUTPUT PULSE DURATION CONSTANT vs SUPPLY VOLTAGE EXTERNAL CAPACITANCE vs MULTIPLIER FACTOR 1.20 For Capacitor Values of 0.001 µF or Greater, K = 1.0 (K is Independent of R) Output Pulse Duration Constant – K C T – External Capacitor Value – µ F 0.001 0.0001 0.00001 TA = 25°C VCC = 5 V 1.00 1.50 2.00 2.50 3.00 3.50 4.00 RT = 10 kΩ TA = 25°C tw = K × C T × R T 1.15 1.10 CT = 1000 pF 1.05 CT = 0.01 µF 1.00 CT = 0.1 µF 0.95 0.90 1.5 4.50 2 2.5 3 3.5 4 4.5 5 5.5 6 VCC – Supply Voltage – V Multiplier Factor – K Figure 6 Figure 7 Relative Frequency of Occurrence DISTRIBUTION OF UNITS vs OUTPUT PULSE DURATION VCC = 5 V TA = 25°C CT = 50 pF RT = 10 kΩ Mean = 856 ns Median = 856 ns Std. Dev. = 3.5 ns –3 Std. Dev. 99% of Data Units +3 Std. Dev. Median tw – Output Pulse Duration Figure 8 † Operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK. In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof. Copyright 1999, Texas Instruments Incorporated