PRELIMINARY ICS8543 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-4 LVDS FANOUT BUFFER GENERAL DESCRIPTION FEATURES The ICS8543 is a low skew, high performance 1-to-4 clock fanout buffer and a member of HiPerClockS™ the HiPerClockS™ family of High Performance Clock Solutions from ICS. Utilizing Low Voltage Differential Signaling (LVDS) the ICS8543 provides a low power, low noise, solution for distributing clock signals over controlled impedances of 100Ω. The ICS8543 accepts any differential input level and translates it to 3.3V LVDS output levels. • 4 LVDS outputs Guaranteed output and part-to-part skew characteristics make the ICS8543 ideal for those applications demanding well defined performance and repeatability. • 0°C to 70°C ambient operating temperature BLOCK DIAGRAM PIN ASSIGNMENT ,&6 • Designed to meet or exceed the requirements of ANSI TIA/EIA-644 • Selectable differential HSTL or LVPECL clock inputs • LVCMOS / LVTTL control inputs • 3.3V operating supply • 20 lead TSSOP VEE CLK_EN CLK_SEL HCLK nHCLK PCLK nPCLK OE VEE VDD nD CLK_EN Q LE HCLK nHCLK PCLK nPCLK CLK_SEL 0 1 Q0 nQ0 Q1 nQ1 Q2 nQ2 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 Q0 nQ0 VDD Q1 nQ1 Q2 nQ2 VEE Q3 nQ3 ICS8543 Q3 nQ3 20-Lead TSSOP G Package Top View OE The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice. ICS8543BG www.icst.com/products/hiperclocks.html REV. C MAY 21, 2001 1 PRELIMINARY ICS8543 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-4 LVDS FANOUT BUFFER TABLE 1. PIN DESCRIPTIONS Number Name 1, 9, 13 VEE Power Type 2 CLK_EN Input Pullup 3 CLK_SEL Input Pulldown 4 HCLK Input Pulldown 5 nHCLK Input Pullup 6 PCLK Input Pulldown 7 nPCLK Input Pullup 8 OE Input Pullup Description Power supply ground. Connect to ground. Synchronous clock enable. When HIGH clock outputs follows clock input. When LOW, Q outputs are force low, nQ outputs are force high. LVCMOS / LVTTL interface levels. Clock select input. When HIGH selects differential PECL inputs. When LOW selects differential HSTL inputs. LVCMOS / LVTTL interface levels. Non-inver ting differential HSTL clock input. Inver ting differential HSTL clock input. Non-inver ting differential PECL clock input. 10, 18 VDD Power Inver ting differential PECL clock input. Output enable. Controls enabling and disabling of outputs Q0, nQ0 thru Q3, nQ3 Power supply pin. Connect to 3.3V. 11, 12 nQ3, Q3 Output Differential clock outputs. LVDS interface levels. 14, 15 nQ2, Q2 Output Differential clock outputs. LVDS interface levels. 16, 17 nQ1, Q1 Output Differential clock outputs. LVDS interface levels. 19, 20 nQ0, Q0 Output Differential clock outputs. LVDS interface levels. TABLE 2. PIN CHARACTERISTICS Symbol Maximum Units HCLK, nHCLK 4 pF 4 pF 4 pF RPULLUP PCLK, nPLCK CLK_EN, CLK_SEL Input Pullup Resistor 51 KΩ RPULLDOWN Input Pulldown Resistor 51 KΩ CIN ICS8543BG Parameter Test Conditions Minimum Typical Input Capacitance www.icst.com/products/hiperclocks.html 2 REV. C MAY 21, 2001 PRELIMINARY ICS8543 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-4 LVDS FANOUT BUFFER TABLE 3A. CONTROL INPUTS FUNCTION TABLE Inputs Outputs OE CLK_EN CLK_SEL Q1 thru Q3 nQ1 thru nQ3 0 X X Hi Z Hi Z 1 0 0 Low High 1 0 1 Low High 1 1 0 ACTIVE ACTIVE 1 1 1 ACTIVE ACTIVE In the active mode the state of the output is a function of the HCLK, nHCLK and PCLK, nPCLK inputs as described in Table 3B. TABLE 3B. CLOCK INPUTS FUNCTION TABLE Inputs Outputs Input to Output Mode Polarity HIGH Differential to Differential Non Inver ting HIGH LOW Differential to Differential Non Inver ting Biased; NOTE 1 LOW HIGH Single Ended to Differential Non Inver ting 1 Biased; NOTE 1 HIGH LOW Single Ended to Differential Non Inver ting Biased; NOTE 1 0 HIGH LOW Single Ended to Differential Inver ting Biased; NOTE 1 1 LOW HIGH Single Ended to Differential Inver ting HCLK, PCLK nHCLK, nPCLK Q0 thru Q3 nQ0 thru nQ3 0 1 LOW 1 0 0 NOTE 1: Single ended use requires that one of the differential inputs be biased. The voltage at the biased input sets the switch point for the single ended input. For LVCMOS and LVTTL levels the recommended input bias network is a resistor to VCC, a resistor of equal value to ground and a 0.1µF capacitor from the input to ground. The resulting switch point is approximately VCC/2 ± 300mV. ICS8543BG www.icst.com/products/hiperclocks.html 3 REV. C MAY 21, 2001 PRELIMINARY ICS8543 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-4 LVDS FANOUT BUFFER ABSOLUTE MAXIMUM RATINGS Supply Voltage Inputs Outputs Ambient Operating Temperature Storage Temperature 4.6V -0.5V to VDD + 0.5V -0.5V to VDD + 0.5V 0°C to 70°C -65°C to 150°C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of product at these condition or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V±5%, TA=0°C TO 70°C Symbol Parameter VDD Power Supply Voltage Test Conditions IEE Power Supply Current Minimum Typical Maximum Units 3.135 3.3 3.465 V 50 mA Maximum Units 150 µA TABLE 4B. LVPECL DC CHARACTERISTICS, VDD = 3.3V±5%, TA=0°C TO 70°C Symbol Parameter IIH Input High Current Test Conditions Minimum Typical PCLK nPCLK 5 µA PCLK -5 µA nPCLK -150 µA IIL Input Low Current VPP Peak-to-Peak Input Voltage VCMR Common Mode Input Voltage; NOTE 1 0.15 1.3 V 1.5 3.3 V Maximum Units 150 µA NOTE 1: Common mode voltage for LVPECL is defined as the minimum VIH. TABLE 4C. LVHSTL DC CHARACTERISTICS, VDD = 3.3V±5%, TA=0°C TO 70°C Symbol IIH Parameter Input High Current Test Conditions HCLK Minimum 3.135V ≤ VDDI ≤ 3.465V Typical nHCLK 3.135V ≤ VDDI ≤ 3.465V HCLK 3.135V ≤ VDDI ≤ 3.465V -5 µA nHCLK 3.135V ≤ VDDI ≤ 3.465V -150 µA IIL Input Low Current VPP Peak-to-Peak Input Voltage 5 0.15 1.3 µA V VCMR Common Mode Input Voltage; NOTE 1 0.5 VDD - 0.85 V NOTE 1: Common mode voltage for HSTL is defined as the crossover voltage. VCMR is compatible with DCM, LVDS and SSTL inputs. ICS8543BG www.icst.com/products/hiperclocks.html 4 REV. C MAY 21, 2001 PRELIMINARY ICS8543 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-4 LVDS FANOUT BUFFER TABLE 4D. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = 3.3V±5%, TA=0°C TO 70°C Symbol Parameter VIH Input High Voltage CLK_EN, CLK_SEL, OE Test Conditions VIL Input Low Voltage CLK_EN, CLK_SEL, OE IIH Input High Current IIL Input Low Current Minimum Typical Maximum 2 V 0.8 V 5 µA 150 µA CLK_EN, OE CLK_SEL CLK_EN, OE CLK_SEL Units -150 µA -5 µA TABLE 4E. LVDS DC CHARACTERISTICS, VDD = 3.3V±5%, TA=0°C TO 70°C Symbol Parameter VOD Differential Output Voltage ∆ VOD VOD Magnitude Change VOS Offset Voltage ∆ VOS VOS Magnitude Change Test Conditions Minimum Typical Maximum Units 250 350 450 mV 4 35 mV 1.25 1.375 V 5 25 mV 1.125 IOZ High Impedance Leakage Current -10 ±1 +10 µA IOFF Power Off Leakage -20 ±1 +20 µA IOSD Differential Output Shor t Circuit Current 3.0 mA IOS Output Shor t Circuit Current 3.0 mA TABLE 5. AC CHARACTERISTICS, VDD = 3.3V±5%, TA=0°C TO 70°C Symbol Parameter fMAX Maximum Input Frequency Test Conditions 0 ≤ f ≤ 650MHz tpLH Propagation Delay, Low-to-High tsk(o) Output Skew; NOTE 2 tsk(pp) Par t-to-Par t Skew; NOTE 3 tR Output Rise Time RL = 100Ω tF Output Fall Time RL = 100Ω tPW Output Pulse Width tEN Output Enable Time Minimum Typical 1.8 200 400 200 400 Maximum Units 650 MHz 2.4 ns 50 ps 300 ps 600 ps 600 ps tCYCLE/2 + TBD ns TBD ns tDIS Output Disable Time TBD NOTE 1: All parameters measured at fMAX unless noted otherwise. NOTE 2: Defined as skew across outputs at the same supply voltages and with equal load conditions. Measured from the 50% point of the input to the differential output crossing point. NOTE 3: Defined as skew at different outputs on different devices operating at the same supply voltages and with equal load conditions. Measured from 50% of like inputs to the differential output crossing point. ns ICS8543BG tCYCLE/2 - TBD www.icst.com/products/hiperclocks.html 5 REV. C MAY 21, 2001 PRELIMINARY ICS8543 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-4 LVDS FANOUT BUFFER PACKAGE OUTLINE - G SUFFIX c N 20 11 L E E1 10 1 α D A2 A -Ce b A1 SEATING PLANE aaa C TABLE 6. PACKAGE DIMENSIONS Millimeters SYMBOL MIN Inches MAX N MIN MAX 20 A -- 1.20 -- 0.047 A1 0.05 0.15 0.002 0.006 A2 0.80 1.05 0.032 0.041 b 0.19 0.30 0.007 0.012 c 0.09 0.20 0.0035 0.008 D 6.40 6.60 0.252 0.260 E E1 6.40 BASIC 4.30 e 0.252 BASIC 4.50 0.169 0.65 BASIC L 0.45 α aaa 0.177 0.0256 BASIC 0.75 0.018 0.030 0° 8° 0° 8° -- 0.10 -- 0.004 Reference Document: JEDEC Publication 95, MO-153 ICS8543BG www.icst.com/products/hiperclocks.html 6 REV. C MAY 21, 2001 PRELIMINARY ICS8543 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-4 LVDS FANOUT BUFFER TABLE 7. ORDERING INFORMATION Part/Order Number Marking Package Count Temperature ICS8543BG ICS8543BG 20 lead TSSOP 72 per tube 0°C to 70°C ICS8543BGT ICS8543BG 20 lead TSSOP on Tape and Reel 2500 0°C to 70°C While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. ICS8543BG www.icst.com/products/hiperclocks.html 7 REV. C MAY 21, 2001