ICS8547 Integrated Circuit Systems, Inc. HEX, LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVDS CLOCK BUFFERS GENERAL DESCRIPTION FEATURES The ICS8547 is a Hex low skew, high performance 1-to-2 Differential-to-LVDS Clock Buffer HiPerClockS™ and a member of the HiPerClockS™ family of High Performance Clock Solutions from ICS. Utilizing Low Voltage Differential Signaling (LVDS) the ICS8547 provides a low power, low noise, point-to-point solution for distributing clock signals over controlled impedances of 100Ω. The ICS8547 has six selectable clock inputs. The CLKx, nCLKx pairs can accept any differential input levels and translates them to 3.3V LVDS output levels. • 12 LVDS outputs ,&6 • Selectable CLKx, nCLKx inputs • CLKx, nCLKx pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL • Maximum output frequency: 700MHz • Translates any differential input signal (LVPECL, LVHSTL, SSTL, DCM) to LVDS levels without external bias networks • Translates any single-ended input signal to LVDS with resistor bias on nCLKx input Guaranteed output and part-to-part skew specifications make the ICS8547 ideal for those applications demanding well defined performance and repeatability. • Output skew: 250ps (maximum) • Bank skew: 15ps (maximum) • Part-to-part skew: 500ps (maximum) • Propagation delay: 1.8ns (maximum) • 3.3V operating supply • 0°C to 85°C ambient operating temperature • Industrial temperature information available upon request BLOCK DIAGRAM CLK1 nCLK1 CLK2 nCLK2 CLK3 nCLK3 CLK5 nCLK5 ICS8547AY Q0B nQ0B Q4A nQ4A nQ4B Q4B nCLK4 CLK4 CLK5 nCLK5 Q5B nQ5B nQ5A Q5A Q1A nQ1A Q1B nQ1B Q2A nQ2A Q2B nQ2B Q3A nQ3A Q3B nQ3B 48 47 46 45 44 43 42 41 40 39 38 37 1 36 2 35 3 34 4 33 5 32 6 31 7 30 8 29 9 28 10 27 11 26 12 25 13 14 15 16 17 18 19 20 21 22 23 24 ICS8547 Q2A nQ2A nQ2B Q2B nCLK2 CLK2 CLK1 nCLK1 Q1B nQ1B nQ1A Q1A VDDO GND VDD Q0B nQ0B nQ0A Q0A nCLK0 CLK0 VDD GND VDDO CLK4 nCLK4 Q0A nQ0A VDDO GND VDD Q3B nQ3B nQ3A Q3A nCLK3 CLK3 VDD GND VDDO CLK0 nCLK0 PIN ASSIGNMENT Q4A nQ4A Q4B nQ4B 48-Lead LQFP 7mm x 7mm x 1.4mm package body Y Package Top View Q5A nQ5A Q5B nQ5B www.icst.com/products/hiperclocks.html 1 REV. A FEBRUARY 4, 2003 ICS8547 Integrated Circuit Systems, Inc. HEX, LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVDS CLOCK BUFFERS TABLE 1. PIN DESCRIPTIONS Number Name Type 1, 2 Q4A, nQ4A Output 3, 4 nQ4B, Q4B Output 5 nCLK4 Input Description Differential output pair. LVDS interface levels. Differential output pair. LVDS interface levels. Pullup Inver ting differential clock input. 6 CLK4 Input Pulldown Non-inver ting differential clock input. 7 CLK5 Input Pulldown Non-inver ting differential clock input. 8 nCLK5 Input Pullup 9, 10 Q5B, nQ5B Output Differential output pair. LVDS interface levels. 11, 12 nQ5A, Q5A Output Differential output pair. LVDS interface levels. Inver ting differential clock input. 13, 24, 37, 48 VDDO Power Output supply pins. 14, 23, 38, 47 GND Power Power supply ground. 15, 22, 39, 46 VDD Power Core supply pins. 16 CLK0 Input Pulldown 17 nCLK0 Input Pullup Non-inver ting differential clock input. 18, 19 Q0A, nQ0A Output Differential output pair. LVDS interface levels. 20, 21 nQ0B, Q0B Output Differential output pair. LVDS interface levels. 25, 26 Q1A, nQ1A Output Differential output pair. LVDS interface levels. 27, 28 nQ1B, Q1B Output 29 nCLK1 Input Inver ting differential clock input. Differential output pair. LVDS interface levels. Pullup Inver ting differential clock input. 30 CLK1 Input Pulldown Non-inver ting differential clock input. 31 CLK2 Input Pulldown Non-inver ting differential clock input. 32 nCLK2 Input Pullup 33, 34 Q2B, nQ2B Output Differential output pair. LVDS interface levels. 35, 36 nQ2A, Q2A Output Differential output pair. LVDS interface levels. 40, 41 Q3B, nQ3B Output Differential output pair. LVDS interface levels. 42, 43 nQ3A, Q3A Output 44 nCLK3 Input Pullup 45 CLK3 Input Pulldown Inver ting differential clock input. Differential output pair. LVDS interface levels. Inver ting differential clock input. Non-inver ting differential clock input. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. ICS8547AY www.icst.com/products/hiperclocks.html 2 REV. A FEBRUARY 4, 2003 ICS8547 Integrated Circuit Systems, Inc. HEX, LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVDS CLOCK BUFFERS TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN Input Capacitance Test Conditions Minimum Typical Maximum Units 4 pF RPULLUP Input Pullup Resistor 51 KΩ RPULLDOWN Input Pulldown Resistor 51 KΩ CPD Capacitance Power Dissipation 1 pF TABLE 3. CLOCK INPUT FUNCTION TABLE Inputs Outputs nQ0A:nQ5A, nQ5B:nQ5B HIGH Input to Output Mode Polarity 0 1 Q0A:Q5A, Q0B:Q5B LOW Differential to Differential Non Inver ting 1 0 HIGH LOW Differential to Differential Non Inver ting 0 Biased; NOTE 1 LOW HIGH Single Ended to Differential Non Inver ting 1 Biased; NOTE 1 HIGH LOW Single Ended to Differential Non Inver ting Biased; NOTE 1 0 HIGH LOW Single Ended to Differential Inver ting Biased; NOTE 1 1 LOW HIGH Single Ended to Differential Inver ting CLKx nCLKx NOTE 1: Please refer to the Application Information section, "Wiring the Differential Input to Accept Single Ended Levels". ICS8547AY www.icst.com/products/hiperclocks.html 3 REV. A FEBRUARY 4, 2003 ICS8547 Integrated Circuit Systems, Inc. HEX, LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVDS CLOCK BUFFERS ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5 V Outputs, VO -0.5V to VDDO + 0.5V Package Thermal Impedance, θJA 47.9°C/W (0 lfpm) Storage Temperature, TSTG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 3.3V±5%, TA = 0°C TO 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VDD Core Supply Voltage 3.135 3.3 3.465 V VDDO Output Supply Voltage 3.135 3.3 3.465 V IDD Power Supply Current 22 mA IDDO Output Supply Current 18 mA TABLE 4B. DIFFERENTIAL DC CHARACTERISTICS, VDD = VDDO = 3.3V±5%, TA = 0°C TO 85°C Symbol IIH Parameter Input High Current Test Conditions CLKx Minimum Typical VIN = VDD = 3.465V nCLKx VIN = VDD = 3.465V CLKx VDD = 3.465V, VIN = 0V -5 nCLKx VDD = 3.465V, VIN = 0V -150 Maximum Units 150 µA 5 µA µA IIL Input Low Current VPP Peak-to-Peak Voltage 0.15 1.3 V VCMR Common Mode Voltage Range 0.5 VDD - 0.85 V µA TABLE 4C. LVDS DC CHARACTERISTICS, VDD = VDDO = 3.3V±5%, TA = 0°C TO 85°C Symbol Parameter VOD Differential Output Voltage ∆ VOD VOD Magnitude Change VOS Offset Voltage ∆ VOS VOS Magnitude Change Test Conditions Minimum Typical Maximum Units 175 275 375 mV 50 mV 1.0 1.3 1.6 V 50 mV IOFF Power Off Leakage +1 µA IOSD Differential Output Shor t Circuit Current -5.5 mA IOS/IOSB Output Shor t Circuit Current -12 mA ICS8547AY -1 www.icst.com/products/hiperclocks.html 4 REV. A FEBRUARY 4, 2003 ICS8547 Integrated Circuit Systems, Inc. HEX, LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVDS CLOCK BUFFERS TABLE 5. AC CHARACTERISTICS, VDD = VDDO = 3.3V±5%, TA = 0°C TO 85°C Symbol Parameter fMAX Output Frequency tPD Propagation Delay; NOTE 1 tsk(o) Output Skew; NOTE 2, 5 tsk(b) Bank Skew; NOTE 3, 5 tsk(pp) Par t-to-Par t Skew; NOTE 4, 5 tR / tF Output Rise/Fall Time odc Output Duty Cycle Test Conditions Minimum ƒ≤ 500MHz 1.2 20% to 80% 250 ƒ≤ 300MHz 45 Typical 1.5 50 300MHz < ƒ ≤ 500MHz 40 All parameters measured at 500MHz unless noted otherwise. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured from at the output differential cross points. NOTE 3: Defined as skew within a bank of outputs at the same voltages and with equal load conditions. NOTE 4: Defined as between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 5: This parameter is defined in accordance with JEDEC Standard 65. ICS8547AY www.icst.com/products/hiperclocks.html 5 Maximum Units 700 MHz 1.8 ns 250 ps 15 ps 500 ps 550 ps 55 % 60 % REV. A FEBRUARY 4, 2003 ICS8547 Integrated Circuit Systems, Inc. HEX, LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVDS CLOCK BUFFERS PARAMETER MEASUREMENT INFORMATION VDD 3.3V nCLKx Qx 3.3V±5% POWER SUPPLY + Float GND - SCOPE V V Cross Points PP LVDS CMR CLKx nQx GND 3.3V OUTPUT LOAD AC TEST CIRCUIT DIFFERENTIAL INPUT LEVEL nQx nQx PART 1 Qx Qx nQy nQy PART 2 Qy Qy tsk(pp) tsk(o) PART-TO-PART SKEW OUTPUT SKEW QxA, nQxA 80% QxA, nQxA VO D 20% QxB, nQxB QxB, nQxB 80% 20% Clock Outputs t R t F tsk(b) BANK SKEW OUTPUT RISE/FALL TIME nQxA, nQxB nCLKx QxA, QxB Pulse Width t CLKx PERIOD nQxA, nQxB odc = t PW QxA, QxB t PERIOD tPD odc & tPERIOD ICS8547AY PROPAGATION DELAY www.icst.com/products/hiperclocks.html 6 REV. A FEBRUARY 4, 2003 ICS8547 Integrated Circuit Systems, Inc. HEX, LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVDS CLOCK BUFFERS VDD VDD out ➤ out ➤ 100 DC Input VOD/∆ VOD out LVDS ➤ ➤ LVDS ➤ DC Input out VOS/∆ VOS ➤ VOD / DVOD SETUP VOS / DVOS SETUP VDD VDD ➤ out DC Input out IOS LVDS DC Input ➤ LVDS IOSD ➤ IOSB out out IOS SETUP IOSD SETUP LVDS ➤ VDD IOFF IOFF SETUP ICS8547AY www.icst.com/products/hiperclocks.html 7 REV. A FEBRUARY 4, 2003 ICS8547 Integrated Circuit Systems, Inc. HEX, LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVDS CLOCK BUFFERS APPLICATION INFORMATION WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. VDD R1 1K CLK_IN + V_REF C1 0.1uF R2 1K FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT ICS8547AY www.icst.com/products/hiperclocks.html 8 REV. A FEBRUARY 4, 2003 ICS8547 Integrated Circuit Systems, Inc. HEX, LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVDS CLOCK BUFFERS DIFFERENTIAL CLOCK INPUT INTERFACE examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 2, the input termination applies for ICS HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation. The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 2 to 5 show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are 3.3V 3.3V 3.3V 1.8V Zo = 50 Ohm CLK Zo = 50 Ohm CLK Zo = 50 Ohm nCLK Zo = 50 Ohm nCLK LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 HiPerClockS Input LVPECL HiPerClockS Input R1 50 R2 50 R2 50 R3 50 FIGURE 2. HIPERCLOCKS CLK/NCLK INPUT DRIVEN ICS HIPERCLOCKS LVHSTL DRIVER FIGURE 3. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER BY 3.3V 3.3V 3.3V 3.3V R3 125 BY 3.3V R4 125 3.3V Zo = 50 Ohm LVPECL CLK Zo = 50 Ohm C1 Zo = 50 Ohm C2 R3 125 R4 125 CLK Zo = 50 Ohm nCLK LVPECL R1 84 HiPerClockS Input nCLK R2 84 R5 100 - 200 R6 100 - 200 R1 84 HiPerClockS Input R2 84 R5,R6 locate near the driver pin. FIGURE 4. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER ICS8547AY FIGURE 5. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER WITH AC COUPLE BY www.icst.com/products/hiperclocks.html 9 BY REV. A FEBRUARY 4, 2003 ICS8547 Integrated Circuit Systems, Inc. HEX, LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVDS CLOCK BUFFERS LVDS DRIVER TERMINATION Figure 6 shows typical termination for LVDS driver in characteristic impedance of 100Ω differential (50Ω single) transmission line environment. For buffer with multiple LDVS driver, it is recommended to terminate the unused outputs. 3.3V 3.3V Zo = 50 LVDS_Driver + R1 100 - Zo = 50 FIGURE 6. TYPICAL LVDS DRIVER TERMINATION RELIABILITY INFORMATION TABLE 6. θJAVS. AIR FLOW TABLE qJA by Velocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 67.8°C/W 47.9°C/W 55.9°C/W 42.1°C/W 50.1°C/W 39.4°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS8547 is: 1117 ICS8547AY www.icst.com/products/hiperclocks.html 10 REV. A FEBRUARY 4, 2003 ICS8547 Integrated Circuit Systems, Inc. HEX, LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVDS CLOCK BUFFERS PACKAGE OUTLINE - Y SUFFIX TABLE 6. PACKAGE DIMENSIONS JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS SYMBOL BBC MINIMUM NOMINAL MAXIMUM 48 N A -- -- 1.60 A1 0.05 -- 0.15 A2 1.35 1.40 1.45 b 0.17 0.22 0.27 c 0.09 -- 0.20 D 9.00 BASIC D1 7.00 BASIC D2 5.50 Ref. E 9.00 BASIC E1 7.00 BASIC E2 5.50 Ref. e 0.50 BASIC L 0.45 0.60 0.75 q 0° -- 7° ccc -- -- 0.08 Reference Document: JEDEC Publication 95, MS-026 ICS8547AY www.icst.com/products/hiperclocks.html 11 REV. A FEBRUARY 4, 2003 ICS8547 Integrated Circuit Systems, Inc. HEX, LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVDS CLOCK BUFFERS TABLE 7. ORDERING INFORMATION Part/Order Number Marking Package Count Temperature ICS8547AY ICS8547AY 48 Lead LQFP 250 per tray 0°C to 85°C ICS8547AYT ICS8547AY 48 Lead LQFP on Tape and Reel 1000 0°C to 85°C While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. ICS8547AY www.icst.com/products/hiperclocks.html 12 REV. A FEBRUARY 4, 2003