PRELIMINARY ICS854S202I-01 12:2, DIFFERENTIAL-TO-LVDS MULTIPLEXER GENERAL DESCRIPTION FEATURES The ICS854S202I-01 is a 12:2 Differential-toICS LVDS Clock Multiplexer which can operate up to HiPerClockS™ 700MHz and is a member of the HiPerClockS™ family of High Performance Clock Solutions from IDT. The ICS854S202I-01 has 12 selectable differential clock inputs, any of which can be independently routed to either of the two LVDS outputs. The CLKx, nCLKx input pairs can accept LVPECL, LVDS, CML or SSTL levels. The fully differential architecture and low propagation delay make it ideal for use in clock distribution circuits. • Two differential 2.5V LVDS clock outputs • Twelve selectable differential clock inputs • CLKx, nCLKx pairs can accept the following differential input levels: LVPECL, LVDS, HSTL, SSTL, HCSL • Maximum output frequency: >3GHz • Propagation delay: 650ps (typical) • Input skew: TBD • Output skew: 25ps (typical) • Part-to-part skew: TBD • Additive phase jitter, RMS (12kHz – 20MHz): 0.16ps (typical) • Full 2.5V operating supply mode BLOCK DIAGRAM SELA_[3:0] • • Available in both standard (RoHS 5) and lead-free (RoHS 6) packages 4 Pulldown -40°C to 85°C ambient operating temperature CLK0 nCLK0 CLK1 nCLK1 CLK2 nCLK2 QA nQA OEA PIN ASSIGNMENT CLK2 nCLK2 SELA_0 SELA_1 VDD QA nQA GND SELA_2 SELA_3 CLK3 nCLK3 CLK6 nCLK6 CLK7 nCLK7 CLK8 nCLK8 QB nQB OEB CLK9 nCLK9 CLK11 nCLK11 SELB_[3:0] 48 47 46 45 44 43 42 41 40 39 38 37 1 36 2 35 3 34 4 33 5 32 48-Pin LQFP 6 31 7mm x 7mm x 1.4mm 7 30 package body 8 29 Y Package 9 28 Top View 10 27 11 26 12 25 13 14 15 16 17 18 19 20 21 22 23 24 ICS854S202I-01 nCLK4 CLK4 GND nCLK5 CLK5 VDD OEA CLK6 nCLK6 GND CLK7 CLK10 nCLK10 Pulldown nCLK10 CLK5 nCLK5 CLK10 GND nCLK11 CLK11 OEB VDD CLK0 nCLK0 GND CLK1 nCLK1 CLK4 nCLK4 CLK9 nCLK9 SELB_0 SELB_1 VDD QB nQB GND SELB_2 SELB_3 CLK8 nCLK8 nCLK7 CLK3 nCLK3 4 The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization and/or qualification. Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice. IDT ™ / ICS™ LVDS MULTIPLEXER 1 ICS854S202AYI-01 REV. A JANUARY 8, 2007 ICS854S202I-01 12:2, DIFFERENTIAL-LVDS MULTIPLEXER PRELIMINARY TABLE 1. PIN DESCRIPTIONS (CONTINUED ON NEXT PAGE) Number Name 1 CLK2 Input Type 2 nCLK2 Input 3, 4, 9, 10 5, 32, 43 SELA_0, SELA_1, SELA_2, SELA_3 VDD Power Positive supply pins. 6, 7 QA, nQA Output Clock outputs. LVDS interface levels. 8, 15, 22, 29, 39, 46 GND Power 11 CLK3 Input 12 nCLK3 Input 13 nCLK4 Input 14 CLK4 Input 16 nCLK5 Input 17 CLK5 Input 18, 43 VDD Power 19 OEA Input Pullup 20 CLK6 Input 21 nCLK6 Input 23 CLK7 Input 24 nCLK7 Input 25 nCLK8 Input 26 27, 28, 33, 34 30, 31 CLK8 SELB_3, SELB_2, SELB_1, SELB_0 nQB, QB Input Pullup Pullup/ Pulldown Pullup Pullup/ Pulldown Pullup/ Pulldown Pullup Output 35 nCLK9 Input 36 CLK9 Input 37 nCLK10 Input 38 CLK10 Input 40 nCLK11 Input 41 CLK11 Input Input Input Description Pullup Non-inver ting differential clock input. Pullup/ Inver ting differential clock input. VDD/2 default when left floating. Pulldown Clock select pins for Bank A outputs. See Control Input Pulldown Function Table. LVCMOS/LVTTL interface levels. See Table 3B. Power supply ground. Pullup Pullup/ Pulldown Pullup/ Pulldown Pullup Pullup/ Pulldown Pullup Non-inver ting differential clock input. Inver ting differential clock input. VDD/2 default when left floating. Inver ting differential clock input. VDD/2 default when left floating. Non-inver ting differential clock input. Inver ting differential clock input. VDD/2 default when left floating. Non-inver ting differential clock input. Positive supply pins. Output enable pin. Controls enabling and disabling of QA/nQA outputs. LVCMOS/LVTTL internface levels. Non-inver ting differential clock input. Inver ting differential clock input. VDD/2 default when left floating. Non-inver ting differential clock input. Inver ting differential clock input. VDD/2 default when left floating. Inver ting differential clock input. VDD/2 default when left floating. Non-inver ting differential clock input. Clock select pins for Bank B outputs. See Control Input Pulldown Function Table. LVCMOS/LVTTL interface levels. See Table 3C. Clock outputs. LVDS interface levels. Pullup/ Pulldown Pullup Pullup/ Pulldown Pullup Pullup/ Pulldown Pullup Inver ting differential clock input. VDD/2 default when left floating. Non-inver ting differential clock input. Inver ting differential clock input. VDD/2 default when left floating. Non-inver ting differential clock input. Inver ting differential clock input. VDD/2 default when left floating. Non-inver ting differential clock input. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. IDT ™ / ICS™ LVDS MULTIPLEXER 2 ICS854S202AYI-01 REV. A JANUARY 8, 2007 ICS854S202I-01 12:2, DIFFERENTIAL-LVDS MULTIPLEXER PRELIMINARY TABLE 1. PIN DESCRIPTIONS (CONTINUED) Number Name Type 42 OEB Input 44 CLK0 Input Pullup Description Output enable pin. Controls enabling and disabling of QB/nQB outputs. LVCMOS/LVTTL internface levels. See Table 3A. Non-inver ting differential clock input. Pullup Pullup/ 45 nCLK0 Input Inver ting differential clock input. VDD/2 default when left floating. Pulldown 47 CLK1 Input Pullup Non-inver ting differential clock input. Pullup/ 48 nCLK1 Input Inver ting differential clock input. VDD/2 default when left floating. Pulldown NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN Input Capacitance Test Conditions Minimum Typical 4 Maximum Units pF RPULLUP Input Pullup Resistor 51 kΩ RPULLDOWN Input Pulldown Resistor 51 kΩ TABLE 3B. OEA, OEB CONTROL INPUT FUNCTION TABLE Input OEA, OEB 0 Output QA/nQA, QB/nQB Disabled (Logic LOW) 1 Active IDT ™ / ICS™ LVDS MULTIPLEXER 3 ICS854S202AYI-01 REV. A JANUARY 8, 2007 ICS854S202I-01 12:2, DIFFERENTIAL-LVDS MULTIPLEXER PRELIMINARY TABLE 3B. SEL_A CONTROL INPUT FUNCTION TABLE SELA_3 0 Control Input SELA_2 SELA_1 0 0 SELA_0 0 Input Selected to QA/nQA CLK0, nCLK0 0 0 0 1 CLK1, nCLK1 0 0 1 0 CLK2, nCLK2 0 0 1 1 CLK3, nCLK3 0 1 0 0 CLK4, nCLK4 0 1 0 1 CLK5, nCLK5 0 1 1 0 CLK6, nCLK6 0 1 1 1 CLK7, nCLK7 1 0 0 0 CLK8, nCLK8 1 0 0 1 CLK9, nCLK9 1 0 1 0 CLK10, nCLK10 1 0 1 1 CLK11, nCLK11 1 1 0 0 L/H 1 1 0 1 L/H 1 1 1 0 L/H 1 1 1 1 L/H TABLE 3C. SEL_B CONTROL INPUT FUNCTION TABLE SELB_3 0 Control Input SELB_2 SELB_1 0 0 SELB_0 0 Input Selected to QB/nQB CLK0, nCLK0 0 0 0 1 CLK1, nCLK1 0 0 1 0 CLK2, nCLK2 0 0 1 1 CLK3, nCLK3 0 1 0 0 CLK4, nCLK4 0 1 0 1 CLK5, nCLK5 0 1 1 0 CLK6, nCLK6 0 1 1 1 CLK7, nCLK7 CLK8, nCLK8 1 0 0 0 1 0 0 1 CLK9, nCLK9 1 0 1 0 CLK10, nCLK10 1 0 1 1 CLK11, nCLK11 1 1 0 0 L/H 1 1 0 1 L/H 1 1 1 0 L/H 1 1 1 1 L/H IDT ™ / ICS™ LVDS MULTIPLEXER 4 ICS854S202AYI-01 REV. A JANUARY 8, 2007 ICS854S202I-01 12:2, DIFFERENTIAL-LVDS MULTIPLEXER PRELIMINARY ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD 4.6V NOTE: Stresses beyond those listed under Absolute Inputs, VI -0.5V to VDD + 0.5 V Outputs, IO (LVDS) Continuous Current Surge Current 10mA 15mA Maximum Ratings may cause per manent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Package Thermal Impedance, θJA 67.2°C/W (0 lfpm) Storage Temperature, TSTG -65°C to 150°C TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 2.5V±5%, TA = -40°C TO 85°C Symbol Parameter VDD Power Supply Voltage Test Conditions IDD Power Supply Current Minimum Typical Maximum Units 2.375 2.5 2.625 V 110 mA TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = 2.5V±5%, TA = -40°C TO 85°C Symbol Parameter VIH Input High Voltage VIL Input Low Voltage IIH IIL Input High Current Input Low Current Test Conditions SELA_0:3, SELB_0:3 OEA, OEB SELA_0:3, SELB_0:3 OEA, OEB Minimum Maximum Units 1.7 Typical VDD + 0.3 V -0.3 0.7 V VDD = 2.625V 15 0 µA VDD = 2.625V 5 µA VDD = 2.625V, VIN = 0V -5 µA VDD = 2.625V, VIN = 0V -150 µA TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = 2.5V±5%, TA = -40°C TO 85°C Symbol Parameter IIH Input High Current IIL Input Low Current Test Conditions CLK0:CLK11 nCLK0:nCLK11 Minimum Typical VDD = VIN = 2.625V Units 150 µA CLK0:CLK11 VDD = 2.625V, VIN = 0V -5 µA nCLK0:nCLK11 VDD = 2.625V, VIN = 0V -150 µA Peak-to-Peak Input Voltage 0.15 Common Mode Input Voltage; VCMR GND + 0.5 NOTE 1, 2 NOTE 1: Common mode voltage is defined as VIH. NOTE 2: For single ended applications, the maximum input voltage for CLKx, nCLKx is VDD + 0.3V. VPP IDT ™ / ICS™ LVDS MULTIPLEXER Maximum 5 1.3 V VDD – 0.85 V ICS854S202AYI-01 REV. A JANUARY 8, 2007 ICS854S202I-01 12:2, DIFFERENTIAL-LVDS MULTIPLEXER PRELIMINARY TABLE 4D. LVDS DC CHARACTERISTICS, VDD = 2.5V±5%, TA = -40°C TO 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VOD Differential Output Voltage 400 mV ∆ VOD VOD Magnitude Change 50 mV VOS Offset Voltage 1.3 V ∆ VOS VOS Magnitude Change 50 mV TABLE 5. AC CHARACTERISTICS, VDD = 2.5V ± 5%, TA = -40°C TO 85°C Symbol Parameter fMAX t sk(o) Output Frequency Propagation Delay, Low to High; NOTE 1 Propagation Delay, High to Low; NOTE 1 Output Skew; NOTE 2, 3 t sk(i) Input Skew; NOTE 3 TBD ps t sk(pp) TBD ps 0.16 ps tR / tF Par t-to-Par t Skew; NOTE 3, 4 Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter section, NOTE 5 Output Rise/Fall Time 110 ps od c Output Duty Cycle 50 % tpLH tpHL tjit Test Conditions 155.52MHz, Integration Range: 12kHz - 20MHz 20% to 80% Minimum Typical Maximum Units >3 GHz 650 ps 650 ps 25 ps fOUT < 1.2GHz 45 dB MUXISOLATION MUX Isolation All parameters measured at 500MHz, unless noted otherwise. NOTE 1: Measured from VDD/2 of the input to VDD/2 of the output. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDD/2. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. NOTE 4: Defined as skew between outputs on different devices operating a the same supply voltages and with equal load conditions. Using the same type of input on each device, the output is measured at VDD/2. NOTE 5: Driving only one input clock. IDT ™ / ICS™ LVDS MULTIPLEXER 6 ICS854S202AYI-01 REV. A JANUARY 8, 2007 ICS854S202I-01 12:2, DIFFERENTIAL-LVDS MULTIPLEXER PRELIMINARY ADDITIVE PHASE JITTER band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot. The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in the 1Hz Additive Phase Jitter at 155.52MHz SSB PHASE NOISE dBc/HZ (12kHz - 20MHz) = 0.16ps (typical) OFFSET FROM CARRIER FREQUENCY (HZ) meets the noise floor of what is shown, but can actually be lower. The phase noise is dependant on the input source and measurement equipment. As with most timing specifications, phase noise measurements have issues. The primary issue relates to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. This is illustrated above. The device IDT ™ / ICS™ LVDS MULTIPLEXER 7 ICS854S202AYI-01 REV. A JANUARY 8, 2007 ICS854S202I-01 12:2, DIFFERENTIAL-LVDS MULTIPLEXER PRELIMINARY PARAMETER MEASUREMENT INFORMATION VDD SCOPE Qx VDD 2.5V±5% POWER SUPPLY + Float GND – nCLK0:nCLK11 LVDS V V Cross Points PP CMR CLK0:CLK11 nQx GND 2.5V OUTPUT LOAD AC TEST CIRCUIT DIFFERENTIAL INPUT LEVEL Part 1 nQx nQx Qx Qx Part 2 nQy nQy Qy Qy tsk(pp) tsk(o) PART-TO-PART SKEW OUTPUT SKEW nCLK0:nCLK11 CLK0:CLK11 80% 80% VOD nQA, nQB Clock Outputs QA, QB tPD PROPAGATION DELAY IDT ™ / ICS™ LVDS MULTIPLEXER 20% 20% tR tF OUTPUT RISE/FALL TIME 8 ICS854S202AYI-01 REV. A JANUARY 8, 2007 ICS854S202I-01 12:2, DIFFERENTIAL-LVDS MULTIPLEXER PRELIMINARY nCLK0: nCLK11 CLK0: CLK11 nQA, nQB QA, QB nQA, nQB QA, QB tPD1 t PW t nCLKy odc = PERIOD t PW x 100% t PERIOD CLKy nQA, nQB QA, QB tPD2 tsk(i) = |tPD1 - tPD2| OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD INPUT SKEW VDD VDD out ➤ ➤ LVDS 100 DC Input VOD/∆ VOD out LVDS ➤ ➤ DC Input ➤ out out VOS/∆ VOS ➤ DIFFERENTIAL OUTPUT VOLTAGE SETUP IDT ™ / ICS™ LVDS MULTIPLEXER OFFSET VOLTAGE SETUP 9 ICS854S202AYI-01 REV. A JANUARY 8, 2007 ICS854S202I-01 12:2, DIFFERENTIAL-LVDS MULTIPLEXER PRELIMINARY APPLICATION INFORMATION RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS: OUTPUTS: CLK/nCLK INPUT: For applications not requiring the use of the differential input, both CLK and nCLK can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from CLK to ground. LVDS OUTPUT All unused LVDS output pairs can be either left floating or ter minated with 100Ω across. If they are left floating, we recommend that there is no trace attached. LVCMOS CONTROL PINS: All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V VDD R1 1K Single Ended Clock Input CLKx V_REF nCLKx C1 0.1u R2 1K FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT IDT ™ / ICS™ LVDS MULTIPLEXER 10 ICS854S202AYI-01 REV. A JANUARY 8, 2007 ICS854S202I-01 12:2, DIFFERENTIAL-LVDS MULTIPLEXER PRELIMINARY DIFFERENTIAL CLOCK INPUT INTERFACE The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both V SWING and VOH must meet the V PP and V CMR input requirements. Figures 2A to 2E show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 2A, the input termination applies for IDT HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation. 3.3V 3.3V 3.3V 1.8V Zo = 50 Ohm CLK Zo = 50 Ohm CLK Zo = 50 Ohm nCLK Zo = 50 Ohm LVPECL nCLK HiPerClockS Input LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 R1 50 HiPerClockS Input R2 50 R2 50 R3 50 FIGURE 2A. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY IDT HIPERCLOCKS LVHSTL DRIVER FIGURE 2B. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY 3.3V LVPECL DRIVER 3.3V 3.3V 3.3V 3.3V 3.3V R3 125 R4 125 Zo = 50 Ohm LVDS_Driv er Zo = 50 Ohm CLK CLK R1 100 Zo = 50 Ohm nCLK LVPECL R1 84 HiPerClockS Input nCLK Receiv er Zo = 50 Ohm R2 84 FIGURE 2C. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY 3.3V LVPECL DRIVER FIGURE 2D. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY 3.3V LVDS DRIVER 3.3V 3.3V 3.3V LVPECL Zo = 50 Ohm C1 Zo = 50 Ohm C2 R3 125 R4 125 CLK nCLK R5 100 - 200 R6 100 - 200 R1 84 HiPerClockS Input R2 84 R5,R6 locate near the driver pin. FIGURE 2E. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY 3.3V LVPECL DRIVER WITH AC COUPLE IDT ™ / ICS™ LVDS MULTIPLEXER 11 ICS854S202AYI-01 REV. A JANUARY 8, 2007 ICS854S202I-01 12:2, DIFFERENTIAL-LVDS MULTIPLEXER PRELIMINARY 2.5V LVDS DRIVER TERMINATION Figure 3 shows a typical termination for LVDS driver in characteristic impedance of 100Ω differential (50Ω single) transmission line environment. For buffer with multiple LDVS driver, it is recommended to terminate the unused outputs. 2.5V 2.5V LVDS_Driv er + R1 100 - 100 Ohm Transmission Line ΩDifferential 100Ω Differential Transmission Line FIGURE 3. TYPICAL LVDS DRIVER TERMINATION IDT ™ / ICS™ LVDS MULTIPLEXER 12 ICS854S202AYI-01 REV. A JANUARY 8, 2007 ICS854S202I-01 12:2, DIFFERENTIAL-LVDS MULTIPLEXER PRELIMINARY POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS854S202I-01. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS854S202I-01 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 2.5V + 5% = 2.625V, which gives worst case results. • Power (core)MAX = VDD_MAX * IDD_MAX = 2.625V * 110mA = 288.75mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 57.4°C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.289W * 57.4°C/W = 101.6°C. This is well below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). TABLE 6. THERMAL RESISTANCE θJA FOR 48-LEAD LQFP, FORCED CONVECTION θJA vs. Air Flow (Linear Feet per Minute) Multi-Layer PCB, JEDEC Standard Test Boards IDT ™ / ICS™ LVDS MULTIPLEXER 0 200 500 67.2°C/W 57.4°C/W 53.8°C/W 13 ICS854S202AYI-01 REV. A JANUARY 8, 2007 ICS854S202I-01 12:2, DIFFERENTIAL-LVDS MULTIPLEXER PRELIMINARY RELIABILITY INFORMATION TABLE 7. θJAVS. AIR FLOW TABLE FOR 48 LEAD LQFP θJA vs. Air Flow (Linear Feet per Minute) Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 67.2°C/W 57.4°C/W 53.8°C/W TRANSISTOR COUNT The transistor count for ICS854S202I-01 is: 8,485 IDT ™ / ICS™ LVDS MULTIPLEXER 14 ICS854S202AYI-01 REV. A JANUARY 8, 2007 ICS854S202I-01 12:2, DIFFERENTIAL-LVDS MULTIPLEXER PRELIMINARY PACKAGE OUTLINE - Y SUFFIX FOR 48 LEAD LQFP TABLE 8. PACKAGE DIMENSIONS JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS SYMBOL BBC MINIMUM NOMINAL MAXIMUM 48 N A -- -- 1.60 A1 0.05 -- 0.15 A2 1.35 1.40 1.45 b 0.17 0.22 0.27 c 0.09 -- 0.20 D 9.00 BASIC D1 7.00 BASIC D2 5.50 Ref. E 9.00 BASIC E1 7.00 BASIC E2 5.50 Ref. e 0.50 BASIC L 0.45 0.60 θ 0° -- 0.75 7° ccc -- -- 0.08 Reference Document: JEDEC Publication 95, MS-026 IDT ™ / ICS™ LVDS MULTIPLEXER 15 ICS854S202AYI-01 REV. A JANUARY 8, 2007 ICS854S202I-01 12:2, DIFFERENTIAL-LVDS MULTIPLEXER PRELIMINARY TABLE 9. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature ICS854S202AYI-01 ICS4S202AI01 48 Lead LQFP tray -40°C to 85°C ICS854S202AYI-01T ICS4S202AI01 48 Lead LQFP 1000 tape & reel -40°C to 85°C ICS854S202AYI-01LF TBD 48 Lead "Lead-Free" LQFP tray -40°C to 85°C ICS854S202AYI-01LFT TBD 48 Lead "Lead-Free" LQFP 1000 tape & reel -40°C to 85°C NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDT ™ / ICS™ LVDS MULTIPLEXER 16 ICS854S202AYI-01 REV. A JANUARY 8, 2007 ICS854S202I-01 12:2, DIFFERENTIAL-LVDS MULTIPLEXER PRELIMINARY Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales For Tech Support 800-345-7015 408-284-8200 Fax: 408-284-2775 [email protected] 480-763-2056 Corporate Headquarters Asia Pacific and Japan Europe Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.) Integrated Device Technology Singapore (1997) Pte. Ltd. Reg. No. 199707558G 435 Orchard Road #20-03 Wisma Atria Singapore 238877 +65 6 887 5505 IDT Europe, Limited 321 Kingston Road Leatherhead, Surrey KT22 7TU England +44 (0) 1372 363 339 Fax: +44 (0) 1372 378851 © 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA