PRELIMINARY Integrated Circuit Systems, Inc. ICS853111 LOW SKEW, 1-TO-10 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER GENERAL DESCRIPTION FEATURES The ICS853111 is a low skew, high performance 1-to-10 Differential-to-2.5V/3.3V LVPECL/ HiPerClockS™ ECL Fanout Buffer and a member of the HiPerClockS™ family of High Performance Clock Solutions from ICS. The ICS853111 is characterized to operate from either a 2.5V or a 3.3V power supply. Guaranteed output and part-to-part skew characteristics make the ICS853111 ideal for those clock distribution applications demanding well defined performance and repeatability. • 10 differential 2.5V/3.3V LVPECL / ECL outputs ,&6 • 2 selectable differential input pairs • PCLKx, nPCLKx pairs can accept the following differential input levels: LVPECL, LVDS, CML, SSTL • Maximum output frequency: >3GHz • Translates any single ended input signal to 3.3V LVPECL levels with resistor bias on nPCLK input • Output skew: TBD • Part-to-part skew: TBD • Propagation delay: TBD • LVPECL mode operating voltage supply range: VCC = 2.375V to 3.8V, VEE = 0V • ECL mode operating voltage supply range: VCC = 0V, VEE = -3.8V to -2.375V • -40°C to 85°C ambient operating temperature • Pin compatible with MC100EP111 and MC100LVEP111 24 23 22 21 20 19 18 17 VCCO 25 16 VCCO nQ2 26 15 Q7 Q2 27 14 nQ7 Q3 nQ3 nQ1 28 13 Q8 Q1 29 12 nQ8 Q4 nQ4 nQ0 30 11 Q9 Q0 31 10 nQ9 Q5 nQ5 VCCO 32 9 VCCO 3 4 5 6 7 8 nPCLK0 VBB PCLK1 nPCLK1 VEE Q7 nQ7 2 PCLK0 Q6 nQ6 1 VCC V BB ICS853111 CLK_SEL Q2 nQ2 CLK_SEL nQ6 Q1 nQ1 Q6 1 nQ5 PCLK1 nPCLK1 Q5 Q0 nQ0 nQ4 0 Q4 PCLK0 nPCLK0 nQ3 PIN ASSIGNMENT Q3 BLOCK DIAGRAM 32-Lead LQFP 7mm x 7mm x 1.4mm package body Y Package Top View Q8 nQ8 Q9 nQ9 The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice. 853111AY www.icst.com/products/hiperclocks.html REV. D JULY 22, 2003 1 PRELIMINARY Integrated Circuit Systems, Inc. ICS853111 LOW SKEW, 1-TO-10 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER TABLE 1. PIN DESCRIPTIONS Number Name 1 VCC Power Type Description 2 CLK_SEL Input Pulldown 3 PCLK0 Input Pulldown 4 nPCLK0 Input Pullup/Pulldown 5 VBB Output 6 PCLK1 Input Pulldown 7 nPCLK1 Input Pullup/Pulldown 8 VEE Power Core supply pin. Clock select input. When HIGH, selects PCLK1, nPCLK1 inputs. When LOW, selects PCLK0, nPCLK0 inputs. LVCMOS / LVTTL interface levels. Non-inver ting differential clock input. Inver ting differential LVPECL clock input. VCC/2 default when left floating. Bias voltage. Non-inver ting differential clock input. Inver ting differential LVPECL clock input. VCC/2 default when left floating. Negative supply pin. 9, 16, 25, 32 VCCO Power Output supply pins. 10, 11 nQ9, Q9 Output Differential output pair. LVPECL interface levels. 1 2, 13 nQ8, Q8 Output Differential output pair. LVPECL interface levels. 14, 15 nQ7, Q7 Output Differential output pair. LVPECL interface levels. 17, 18 nQ6, Q6 Output Differential output pair. LVPECL interface levels. 19, 20 nQ5, Q5 Output Differential output pair. LVPECL interface levels. 21, 22 nQ4, Q4 Output Differential output pair. LVPECL interface levels. 23, 24 nQ3, Q3 Output Differential output pair. LVPECL interface levels. 26, 27 nQ2, Q2 Output Differential output pair. LVPECL interface levels. 28, 29 nQ1, Q1 Output Differential output pair. LVPECL interface levels. 30, 31 nQ0, Q0 Output Differential output pair. LVPECL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions Minimum RPULLDOWN Input Pulldown Resistor 75 KΩ RVCC/2 Pullup/Pulldown Resistors 50 KΩ CLKx Outputs nCLKx Q0:Q9 nQ0:Q9 Maximum Units TABLE 3A. CONTROL INPUT FUNCTION TABLE TABLE 3B. CLOCK INPUT FUNCTION TABLE Inputs Typical Input to Output Mode Polarity Inputs 0 1 LOW HIGH Differential to Differential Non Inver ting CLK_SEL 1 0 Biased; NOTE 1 Biased; NOTE 1 HIGH LOW Differential to Differential Non Inver ting 0 CLK0, nCLK0 LOW HIGH Single Ended to Differential Non Inver ting 1 CLK1, nCLK1 HIGH LOW Single Ended to Differential Non Inver ting 0 1 Selected Source Biased; 0 HIGH LOW Single Ended to Differential Inver ting NOTE 1 Biased; 1 LOW HIGH Single Ended to Differential Inver ting NOTE 1 NOTE 1: Please refer to the Application Information, "Wiring the Differential Input to Accept Single Ended Levels". 853111AY www.icst.com/products/hiperclocks.html 2 REV. D JULY 22, 2003 PRELIMINARY Integrated Circuit Systems, Inc. ICS853111 LOW SKEW, 1-TO-10 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCC Negative Supply Voltage, VEE Inputs, VI (LVPECL mode) Inputs, VI (ECL mode) Outputs, IO Continuous Current Surge Current VBB Sink/Source, IBB 4.6V (LVPECL mode, VEE = 0) NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage -4.6V (ECL mode, VCC = 0) to the device. These ratings are stress specifi-0.5V to VCC + 0.5 V cations only. Functional operation of product at 0.5V to VEE - 0.5V these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. 50mA 100mA ± 0.5mA Operating Temperature Range, TA -40°C to +85°C Storage Temperature, TSTG -65°C to 150°C Package Thermal Impedance, θJA 37.8°C/W (0 lfpm) (Junction-to-Ambient) TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = 2.375 TO 3.8V; VEE = 0V Symbol Parameter VCC Positive Supply Voltage IEE Power Supply Current Test Conditions Minimum Typical Maximum Units 2.375 3.3 3.8 V TBD mA TABLE 4B. LVPECL DC CHARACTERISTICS, VCC = 3.3V; VEE = 0V Symbol Parameter VOH VOL -40°C 25°C 85°C Units Min Typ Max Min Typ Max Min Typ Max Output High Voltage; NOTE 1 2.175 2.275 2.38 2.225 2.295 2.37 2.295 2.33 2.365 V Output Low Voltage; NOTE 1 1.405 1.545 1.68 1.425 1.52 1.615 1 .4 4 1.535 1 .6 3 V VIH Input High Voltage(Single-Ended) 2.075 2.36 2.075 2 .3 6 2.075 2.36 V VIL Input Low Voltage(Single-Ended) 1.43 1.765 1.43 1.765 1.43 1.765 V VBB Output Voltage Reference; NOTE 2 1.86 1.98 1.86 1.98 1.86 1.98 V VPP Peak-to-Peak Input Voltage Input High Voltage Common Mode Range; NOTE 3, 4 PCLK0, PCLK1 Input High Current nPCLK0, nPCLK1 150 1200 150 1200 150 1200 V 3.3 1.2 3.3 1.2 3.3 V 150 µA VCMR IIH 800 1.2 150 800 800 150 PCLK0, PCLK1 -150 -150 -150 nPCLK0, nPCLK1 Input and output parameters vary 1:1 with VCC. VEE can vary +0.925V to -0.5V. NOTE 1: Outputs terminated with 50Ω to VCCO - 2V. NOTE 2: Single-ended input operation is limited VCC ≥ 3V in LVPECL mode. NOTE 3: Common mode voltage is defined as VIH. NOTE 4: For single-ended applications, the maximum input voltage for PCLK0, nPCLK0 and PCLK1, nPCLK1 is VCC + 0.3V. IIL 853111AY Input Low Current www.icst.com/products/hiperclocks.html 3 µA REV. D JULY 22, 2003 PRELIMINARY Integrated Circuit Systems, Inc. ICS853111 LOW SKEW, 1-TO-10 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = 2.5V; VEE = 0V Symbol Parameter -40°C Min 25°C Typ Max Min Typ 85°C Max Min Typ Max Units VOH Output High Voltage; NOTE 1 1.375 1.475 1.58 1.425 1.495 1.57 1.495 1.53 1.565 V VOL Output Low Voltage; NOTE 1 0.605 0.745 0.88 0.625 0.72 0.815 0.64 0.735 0.83 V VIH Input High Voltage(Single-Ended) 1.275 1.56 1.275 1.56 1.275 -0.8 V VIL Input Low Voltage(Single-Ended) 0.63 0.965 0.63 0.965 0.63 0.965 V VPP Peak-to-Peak Input Voltage Input High Voltage Common Mode Range; NOTE 2, 3 PCLK0, PCLK1 Input High Current nPCLK0, nPCLK1 150 1200 150 1200 150 1200 V 2.5 1.2 2.5 1.2 2.5 V 150 µA VCMR IIH 800 1.2 800 150 800 150 PCLK0, PCLK1 -150 -150 -150 nPCLK0, nPCLK1 Input and output parameters var y 1:1 with VCC. VEE can var y +0.125V to -1.3V. NOTE 1: Outputs terminated with 50Ω to VCCO - 2V. NOTE 2: Common mode voltage is defined as VIH. NOTE 3: For single-ended applications, the maximum input voltage for PCLK0, nPCLK0 and PCLK1, nPCLK1 is VCC + 0.3V. IIL Input Low Current µA TABLE 4C. ECL DC CHARACTERISTICS, VCC = 0V; VEE = -3.8V TO -2.375V Symbol Parameter VOH -40°C 25°C 85°C Units Min Typ Max Min Typ Max Min Typ Max Output High Voltage; NOTE 1 -1.125 -1.025 -0.92 -1.075 -1.005 -0.93 -1.005 -0.97 -0.935 V VOL Output Low Voltage; NOTE 1 -1.895 -1.755 -1.62 -1.875 -1.78 -1.685 -1.86 -1.765 -1.67 V VIH Input High Voltage(Single-Ended) -1.225 -0.94 -1.225 -0.94 -1.225 -0.94 V VIL Input Low Voltage(Single-Ended) Output Voltage Reference; NOTE 2 Peak-to-Peak Input Voltage Input High Voltage Common Mode Range; NOTE 3, 4 Input PCLK0, PCLK1 High Current nPCLK0, nPCLK1 -1.87 -1.535 -1.87 -1.535 -1.87 -1.535 V -1.486 -1.386 -1.486 -1.386 -1.486 -1.386 V 1200 150 1200 150 1200 V 0 VE E+ 1 . 2 V 0 VEE+1.2V 0 V 150 µA VBB VPP VCMR IIH 150 800 VEE+1.2V 800 150 800 150 Input PCLK0, PCLK1 -150 -150 -150 Low Current nPCLK0, nPCLK1 Input and output parameters vary 1:1 with VCC. VEE can vary +0.925V to -0.5V. NOTE 1: Outputs terminated with 50Ω to VCCO - 2V. NOTE 2: Single-ended input operation is limited VCC ≥ 3V in LVPECL mode. NOTE 3: Common mode voltage is defined as VIH. NOTE 4: For single-ended applications, the maximum input voltage for PCLK0, nPCLK0 and PCLK1, nPCLK1 is VCC + 0.3V. IIL 853111AY www.icst.com/products/hiperclocks.html 4 µA REV. D JULY 22, 2003 PRELIMINARY Integrated Circuit Systems, Inc. ICS853111 LOW SKEW, 1-TO-10 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER TABLE 5. AC CHARACTERISTICS, VCC = 0V; VEE = -3.8V TO -2.375V OR VCC = 2.375 TO 3.8V; VEE = 0V Symbol -40°C Parameter Min Typ 25°C Max Min Typ 85°C Max Min Typ Max Units fMAX Output Frequency >3 >3 >3 GHz tPD Propagation Delay; NOTE 1 660 695 745 ps tsk(o) Output Skew; NOTE 2, 4 TBD TBD TBD ps tsk(pp) Par t-to-Par t Skew; NOTE 3, 4 TBD TBD TBD ps tR/tF Output Rise/Fall Time TBD TBD TBD ps 20% to 80% All parameters are measured ≤ 1GHz unless otherwise noted. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. 853111AY www.icst.com/products/hiperclocks.html 5 REV. D JULY 22, 2003 PRELIMINARY Integrated Circuit Systems, Inc. ICS853111 LOW SKEW, 1-TO-10 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER PARAMETER MEASUREMENT INFORMATION VCC, VCCO = 2V Qx VCC SCOPE nCLK0, nCLK1 LVPECL V Cross Points PP V CMR CLK0, CLK1 nQx V EE VEE = -0.375V to -1.8V 3.3V OUTPUT LOAD AC TEST CIRCUIT DIFFERENTIAL INPUT LEVEL nQx PART 1 Qx nQx nQy nQy Qx PART 2 Qy Qy tsk(pp) tsk(o) PART-TO-PART SKEW OUTPUT SKEW nCLK0, nCLK1 80% 80% CLK0, CLK1 VSW I N G Clock Outputs nQ0:nQ9 20% 20% tR tF Q0:Q9 tPD OUTPUT RISE/FALL TIME 853111AY PROPAGATION DELAY www.icst.com/products/hiperclocks.html 6 REV. D JULY 22, 2003 PRELIMINARY Integrated Circuit Systems, Inc. ICS853111 LOW SKEW, 1-TO-10 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER APPLICATION INFORMATION WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LVCMOS LEVELS Figure 2A shows an example of the differential input that can be wired to accept single ended LVCMOS levels. The reference voltage level VBB generated from the device is connected to the negative input. The C1 capacitor should be located as close as possible to the input pin. VCC R1 1K Single Ended Clock Input PCLK V_REF nPCLK C1 0.1u R2 1K FIGURE 2A. SINGLE ENDED LVCMOS SIGNAL DRIVING DIFFERENTIAL INPUT WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LVPECL LEVELS Figure 2B shows an example of the differential input that can be wired to accept single ended LVPECL levels. The reference voltage level VBB generated from the device is connected to the negative input. The C1 capacitor should be located as close as possible to the input pin. VDD(or VCC) CLK_IN + VBB - C1 0.1uF FIGURE 2B. SINGLE ENDED LVPECL SIGNAL DRIVING DIFFERENTIAL INPUT 853111AY www.icst.com/products/hiperclocks.html 7 REV. D JULY 22, 2003 PRELIMINARY Integrated Circuit Systems, Inc. TERMINATION FOR ICS853111 LOW SKEW, 1-TO-10 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER 3.3V LVPECL OUTPUTS 50Ω transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 3A and 3B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 3.3V Zo = 50Ω 5 2 Zo FIN FOUT 5 2 Zo Zo = 50Ω Zo = 50Ω FOUT ➤ RTT = 1 (VOH + VOL / VCC –2) –2 VCC - 2V Zo = 50Ω RTT 3 2 Zo Zo FIGURE 3A. LVPECL OUTPUT TERMINATION 853111AY FIN 50 Ω 50Ω 3 2 Zo FIGURE 3B. LVPECL OUTPUT TERMINATION www.icst.com/products/hiperclocks.html 8 REV. D JULY 22, 2003 PRELIMINARY Integrated Circuit Systems, Inc. ICS853111 LOW SKEW, 1-TO-10 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER TERMINATION FOR 2.5V LVPECL OUTPUT Figure 3A and Figure 4B show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating 50Ω to VCC - 2V. For VCC = 2.5V, the VCC - 2V is very close to ground level. The R3 in Figure 4B can be eliminated and the termination is shown in Figure 4C. 2.5V 2.5V 2.5V VCCO=2.5V VCCO=2.5V R1 250 R3 250 Zo = 50 Ohm Zo = 50 Ohm + + Zo = 50 Ohm Zo = 50 Ohm - - 2,5V LVPECL Driv er 2,5V LVPECL Driv er R2 62.5 R1 50 R4 62.5 R2 50 R3 18 FIGURE 4A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE FIGURE 4B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE 2.5V VCCO=2.5V Zo = 50 Ohm + Zo = 50 Ohm 2,5V LVPECL Driv er R1 50 R2 50 FIGURE 4C. 2.5V LVPECL TERMINATION EXAMPLE 853111AY www.icst.com/products/hiperclocks.html 9 REV. D JULY 22, 2003 PRELIMINARY Integrated Circuit Systems, Inc. ICS853111 LOW SKEW, 1-TO-10 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER LVPECL CLOCK INPUT INTERFACE The PCLK /nPCLK accepts LVPECL, CML, SSTL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 5A to 5E show interface examples for the HiPerClockS PCLK/nPCLK input driven by the most common driver types. The input interfaces sug- gested here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements. 2.5V 3.3V 3.3V 3.3V 2.5V 3.3V R1 50 CML R3 120 R2 50 SSTL Zo = 50 Ohm R4 120 Zo = 60 Ohm PCLK PCLK Zo = 60 Ohm Zo = 50 Ohm nPCLK nPCLK HiPerClockS PCLK/nPCLK R1 120 FIGURE 5A. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN BY A CML DRIVER HiPerClockS PCLK/nPCLK R2 120 FIGURE 5B. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN BY AN SSTL DRIVER 3.3V 3.3V 3.3V 3.3V R3 125 Zo = 50 Ohm 3.3V R4 125 LVDS_Driv er Zo = 50 Ohm CLK CLK R1 100 Zo = 50 Ohm nCLK LVPECL R1 84 nCLK Receiv er Zo = 50 Ohm HiPerClockS Input R2 84 FIGURE 5C. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER FIGURE 5D. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN BY A 3.3V LVDS DRIVER 3.3V 3.3V 3.3V 3.3V LVPECL Zo = 50 Ohm C1 Zo = 50 Ohm C2 R3 84 R4 84 PCLK nPCLK R5 100 - 200 R6 100 - 200 R1 125 HiPerClockS PCLK/nPCLK R2 125 FIGURE 5E. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER WITH AC COUPLE 853111AY www.icst.com/products/hiperclocks.html 10 REV. D JULY 22, 2003 PRELIMINARY Integrated Circuit Systems, Inc. ICS853111 LOW SKEW, 1-TO-10 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER SCHEMATIC EXAMPLE This application note provides general design guide using ICS853111 LVPECL buffer. Figure 6 shows a schematic example of the ICS853111 LVPECL clock buffer. In this example, the input is driven by an LVPECL driver. CLK_SEL is set at logic high to select PCLK0/nPCLK0 input. Zo = 50 + Zo = 50 - R2 50 VCC 32 31 30 29 28 27 26 25 C6 (Option) 0.1u R3 50 VCCO Q0 nQ0 Q1 nQ1 Q2 nQ2 VCCO VCC R1 50 Zo = 50 Ohm 1 2 3 4 5 6 7 8 Zo = 50 Ohm R4 1K R10 50 C8 (Option) 0.1u R11 50 9 10 11 12 13 14 15 16 R9 50 Q3 nQ3 Q4 nQ4 Q5 nQ5 Q6 nQ6 24 23 22 21 20 19 18 17 VCCO nQ9 Q9 nQ8 Q8 nQ7 Q7 VCCO 3.3V LVPECL VCC CLK_SEL PCLK0 nPCLK0 VBB PCLK1 nPCLK1 VEE U1 ICS853111 VCC Zo = 50 + VCC=3.3V Zo = 50 (U1-9) VCC (U1-16) (U1-25) (U1-32) - (U1-1) R8 50 C1 0.1uF C2 0.1uF C3 0.1uF C4 0.1uF R7 50 C5 0.1uF C7 (Option) 0.1u R13 50 FIGURE 6. EXAMPLE ICS853111 LVPECL CLOCK OUTPUT BUFFER SCHEMATIC RELIABILITY INFORMATION TABLE 6. θJAVS. AIR FLOW TABLE q by Velocity (Linear Feet per Minute) JA Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 67.8°C/W 47.9°C/W 55.9°C/W 42.1°C/W 50.1°C/W 39.4°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS853111 is: 1340 853111AY www.icst.com/products/hiperclocks.html 11 REV. D JULY 22, 2003 PRELIMINARY Integrated Circuit Systems, Inc. ICS853111 LOW SKEW, 1-TO-10 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER PACKAGE OUTLINE - Y SUFFIX TABLE 7. PACKAGE DIMENSIONS JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS BBA SYMBOL MINIMUM NOMINAL MAXIMUM 32 N A -- -- 1.60 A1 0.05 -- 0.15 A2 1.35 1.40 1.45 b 0.30 0.37 0.45 c 0.09 -- 0.20 D 9.00 BASIC D1 7.00 BASIC D2 5.60 Ref. E 9.00 BASIC E1 7.00 BASIC E2 5.60 Ref. 0.80 BASIC e L 0.45 0.60 0.75 q 0° -- 7° ccc -- -- 0.10 Reference Document: JEDEC Publication 95, MS-026 853111AY www.icst.com/products/hiperclocks.html 12 REV. D JULY 22, 2003 PRELIMINARY Integrated Circuit Systems, Inc. ICS853111 LOW SKEW, 1-TO-10 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER TABLE 8. ORDERING INFORMATION Part/Order Number Marking Package Count Temperature ICS853111AY ICS853111AY 32 lead LQFP 250 per tray -40°C to 85°C ICS853111AYT ICS853111AY 32 lead LQFP on Tape and Reel 1000 -40°C to 85°C While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 853111AY www.icst.com/products/hiperclocks.html 13 REV. D JULY 22, 2003