ICS ICS9250YF-10

ICS9250-10
Integrated
Circuit
Systems, Inc.
Preliminary Product Preview
Frequency Timing Generator for Pentium II Systems
General Description
The ICS9250-10 is a single chip clock for Intel Pentium II.
It provides all necessary clock signals for such a system.
Spread spectrum may be enabled through I2C programming.
Spread spectrum typically reduces EMI by 8dB to 10 dB.
This simplifies EMI qualification without resorting to board
design iterations or costly shielding. The ICS9250-10
employs a proprietary closed loop design, which tightly
controls the percentage of spreading over process and
temperature variations.
Block Diagram
Features
•
•
•
•
•
Generates the following system clocks:
- 3 CPU (2.5V) 66.6/100 MHz (up to 133MHz through
I2C selection)
- 9 SDRAM (3.3V) up to 133MHz
- 8 PCI (3.3 V) @33.3MHz
- 2 IOAPIC (2.5V) @16.67 or 33.3MHz
- 2 Hublink clocks (3.3 V) @ 66.6 MHz
- 2 USB (3.3V) @ 48 MHz ( Non spread spectrum)
- 1 REF (3.3V) @ 14.318 MHz
Supports spread spectrum modulation ,
down spread 0 to -0.5%
I2C support for power management
Efficient power management scheme through PD#
Uses external 14.138 MHz crystal
Pin Configuration
56-Pin 300 mil SSOP
*60K ohm pull-up to VDD on indicated inputs.
Power Groups
Pentium II is a trademark of Intel Corporation
I2C is a trademark of Philips Corporation
9250-10 Rev J 6/15/99
VDD0, GND0 = REF & Crystal
VDD1, GND1 = 3V66 [1:0]
VDD2, GND2 = PCICLK[7:0]
VDD3, GND3 = PLL core
VDD4, GND4 = 48MHz [1:0]
VDD5, GND5 = SDRAM_F, SDRAM [7:0]
VDDL0, GNDL0 = CPUCLK [2:0]
VDDL1, GNDL1 = IOAPIC [1:0]
PRODUCT PREVIEW documents contain information on new
products in the sampling or preproduction phase of development.
Characteristic data and other specifications are subject to change
without notice.
ICS9250-10
Preliminary Product Preview
Pin Descriptions
PIN NUMBER
3
X1
IN
4
X2
OUT
DESCRIPTION
Latched input at Power On. this determines the IOAPIC frequency.
When a "0" is latched, IOAPIC Freq=16.67MHz
When "1" is latched, IOAPIC Freq=33.3MHz
This pin has a 60K internal pull-up.
3.3V, 14.318MHz reference clock output.
Crystal input, has internal load cap (33pF) and feedback
resistor from X2
Crystal output, nominally 14.318MHz. Has internal load
cap (33pF)
5, 6, 14, 17, 23,
24, 35, 41, 47
GND (0:5)
PWR
Ground pins for 3.3V supply
8, 7
3V66 [1:0]
OUT
3 . 3 V F i xe d 6 6 M H z c l o c k o u t p u t s f o r H U B
PWR
3.3V power supply
OUT
3.3V PCI clock outputs, with Synchronous CPUCLKS
OUT
3 . 3 V F i xe d 4 8 M H z c l o c k o u t p u t s f o r U S B
1
P I N NA M E
FREQ_APIC
REF0
2, 9, 10, 21,
VDD (0:5)
22, 27, 33, 38, 44
20,19,18,16,
PCICLK[7:0]
15,13,12,11
TYPE
IN
OUT
25, 26
48MHz (0:1)
28, 29
FS (0:1)
IN
Function Select pins. Determines CPU frequency, all output
functionality. Please refer to Functionality table on page 3.
30
SDATA
IN
Data input for I2C serial input.
31
SCLK
IN
Clock input of I2C input
32
PD#
IN
36, 37, 39, 40, 42,
SDRAM [7:0]
43, 45, 46
OUT
Asynchronous active low input pin used to power down the device
into a low power state. The internal clocks are disabled and the
VCO and the crystal are stopped. The latency of the power down
will not be greater than 3ms.
3.3V output running 100MHz. All SDRAM outputs can be turned
off through I2C
34
SDRAM_F
OUT
3.3V free running 100MHz SDRAM not affected by I2C
56,48
GNDL [1:0]
PWR
Ground for 2.5V power supply for CPU & APIC
CPUCLK [2:0]
OUT
2.5V Host bus clock output. 66MHz or 100MHz depending on FS
(0:1) pins Refer page 3.
51, 53
VDDL (0:1)
PWR
2.5V power suypply for CPU & IOAPIC
54, 55
IOAPIC [1:0]
OUT
2.5V clock outputs running at 16.67MHz or 33.3MHz.
49,50,52
2
ICS9250-10
Preliminary Product Preview
Functionality Table
FS1
FS0
CPU
SDRAM
3V66
PCICLK
48MHz
REF0
IOAPIC
0
0
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
0
1
TCLK/2
TCLK/4
TCLK/4
TCLK/8
TCLK/2
TCLK
TCLK/16
1
0
66 MHz
100 MHz
66 MHz
33 MHz
48 MHz
14.318MHz
16.67MHz
1
1
100 MHz
100 MHz
66 MHz
33MHz
48 MHz
14.318MHZ
16.67MHz
Clock Enable Configuration
PD#
CPUCLK
SDRAM
IOAPIC
66MHz
PCICLK
REF,
48MHz
Osc
VCOs
0
LOW
LOW
LOW
LOW
LOW
LOW
OFF
OF F
1
ON
ON
ON
ON
ON
ON
ON
ON
Select Functions
FS1
FS0
Notes
0
0
Tristate
0
1
Test Mode
1
0
Active CPU = 66MHz
1
1
Active CPU = 100MHz
3
Notes
Tristate
Test Mode
ICS9250-10
Preliminary Product Preview
Power Down Waveform
Note
1. After PD# is sampled active (Low) for 2 consective rising edges of CPUCLKs, all
the output clocks are driven Low on their next High to Low tranistiion.
2. Power-up latency <3ms.
3. Waveform shown for 100MHz
Maximum Allowed Current
Max 2.5V supply consumption
Max discrete cap loads,
Vddq2 = 2.625V
All static inputs = Vddq3 or GND
Max 2.5V supply consumption
Max discrete cap loads,
Vddq2 = 3.465V
All static inputs = Vddq3 or GND
Powerdown Mode
(PWRDWN# = 0
10mA
10mA
Full Active 66MHz
SEL1, 0 = 10
70mA
280mA
Full Active 100MHz
SEL1, 0 = 11
100mA
280mA
810E
Condition
4
ICS9250-10
Preliminary Product Preview
General I2C serial interface information
The information in this section assumes familiarity with I2C programming.
For more information, contact ICS for an I2C programming application note.
How to Write:
How to Read:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Controller (host) sends a start bit.
Controller (host) sends the write address D2 (H)
ICS clock will acknowledge
Controller (host) sends a dummy command code
ICS clock will acknowledge
Controller (host) sends a dummy byte count
ICS clock will acknowledge
Controller (host) starts sending first byte (Byte 0)
through byte 5
• ICS clock will acknowledge each byte one at a time.
• Controller (host) sends a Stop bit
Controller (host) will send start bit.
Controler (host) sends the read address D3 (H)
ICS clock will acknowledge
ICS clock will send the byte count
Controller (host) acknowledges
ICS clock sends first byte (Byte 0) through byte 5
Controller (host) will need to acknowledge each byte
Controller (host) will send a stop bit
How to Write:
Controller (Host)
Start Bit
Address
D2(H)
ICS (Slave/Receiver)
How to Read:
Controller (Host)
Start Bit
Address
D3(H)
ACK
Dummy Command Code
ACK
ACK
Byte Count
Dummy Byte Count
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
Stop Bit
Byte 0
Byte 0
Byte 1
Byte 1
Byte 2
Byte 2
Byte 3
Byte 3
Byte 4
Byte 4
Byte 5
Byte 5
Stop Bit
Notes:
1.
2.
3.
4.
5.
6.
ICS (Slave/Receiver)
The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification.
Read-Back will support Intel PIIX4 "Block-Read" protocol.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
The input is operating at 3.3V logic levels.
The data byte format is 8 bit bytes.
To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte
has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those
two bytes. The data is loaded until a Stop sequence is issued.
At power-on, all registers are set to a default condition, as shown.
5
ICS9250-10
Preliminary Product Preview
Byte 5:ICS Reserved Functionality and frequency select register (Default=0)
Bit
Desctiption
PWD
Bit7
ICS RESERVED BIT (Needs to be 0 clock to operate normal)
0
Bit6
ICS RESERVED BIT (Needs to be 0 clock to operate normal)
0
Bit5
ICS RESERVED BIT (Needs to be 0 clock to operate normal)
0
Bit (4,3,0)
Bit
(4,3,0)
CPUCLK SDRAM
MHz
MHz
3V66
MHz
PCICLK
MHz
100
66.67
33.33
70.67
106
70.67
35.33
0
74.66
112
74.67
37.33
1
1
82.66
12 4
82.66
41.33
1
0
0
63.5
95.25
63.5
31.75
0
1
0
1
68.67
103
68.67
34.33
0
1
1
0
72.67
109
72.67
36.33
0
1
1
1
88.66
133
88.66
44.33
1
0
0
0
100
100
66.67
33.33
1
0
0
1
106
106
70.67
35.33
1
0
1
0
112
112
74.67
37.33
1
0
1
1
124
124
82.66
41.33
1
1
0
0
95.25
95.25
63.5
31.75
1
1
0
1
103
103
68.67
34.33
1
1
1
0
109
109
72.67
36.33
1
1
1
1
133
133
88.66
44.33
FS0
(HW)
SEL3
(Bit4)
SEL2
(Bit3)
SEL1
(Bit0)
0
0
0
0
66.67
0
0
0
1
0
0
1
0
0
0
XXXX
Note 1
Bit2
Not used (Needs to be 1 for normal clock operation)
1
Bit1
Not used (Needs to be 1 for normal clock operation)
1
Note1: Default at power-up will be for latched logic inputs to define frequency, as diplayed by Bit 3.
6
ICS9250-10
Preliminary Product Preview
Byte 0: Control Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Pin#
Bit 3
Bit 2
Bit 1
Bit 0
26
25
49
Name
Reserved
Reserved
Reserved
Reserved
SpreadSpectrum
(1=On/0=Off)
48MHz 1
48MHz 0
CPUCLK2
PWD
0
0
0
1
Description
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
1
(Active/Inactive)
1
1
1
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
PWD
1
1
1
1
1
1
1
1
Description
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
PWD
1
1
1
1
1
1
1
0
Description
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
Byte 1: Control Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin#
36
37
39
40
42
43
45
46
Name
SDRAM7
SDRAM6
SDRAM5
SDRAM4
SDRAM3
SDRAM2
SDRAM1
SDRAM0
Byte 2: Control Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin#
20
19
18
16
15
13
12
-
Name
PCICLK7
PCICLK6
PCICLK5
PCICLK4
PCICLK3
PCICLK2
PCICLK1
Reserved
Notes:
1. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be configured
at power-on and are not expected to be configured during the normal modes of operation.
2. PWD = Power on Default
7
ICS9250-10
Preliminary Product Preview
Byte 3: Reserved Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin#
-
Name
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
PWD
0
0
0
0
0
0
0
0
Description
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
PWD
0
0
0
0
0
0
0
0
Description
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
Byte 4: Reserved Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin#
-
Name
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Notes:
1. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be configured
at power-on and are not expected to be configured during the normal modes of operation.
2. PWD = Power on Default
8
ICS9250-10
Preliminary Product Preview
Absolute Maximum Ratings
Core Supply Voltage . . . . . . . . . . . . . . . . . . . . . . 4.6 V
I/O Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . 3.6V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +5%, VDDL=2.5 V+ 5%(unless otherwise stated)
PARAMETER
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Input Low Current
Operating
Supply Current
Power Down
Supply Current
Input frequency
Pin Inductance
Input Capacitance1
Transition Time
Settling Time
1
1
Clk Stabilization1
Delay
1
SYMBOL
VIH
VIL
IIH
IIL1
IIL2
IDD3.3OP
IDD3.3PD
CONDITIONS
VIN = VDD
VIN = 0 V; Inputs with no pull-up resistors
VIN = 0 V; Inputs with pull-up resistors
CL = 0 pF; Select @ 66M
MIN
2
VSS-0.3
-5
-5
-200
CL = 0 pF; With input address to Vdd or GND
TYP
2.0
-100
60
400
MAX UNITS
VDD+0.3
V
0.8
V
µA
5
µA
µA
100
mA
600
µA
7
MHz
nH
5
6
45
pF
pF
pF
Fi
Lpin
VDD = 3.3 V;
14.318
CIN
Cout
CINX
Logic Inputs
Out put pin capacitance
X1 & X2 pins
Ttrans
To 1st crossing of target Freq.
3
mS
Ts
From 1st crossing to 1% target Freq.
3
mS
TSTAB
tPZH,tPZH
tPLZ,tPZH
From VDD = 3.3 V to 1% target Freq.
output enable delay (all outputs)
output disable delay (all outputs)
3
10
10
mS
nS
nS
Guarenteed by design, not 100% tested in production.
9
27
1
1
ICS9250-10
Preliminary Product Preview
Electrical Characteristics - CPU
TA = 0 - 70C, VDDL = 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
Output Impedance
RDSP2B1
RDSN2B1
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
VOH2B
VOL2B
IOH2B
IOL2B
CONDITIONS
MIN
TYP
MAX UNITS
VO = VDD*(0.5)
13.5
45
Ω
VO = VDD*(0.5)
IOH = -1 mA
IOL = 1 mA
VOH @MIN= 1.0V , VOH@ MAX= 2.375V
VOL @MIN= 1.2V , VOL@ MAX= 0.3V
13.5
2
45
-27
27
0.4
-27
30
Ω
V
V
mA
mA
Rise Time
tr2B1
VOL = 0.4 V, VOH = 2.0 V
0.4
1.6
ns
Fall Time
tf2B1
dt2B1
tsk2B1
VOH = 0.4 V, VOL = 2.0 V
0.4
1.6
ns
VT = 1.25 V
45
55
%
VT = 1.25 V
175
ps
VT = 1.25 V
250
ps
Duty Cycle
Skew
tjcyc-cyc1
50
Jitter
1
Guarenteed by design, not 100% tested in production.
Electrical Characteristics - 3V66
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10-30 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
RDSP1
1
VO = VDD*(0.5)
12
55
Ω
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
RDSN1
VOH1
VOL1
IOH1
IOL1
1
VO = VDD*(0.5)
12
IOH = -1 mA
2.4
IOL = 1 mA
VOH@ MIN = 1.0 V, VOH@ MAX = 3.135 V -33
VOL@ MIN = 1.95 V, VOL@ MAX= 0.4
30
55
0.55
-33
38
Ω
V
V
mA
mA
Rise Time
tr11
VOL = 0.4 V, VOH = 2.4 V
0.5
2
ns
Fall Time
1
VOH = 2.4 V, VOL = 0.4 V
0.5
2
ns
1
VT = 1.5 V
45
55
%
1
VT = 1.5 V
VT = 1.5 V
175
500
ps
ps
Output Impedance
Duty Cycle
Skew
Jitter
1
tf1
dt1
tsk1
tjcyc-cyc
Guarenteed by design, not 100% tested in production.
10
ICS9250-10
Preliminary Product Preview
Electrical Characteristics - IOAPIC
TA = 0 - 70C;VDDL = 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
Output Impedance
RDSP4B1
RDSN4B1
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
MIN
TYP
MAX UNITS
VO = VDD*(0.5)
9
30
Ω
VO = VDD*(0.5)
IOH = -5.5 mA
IOL = 9.0 mA
VOH@ min = 1.0 V, VOH@ MAX = 2.375 V
VOL@ MIN = 1.2 V, VOL@ MAX= 0.3V
9
2
30
-27
27
0.4
-27
30
Ω
V
V
mA
mA
Rise Time
tr4B1
VOL = 0.4 V, VOH = 2.0 V
0.4
1.6
ns
Fall Time
tf4B1
VOH = 2.0 V, VOL = 0.4 V
0.4
1.6
ns
Duty Cycle
Jitter
dt4B1
VT = 1.25 V
VT = 1.25 V
45
55
500
%
ps
250
ps
Skew
1
VOH4\B
VOL4B
IOH4B
IOL4B
CONDITIONS
tjcyc-cyc
Tsk41
Guarenteed by design, not 100% tested in production.
Electrical Characteristics - SDRAM
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 20 - 30 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
RDSP3
1
VO = VDD*(0.5)
10
24
Ω
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
RDSN3
VOH3
VOL3
IOH3
IOL3
1
VO = VDD*(0.5)
IOH = -1 mA
IOL = 1 mA
VOH @MIN= 2.0 V, VOH@ MAX=3.135 V
VOL@ MIN= 1.0 V, VOL@ MAX=0.4 V
10
2.4
24
-54
54
0.4
-46
53
Ω
V
V
mA
mA
Rise Time
Tr31
VOL = 0.4 V, VOH = 2.4 V
0.4
1.6
ns
Fall Time
Tf3
1
VOH = 2.4 V, VOL = 0.4 V
0.4
1.6
ns
Dt3
1
VT = 1.5 V
45
55
%
250
250
ps
ps
Output Impedance
Duty Cycle
Skew
Jitter
1
1
Tsk3
tj cyc-cyc
VT = 1.5 V
VT = 1.5 V
Guarenteed by design, not 100% tested in production.
11
ICS9250-10
Preliminary Product Preview
Electrical Characteristics - PCI
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10-30 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
RDSP1
1
VO = VDD*(0.5)
12
55
Ω
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
RDSN1
VOH1
VOL1
IOH1
IOL1
1
VO = VDD*(0.5)
12
IOH = -1 mA
2.4
IOL = 1 mA
VOH@ MIN = 1.0 V, VOH@ MAX = 3.135 V -33
VOL@ MIN = 1.95 V, VOL@ MAX= 0.4
30
55
0.55
-33
38
Ω
V
V
mA
mA
Rise Time
tr11
VOL = 0.4 V, VOH = 2.4 V
0.5
2
ns
Fall Time
1
VOH = 2.4 V, VOL = 0.4 V
0.5
2
ns
1
VT = 1.5 V
45
55
%
1
VT = 1.5 V
VT = 1.5 V
500
500
ps
ps
Output Impedance
Duty Cycle
Skew
Jitter
1
tf1
dt1
tsk1
tjcyc-cyc
Guarenteed by design, not 100% tested in production.
Electrical Characteristics - REF, 48MHz_0 (Pin 25)
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 10 -20 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
RDSP5
1
VO = VDD*(0.5)
20
60
Ω
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
RDSN5
VOH5
VOL5
IOH5
IOL5
1
VO = VDD*(0.5)
IOH = 1 mA
IOL = -1 mA
VOH @MIN=1 V, VOH@MAX= 3.135 V
VOL@MIN=1.95 V, VOL@MIN=0.4 V
20
2.4
60
0.4
-23
27
Ω
V
V
mA
mA
Rise Time
tr51
VOL = 0.4 V, VOH = 2.4 V
1.8
4
ns
Fall Time
1
VOH = 2.4 V, VOL = 0.4 V
1.7
4
ns
1
VT = 1.5 V
55
%
VT = 1.5 V; Fixed Clocks
500
ps
VT = 1.5 V; Ref Clocks
VT = 1.5 V
1000
250
ps
ps
Output Impedance
1
tf5
Duty Cycle
dt5
Jitter
tjcyc-cyc1
tjcyc-cyc1
Skew
Tsk
-29
29
45
Guarenteed by design, not 100% tested in production.
12
ICS9250-10
Preliminary Product Preview
Electrical Characteristics - 48MHz_1 (Pin 26)
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 20 - 30 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
RDSP3
1
VO = VDD*(0.5)
10
24
Ω
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
RDSN3
VOH3
VOL3
IOH3
IOL3
1
VO = VDD*(0.5)
IOH = -1 mA
IOL = 1 mA
VOH @MIN= 2.0 V, VOH@ MAX=3.135 V
VOL@ MIN= 1.0 V, VOL@ MAX=0.4 V
10
2.4
24
-54
54
0.4
-46
53
Ω
V
V
mA
mA
Rise Time
Tr31
VOL = 0.4 V, VOH = 2.4 V
0.4
1.6
ns
Fall Time
Tf3
1
VOH = 2.4 V, VOL = 0.4 V
0.4
1.6
ns
Duty Cycle
Dt3
1
VT = 1.5 V
45
Skew
Jitter
Tsk31
tj cyc-cyc
Output Impedance
1
VT = 1.5 V
VT = 1.5 V
Guarenteed by design, not 100% tested in production.
13
55
%
250
250
ps
ps
ICS9250-10
Preliminary Product Preview
Group Offset Waveforms
Group Skews at Common Transition Edges: (CPU = 66MHz)
CPU & IOAPIC load (lumped) = 20pf; PCI, SDRAM, 3V66 LOAD (LUMPED) = 30pf.
GROUP
SYMBOL
CONDITIONS
MIN
CPU @ 1.25V, 3V66 @ 1.5V
0
CPU to 3V66
SCPU1-3V66
(Note: 180° offset between CPU & 66MHz
CPU @ 1.25V, SDRAM @ 1.5V
0
CPU to SDRAM
SCPU2-SDRAM
(Note: 180° offset between CPU & 66MHz
1.5
3V66 to PCI
S3V66-PCI 3V66 @ 1.5V, PCI @ 1.5V
IOAPIC to PCI
SIOAPIC-PCI IOAPIC @ 1.25V, PCI @1.5V
0
1
TYP
MAX UNITS
500
ps
500
ps
4
500
ns
ps
Guarenteed by design, not 100% tested in production.
Group Skews at Common Transition Edges: (CPU = 100MHz)
CPU & IOAPIC load (lumped) = 20pf; PCI, SDRAM, 3V66 LOAD (LUMPED) = 30pf.
GROUP
SYMBOL
CONDITIONS
MIN
CPU @ 1.25V, 3V66 @ 1.5V
CPU to 3V66
SCPU1-3V66
0
(Note: 180° offset between CPU & 100MHz
CPU @ 1.25V, SDRAM @ 1.5V
CPU to SDRAM
SCPU2-SDRAM
0
(Note: 180° offset between CPU & 100MHz
3V66 to PCI
S3V66-PCI 3V66 @ 1.5V, PCI @ 1.5V
1.5
IOAPIC to PCI
SIOAPIC-PCI IOAPIC @ 1.25V, PCI @1.5V
0
1
Guarenteed by design, not 100% tested in production.
14
TYP
MAX UNITS
500
ps
500
ps
4
500
ns
ps
ICS9250-10
Preliminary Product Preview
General Layout Precautions:
1) Use a ground plane on the top layer of the
PCB in all areas not used by traces.
2) Make all power traces and vias as wide as
possible to lower inductance.
Notes:
1) All clock outputs should have series
terminating resistor. Not shown in all
places to improve readibility of diagram.
2) 47 ohm / 56pf RC termination should be
used on all over 50MHz outputs.
3) Optional crystal load capacitors are
recommended.
Capacitor Values:
C1, C2 : Crystal load values determined by user
C3 : 100pF ceramic
All unmarked capacitors are 0.01µF ceramic
Connections to VDD:
15
ICS9250-10
Preliminary Product Preview
SSOP Package
SYMBOL
A
A1
A2
B
C
D
E
e
H
h
L
N
∝
X
COMMON DIMENSIONS
MIN.
NOM.
MAX.
.095
.101
.110
.008
.012
.016
.088
.090
.092
.008
.010
.0135
.005
.006
.0085
See Variations
.292
.296
.299
0.025 BSC
.400
.406
.410
.010
.013
.016
.024
.032
.040
See Variations
0°
5°
8°
.085
.093
.100
VARIATIONS
AC
AD
MIN.
.620
.720
D
NOM.
.625
.725
N
MAX.
.630
.730
48
56
Ordering Information
ICS9250yF-10
Example:
ICS XXXX y F - PPP
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
16
PRODUCT PREVIEW documents contain information on new
products in the sampling or preproduction phase of development.
Characteristic data and other specifications are subject to change
without notice.