TI TPIC1533

TPIC1533
QUAD AND HEX POWER DMOS ARRAY
SLIS064 – OCTOBER 1996
D
D
D
D
Low rDS(on):
0.1 Ω Typ (Full H-Bridge)
0.22 Ω Typ (Triple Half H-Bridge)
Pulsed Current:
12 A Per Channel (Full H-Bridge)
6 A Per Channel (Triple Half H-Bridge)
Matched Sense Transistors for Class A-B
Linear Operation
Fast Commutation Speed
DW PACKAGE
(TOP VIEW)
OUTPUT3
GND
GATE3B
GATE2B
SENSE
OUTPUT2
GATE4B
GATE2A
GATE5B
VDD2
OUTPUT4
SOURCE
description
1
24
2
23
3
22
4
21
5
20
6
19
7
18
8
17
9
16
10
15
VDD3
GND
GATE3A
GATE1B
GATE2C
OUTPUT1
GATE4A
GATE1A
GATE5A
VDD1
VDD3
OUTPUT5
The TPIC1533 is a monolithic power DMOS array
11
14
that consists of ten electrically isolated N-channel
12
13
enhancement-mode power DMOS transistors, four
of which are configured as a full H-bridge and six as a triple half H-bridge. The lower stage of the full H-bridge
is provided with an integrated sense-FET to allow biasing of the bridge in class A-B operation.
The TPIC1533 is offered in a 24-pin wide-body surface-mount (DW) package and is characterized for operation
over the case temperature range of – 40°C to 125°C.
schematic
VDD1
15
8
GATE2A
Q3A
22
GATE3A
Q4A
18
GATE4A
6
OUTPUT2
1
OUTPUT3
11
OUTPUT4
13
OUTPUT5
Q3B
3
GATE3B
Q4B
7
GATE4B
Q5B
9
GATE5B
Q2A
Q1A
17
GATE1A
19
OUTPUT1
D1
D2
Q1B
21
GATE1B
SENSE
VDD3
14, 24
VDD2
10
Q2B
4
GATE2B
D4
5
Q2C
Q5A
16
GATE5A
D5
D6
D3
12
SOURCE
20
GATE2C
6V
2, 23
GND
NOTES: A. Terminals 2 and 23 must be externally connected.
B. Terminals 14 and 24 must be externally connected.
C. No output may be taken greater than 0.5 V below GND.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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1
TPIC1533
QUAD AND HEX POWER DMOS ARRAY
SLIS064 – OCTOBER 1996
absolute maximum ratings, TC = 25°C (unless otherwise noted)†
Supply-to-GND voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 V
Source-to-GND voltage (Q3A, Q4A, Q5A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 V
Output-to-GND voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 V
Sense-to-GND voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 V
Gate-to-source voltage range, VGS (Q1A, Q1B, Q2A, Q2B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 V
Gate-to-source voltage range, VGS (Q3A, Q3B, Q4A, Q4B, Q5A, Q5B) . . . . . . . . . . . . . . . . . . – 0.3 V to 20 V
Gate-to-source voltage, VGS (Q2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.7 V to 6 V
Continuous gate-to-source zener-diode current (Q2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±10 mA
Pulsed gate-to-source zener-diode current (Q2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous drain current, each output (Q1A, Q1B, Q2A, Q2B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 A
Continuous drain current, each output (Q3A, Q3B, Q4A, Q4B, Q5A, Q5B) . . . . . . . . . . . . . . . . . . . . . . . . 1.5 A
Continuous drain current (Q2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 mA
Continuous source-to-drain diode current (Q1A, Q1B, Q2A, Q2B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 A
Continuous source-to-drain diode current (Q3A, Q3B, Q4A, Q4B, Q5A, Q5B) . . . . . . . . . . . . . . . . . . . . . 1.5 A
Continuous source-to-drain diode current (Q2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 mA
Pulsed drain current, each output, Imax (Q1A, Q1B, Q2A, Q2B) (see Note 1 and Figure 24) . . . . . . . . . 12 A
Pulsed drain current, each output, Imax (Q3A, Q3B, Q4A, Q4B, Q5A, Q5B)
(see Note 1 and Figure 25) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 A
Pulsed drain current, each output, Imax (Q2C) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 mA
Continuous total power dissipation, TC = 70°C (see Note 2 and Figures 24 and 25) . . . . . . . . . . . . . . 2.86 W
Operating virtual junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 150°C
Operating case temperature range, TC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 125°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. Pulse duration = 10 ms, duty cycle = 2%
2. Package mounted in intimate contact with infinite heatsink.
2
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TPIC1533
QUAD AND HEX POWER DMOS ARRAY
SLIS064 – OCTOBER 1996
electrical characteristics, Q1A, Q1B, Q2A, Q2B, TC = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VGS = 0
VDS = VGS,
Gate-to-source threshold voltage
g
ID = 250 µA,
ID = 1 mA,
See Figure 5
VGS(th)match
Gate-to-source threshold voltage matching
ID = 5 mA,
ID = 5 mA,
VDS = VGS
VDS = VGS
V(BR)
Reverse drain-to-GND breakdown voltage
V(BR)GS
V(BR)SG
Gate-to-source breakdown voltage, Q2C
V(BR)DSX
Drain-to-source breakdown voltage
VGS(th)
Source-to-gate breakdown voltage, Q2C
Drain-to-GND current = 250 µA
(D1, D2)
IGS = 100 µA
ISG = 100 µA
VDS(on)
Drain-to-source on-state voltage
ID = 3 A,
See Notes 3 and 4
VF
Forward on-state voltage, GND-to-VDD1,
GND-to-VDD2
ID = 3 A (D1, D2)
See Notes 3 and 4
VF(SD)
on state voltage,
voltage source-to-drain
source to drain
Forward on-state
MIN
TYP
MAX
20
UNIT
V
1.4
1.7
2.1
1.65
1.95
2.35
75
V
mV
20
V
6
V
0.7
V
VGS = 10 V,
0.3
0.36
1.8
V
V
IS = 2 A,
VGS = 0,
See Notes 3 and 4 and Figure 19
1
1.2
IS = 3 A,
VGS = 0,
See Notes 3 and 4 and Figure 19
1.1
1.3
0.05
1
0.5
10
V
IDSS
Zero gate voltage drain current
Zero-gate-voltage
VDS = 16 V,,
VGS = 0
TC = 25°C
TC = 125°C
IGSSF
Forward gate current, drain short-circuited
to source
VGS = 16 V,
VDS = 0
10
100
nA
IGSSR
Reverse gate current, drain short-circuited
to source
VSG = 16 V,
VDS = 0
10
100
nA
Ilk
lkg
Leakage
g current,, VDD1-to-GND,, VDD2-to-GND,,
gate shorted to source
VDGND = 16 V
TC = 25°C
TC = 125°C
0.05
1
0.5
10
VGS = 10 V,
ID = 2 A,,
See Notes 3 and 4
and Figure 9
TC = 25°C
0.1
0.12
TC = 125°C
0.14
0.18
VGS = 10 V,
ID = 3 A,,
See Notes 3 and 4
and Figures 7 and 9
TC = 25°C
0.1
0.12
TC = 125°C
0.14
0.18
VDS = 14 V,
See Notes 3 and 4
ID = 1 A,
rDS(on)
DS( )
gfs
f
Static drain-to-source
drain to source on-state
on state resistance
Forward transconductance
VDS = 14 V,
ID = 1.5 A,
See Notes 3 and 4 and Figure 13
Ciss
Short-circuit input capacitance, common source
Coss
Short-circuit output capacitance, common
source
Crss
Short-circuit reverse transfer capacitance,
common source
αs
Sense-FET drain current ratio
µA
µA
Ω
1.5
2.5
2
3
S
240
VDS = 14 V,
f = 1 MHz
MHz,
170
VGS = 0,
See Figure 17
pF
130
VDS = 6 V,
ID(Q2C) = 40 µA
100
150
200
NOTES: 3. Technique should limit TJ – TC to 10°C maximum.
4. These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts.
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3
TPIC1533
QUAD AND HEX POWER DMOS ARRAY
SLIS064 – OCTOBER 1996
source-to-drain diode characteristics, Q1A, Q2A, TC = 25°C
PARAMETER
trr
Reverse-recovery time
QRR
Total diode charge
trr
QRR
Reverse-recovery time
Total diode charge
TEST CONDITIONS
IS = 1.5 A,
VDS = 14 V,
V
See Figures 1 and 23
VGS = 0,
di/dt = 100 A/µs
A/µs,
IS = 2 A,
VDS = 14V,
VGS = 0,
di/dt = 100 A/µs,
MIN
TYP
MAX
UNIT
70
ns
90
nC
75
ns
110
nC
resistive-load switching characteristics, Q1A, Q1B, Q2A, Q2B, TC = 25°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
td(on)
td(off)
Turn-on delay time
tr
tf
Rise time
Fall time
25
Qg
Total gate charge
5.6
7
0.8
1
1.4
1.7
Turn-off delay time
20
VDD = 14 V,,
tdis = 10 ns,
VDS = 14 V,
V
See Figure 4
RL = 9.1 Ω,,
See Figure 3
ID = 1.5
1 5 A,
A
ten = 10 ns,,
30
VGS = 10 V,
V
Threshold gate-to-source charge
Qgd
Gate-to-drain charge
LD
LS
Internal drain inductance
5
Internal source inductance
5
Rg
Internal gate resistance
0.25
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ns
15
Qgs(th)
4
UNIT
nC
nH
Ω
TPIC1533
QUAD AND HEX POWER DMOS ARRAY
SLIS064 – OCTOBER 1996
electrical characteristics, Q3A, Q3B, Q4A, Q4B, Q5A, Q5B, TC = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
V(BR)DSX
Drain-to-source breakdown voltage
VGS(th)
Gate-to-source threshold voltage
g
ID = 250 µA,
ID = 1 mA,
See Figure 6
V(BR)
Reverse drain-to-GND breakdown voltage
ID = 5 mA,
VDS = VGS
Drain-to-GND current = 250 µA (D3)
VDS(on)
Drain-to-source on-state voltage
ID = 2 A,
See Notes 3 and 4
VF
Forward on-state voltage, GND-to-VDD3
ID = 1.5 A (D3)
See Notes 3 and 4
VF(SD)
on state voltage,
voltage source-to-drain
source to drain
Forward on-state
VGS = 0
VDS = VGS,
VGS = 16 V,
VDS = 0
Ilk
lkg
Leakage
g current,, VDD3-to-GND,, g
gate shorted to
source
VDGND = 16 V
Crss
20
V
V
0.44
0.6
V
V
V
V
0.05
1
0.5
10
10
100
TC = 25°C
TC = 125°C
0.05
1
0.5
10
VGS = 10 V,
ID = 1.5 A,,
See Notes 3 and 4
and Figures 8 and 10
TC = 25°C
0.22
0.3
TC = 125°C
0.32
0.4
VGS = 10 V,
ID = 2 A,,
See Notes 3 and 4
and Figure 10
TC = 25°C
0.22
0.3
TC = 125°C
0.32
0.4
VDS = 14 V,
See Notes 3 and 4
ID = 500 mA,
VDS = 14 V,
ID = 750 mA,
See Notes 3 and 4 and Figure 14
Short-circuit reverse transfer capacitance,
common source
2.35
0.5
Forward gate current, drain short-circuited to
source
Short-circuit output capacitance, common source
1.95
1.3
IGSSF
Coss
1.65
1.1
TC = 25°C
TC = 125°C
Short-circuit input capacitance, common source
2.1
IS = 2 A,
VGS = 0
See Notes 3 and 4 and Figure 20
VDS = 16 V,,
VGS = 0
Ciss
1.7
1.2
Zero gate voltage drain current
Zero-gate-voltage
Forward transconductance
1.4
1
IDSS
UNIT
V
IS = 1.5 A,
VGS = 0
See Notes 3 and 4 and Figure 20
ID = 1 mA (D4, D5, D6)
gfs
f
MAX
1.7
Forward on-state voltage, GND-to-GATE 3A,
GND-to-GATE4A, GND-to GATE5A
Static drain-to-source
drain to source on-state
on state resistance
TYP
20
VGS = 10 V,
VF
rDS(on)
DS( )
MIN
µA
nA
µA
Ω
0.3
0.8
0.4
0.9
S
120
VDS = 14 V,
f = 1 MHz,
VGS = 0,
See Figure 18
140
pF
F
80
NOTES: 3: Technique should limit TJ – TC to 10°C maximum.
4: These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts.
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5
TPIC1533
QUAD AND HEX POWER DMOS ARRAY
SLIS064 – OCTOBER 1996
source-to-drain diode characteristics, Q3A, Q4A, Q5A, TC = 25°C
PARAMETER
trr
Reverse-recovery time
QRR
Total diode charge
trr
QRR
Reverse-recovery time
Total diode charge
TEST CONDITIONS
IS = 750 mA,
VDS = 14 V,
V
See Figures 2 and 23
VGS = 0,
di/dt = 100 A/µs
A/µs,
IS = 2 A,
VDS = 14 V,
VGS = 0,
di/dt = 100 A/µs
MIN
TYP
MAX
UNIT
45
ns
45
nC
70
ns
100
nC
resistive-load switching characteristics, Q3A, Q3B, Q4A, Q4B, Q5A, Q5B, TC = 25°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
td(on)
td(off)
Turn-on delay time
tr
tf
Rise time
Fall time
20
Qg
Total gate charge
2.3
3.1
0.4
0.5
0.6
0.9
UNIT
18
Turn-off delay time
VDD = 14 V,,
tdis = 10 ns,
VDS = 14 V,
V
See Figure 4
RL = 18.7 Ω,,
See Figure 3
ID = 750 mA,
A
25
ten = 10 ns,,
ns
13
VGS = 10 V,
V
Qgs(th)
Threshold gate-to-source charge
Qgd
Gate-to-drain charge
LD
LS
Internal drain inductance
5
Internal source inductance
5
Rg
Internal gate resistance
nC
nH
Ω
0.25
thermal resistance
PARAMETER
TEST CONDITIONS
MIN
TYP
RθJA
Junction-to-ambient thermal resistance
See Notes 5 and 8
90
RθJB
Junction-to-board thermal resistance
See Notes 6 and 8
38
See Notes 7 and 8
28
RθJP Junction-to-pin thermal resistance
NOTES: 5. Package mounted on a FR4 printed-circuit board with no heat sink.
6. Package mounted on a 24 in2, 4-layer FR4 printed-circuit board.
7. Package mounted in intimate contact with infinite heat sink.
8. All outputs with equal power
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MAX
UNIT
°C/W
TPIC1533
QUAD AND HEX POWER DMOS ARRAY
SLIS064 – OCTOBER 1996
PARAMETER MEASUREMENT INFORMATION
3
VDS = 14 V
VGS = 0
TJ = 25°C
Q1A and Q2A
2
I S – Source-to-Drain Diode Current – A
Reverse di/dt = 100 A/µs
1
0
25% of IRM†
–1
Shaded Area = QRR
–2
IRM†
–3
trr(SD)
–4
–5
0
100
200
300
400
500
Time – ns
† IRM = maximum recovery current
Figure 1. Reverse-Recovery-Current Waveform of Source-to-Drain Diodes
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7
TPIC1533
QUAD AND HEX POWER DMOS ARRAY
SLIS064 – OCTOBER 1996
PARAMETER MEASUREMENT INFORMATION
3
VDS = 14 V
VGS = 0
TJ = 25°C
Q3A, Q4A, and Q5A
I S – Source-to-Drain Diode Current – A
2
Reverse di/dt = 100 A/µs
1
0
25% of IRM†
–1
Shaded Area = QRR
IRM†
–2
–3
trr(SD)
–4
–5
0
100
200
300
Time – ns
400
500
† IRM = maximum recovery current
Figure 2. Reverse-Recovery-Current Waveform of Source-to-Drain Diodes
VDD = 14 V
RL
Pulse Generator
ten
VDS
10 V
VGS
VGS
0V
DUT
Rgen
tdis
50 Ω
td(on)
CL 30 pF
(see Note A)
50 Ω
td(off)
tr
tf
VDD
VDS
VDS(on)
VOLTAGE WAVEFORMS
TEST CIRCUIT
NOTE A: CL includes probe and jig capacitance.
Figure 3. Resistive-Switching Test Circuit and Voltage Waveforms
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TPIC1533
QUAD AND HEX POWER DMOS ARRAY
SLIS064 – OCTOBER 1996
PARAMETER MEASUREMENT INFORMATION
Current
Regulator
12-V
Battery
0.2 µF
Qg
Same Type
as DUT
50 kΩ
10 V
0.3 µF
VDS
Qgs(th)
VDD = 14 V
VGS
DUT
IG = 100 µA
0
Qgd
Gate Voltage
Time
IG CurrentSampling Resistor
ID CurrentSampling Resistor
VOLTAGE WAVEFORM
TEST CIRCUIT
Figure 4. Gate-Charge Test Circuit and Voltage Waveform
TYPICAL CHARACTERISTICS
2.5
VDS = VGS
Q1A, Q1B, Q2A, Q2B
2
ID = 5 mA
1.5
ID = 100 µA
1
ID = 1 mA
0.5
0
– 40 – 20
0
20
40
60
80 100 120 140 160
GATE-TO-SOURCE THRESHOLD VOLTAGE
vs
JUNCTION TEMPERATURE
VGS(th) – Gate-to-Source Threshold Voltage – V
VGS(th) – Gate-to-Source Threshold Voltage – V
GATE-TO-SOURCE THRESHOLD VOLTAGE
vs
JUNCTION TEMPERATURE
2.5
ID = 10 mA
2
1.5
ID = 100 µA
1
ID = 1 mA
0.5
VDS = VGS
Q3A, Q3B, Q4A, Q4B, Q5A, Q5B
0
– 40 – 20
TJ – Junction Temperature – °C
0
20
40
60
80 100 120 140 160
TJ – Junction Temperature – °C
Figure 5
Figure 6
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9
TPIC1533
QUAD AND HEX POWER DMOS ARRAY
SLIS064 – OCTOBER 1996
TYPICAL CHARACTERISTICS
STATIC DRAIN-TO-SOURCE
ON-STATE RESISTANCE
vs
JUNCTION TEMPERATURE
STATIC DRAIN-TO-SOURCE
ON-STATE RESISTANCE
vs
JUNCTION TEMPERATURE
0.175
ID = 1.5 A
Q3A, Q3B, Q4A, Q4B, Q5A, Q5B
On-State Resistance – Ω
VGS = 10 V
0.125
VGS = 15 V
0.100
0.075
VGS = 12 V
0.050
0.5
On-State Resistance – Ω
r DS(on) – Static Drain-to-Source
r DS(on) – Static Drain-to-Source
0.150
0.6
ID = 3 A
Q1A, Q1B, Q2A, Q2B
0.025
0
– 40 – 20
0
20
40
60
0.4
VGS = 10 V
0.3
0.2
VGS = 15 V
VGS = 12 V
0.1
0
– 40 – 20
80 100 120 140 160
TJ – Junction Temperature – °C
60
80 100 120 140 160
STATIC DRAIN-TO-SOURCE
ON-STATE RESISTANCE
vs
DRAIN CURRENT
0.26
10
TJ = 25°C
Q1A, Q1B, Q2A, Q2B
0.24
VGS = 10 V
VGS = 15 V
VGS = 12 V
TJ = 25°C
Q3A, Q3B, Q4A
Q4B, Q5A, Q5B
VGS = 10 V
0.22
On-State Resistance – Ω
r DS(on) – Static Drain-to-Source
On-State Resistance – Ω
40
Figure 8
STATIC DRAIN-TO-SOURCE
ON-STATE RESISTANCE
vs
DRAIN CURRENT
r DS(on) – Static Drain-to-Source
20
TJ – Junction Temperature – °C
Figure 7
0.1
0
0.2
VGS = 12 V
0.18
VGS = 16 V
0.16
0.14
0.12
0.01
0.01
0.1
1
10
ID – Drain Current – A
100
0.1
0.1
Figure 9
10
1
ID – Drain Current – A
Figure 10
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TPIC1533
QUAD AND HEX POWER DMOS ARRAY
SLIS064 – OCTOBER 1996
TYPICAL CHARACTERISTICS
DRAIN CURRENT
vs
DRAIN-TO-SOURCE VOLTAGE
DRAIN CURRENT
vs
GATE-TO-SOURCE VOLTAGE
12
5
VGS = 5 V
I D – Drain Current – A
10
8
6
VGS = 4 V
4
VGS = 3 V
2
1
3
VGS = 4 V
2
VGS = 3 V
1
0
0
∆VGS = 1 V
(unless otherwise noted)
TJ = 25°C
Q3A, Q3B, Q4A, Q4B,
Q5A, Q5B
4
2
3
4
5
6
7
8
9
VDS – Drain-to-Source Voltage – V
0
10
0
7
8
9
2
3
4
5
6
VGS – Gate-to-Source Voltage – V
1
Figure 11
DISTRIBUTION OF
FORWARD TRANSCONDUCTANCE
DISTRIBUTION OF
FORWARD TRANSCONDUCTANCE
40
gfs – Forward Transconductance – S
0.94
0.93
0.92
0.91
0.90
3.3
3.2
3.1
3
2.9
2.8
2.7
2.6
0
2.5
0
2.4
10
2.3
10
0.89
20
0.87
20
30
Total Number of Units = 1200
VDS = 14 V
TJ = 25°C
ID = 750 mA
Q3A, Q3B, Q4A,
Q4B, Q5A, Q5B
0.86
Percentage of Units – %
Total Number of Units = 1200
VDS = 14 V
TJ = 25°C
ID = 1.5 A
Q1A, Q1B, Q2A, Q2B
2.2
Percentage of Units – %
40
30
10
Figure 12
0.88
I D – Drain Current – A
6
∆VGS = 0.5 V
(unless otherwise noted)
TJ = 25°C
Q1A, Q1B, Q2A, Q2B
gfs – Forward Transconductance – S
Figure 13
Figure 14
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TPIC1533
QUAD AND HEX POWER DMOS ARRAY
SLIS064 – OCTOBER 1996
TYPICAL CHARACTERISTICS
DRAIN CURRENT
vs
GATE-TO-SOURCE VOLTAGE
DRAIN CURRENT
vs
GATE-TO-SOURCE VOLTAGE
12
6
TJ = – 40°C
11
Q3A, Q3B, Q4A, Q4B,
Q5A, Q5B
TJ = 25°C
10
5
TJ = – 40°C
TJ = 125°C
8
I D – Drain Current – A
I D – Drain Current – A
9
7
Q1A, Q1B, Q2A, Q2B
6
5
4
3
2
4
TJ = 25°C
3
TJ = 125°C
2
1
1
0
0
1
2
3
4
5
0
6
0
1
VGS – Gate-to-Source Voltage – V
2
3
Figure 15
8
7
320
VGS = 0
f = 1 MHz
TJ = 25°C
Q1A, Q1B,
Q2A, Q2B
450
400
290
VGS = 0
f = 1 MHz
TJ = 25°C
Q3A, Q3B, Q4A,
Q4B, Q5A, Q5B
260
230
Capacitance – pF
350
300
Ciss
Coss
200
6
CAPACITANCE
vs
DRAIN-TO-SOURCE VOLTAGE
500
250
5
Figure 16
CAPACITANCE
vs
DRAIN-TO-SOURCE VOLTAGE
Capacitance – pF
4
VGS – Gate-to-Source Voltage – V
200
170
Coss
140
Ciss
110
Crss
150
Crss
80
100
50
50
0
2
4
6
8
10
12
14
16
20
0
2
VDS – Drain-to-Source Voltage – V
6
8
10
Figure 18
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12
14
16
VDS – Drain-to-Source Voltage – V
Figure 17
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4
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20
TPIC1533
QUAD AND HEX POWER DMOS ARRAY
SLIS064 – OCTOBER 1996
TYPICAL CHARACTERISTICS
SOURCE-TO-DRAIN DIODE CURRENT
vs
SOURCE-TO-DRAIN VOLTAGE
SOURCE-TO-DRAIN DIODE CURRENT
vs
SOURCE-TO-DRAIN VOLTAGE
10
VGS = 0
Q1A, Q1B, Q2A, Q2B
6
I SD – Source-to-Drain Diode Current – A
4
2
1
0.6
TJ = 125°C
TJ = – 40°C
0.4
TJ = 150°C
TJ = 25°C
0.2
TJ = 75°C
0.1
VGS = 0
Q3A, Q3B, Q4A, Q4B,
Q5A, Q5B
6
4
2
1
0.6
TJ = 125°C
TJ = 150°C
TJ = 25°C
0.2
TJ = 75°C
0.1
0.1
10
1
VSD – Source-to-Drain Voltage – V
0.1
Figure 20
DRAIN-TO-SOURCE VOLTAGE AND
GATE-TO-SOURCE VOLTAGE
vs
GATE CHARGE
DRAIN-TO-SOURCE VOLTAGE AND
GATE-TO-SOURCE VOLTAGE
vs
GATE CHARGE
ID = 1.5 A
TJ = 25°C
Q1A, Q1B, Q2A, Q2B
See Figure 4
14
12
16
16
14
14
12
VDD = 10 V
10
10
8
8
VDD = 12 V
6
6
4
4
VDD = 14 V
2
2
VDD = 12 V
0
VGS – Gate-to-Source Voltage – V
VDS – Drain-to-Source Voltage – V
16
0
0
1
2
3
4
5
6
10
1
VSD – Source-to-Drain Voltage – V
Figure 19
VDS – Drain-to-Source Voltage – V
TJ = – 40°C
0.4
7
8
9
10
ID = 750 mA
TJ = 25°C
See Figure 4
Q3A, Q3B,
Q4A, Q4B,
Q5A, Q5B
12
VDD = 10 V
10
16
14
12
10
VDD = 12 V
8
8
VDD = 14 V
6
6
VDD = 12 V
4
VDD = 14 V
2
0
0
0.25 0.5 0.75
Qg – Gate Charge – nC
1
1.25 1.5 1.75
4
2
VGS – Gate-to-Source Voltage – V
I SD – Source-to-Drain Diode Current – A
10
0
2 2.25 2.5
Qg – Gate Charge – nC
Figure 22
Figure 21
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13
TPIC1533
QUAD AND HEX POWER DMOS ARRAY
SLIS064 – OCTOBER 1996
TYPICAL CHARACTERISTICS
REVERSE RECOVERY TIME
vs
REVERSE di/dt
trr – Reverse Recovery Time – ns
100
TJ = 25°C
See Figures 1 and 2
80
IS = 1.5 A
Q1A, Q1B
60
40
IS = 750 mA
Q3A, Q4A, Q5A
20
0
0
100
200
300
400
Reverse di/dt – A/µs
Figure 23
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TPIC1533
QUAD AND HEX POWER DMOS ARRAY
SLIS064 – OCTOBER 1996
THERMAL INFORMATION
MAXIMUM DRAIN CURRENT
vs
DRAIN-TO-SOURCE VOLTAGE
100
I D – Maximum Drain Current – A
TC = 25°C
Q1A, Q1B, Q2A, Q2B
ÁÁ
ÁÁ
500 µs†
10
10 ms¶
1 ms†
1
θJC§
θJA‡
DC Conditions
0.1
0.1
1
10
100
VDS – Drain-to-Source Voltage – V
Figure 24
MAXIMUM DRAIN CURRENT
vs
DRAIN-TO-SOURCE VOLTAGE
100
I D – Maximum Drain Current – A
TC = 25°C
Q3A, Q3B, Q4A, Q4B, Q5A, Q5B
ÁÁ
ÁÁ
10
500 µs
10 ms¶
1 ms†
1
θJC§
θJA‡
DC Conditions
0.1
0.1
1
10
100
VDS – Drain-to-Source Voltage – V
Figure 25
† Less than 10% duty cycle
‡ Device is mounted on FR4 printed-circuit board with no heat sink.
§ Device is mounted in intimate contact with infinite heat sink.
¶ Less than 2% duty cycle
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TPIC1533
QUAD AND HEX POWER DMOS ARRAY
SLIS064 – OCTOBER 1996
THERMAL INFORMATION
DW PACKAGE†
JUNCTION-TO-BOARD THERMAL RESISTANCE
vs
PULSE DURATION
100
RθJB – Junction-to-Board Thermal Resistance – °C/W
DC Conditions
d = 0.5
10
d = 0.2
d = 0.1
d = 0.05
d = 0.02
1
d = 0.01
tc
tw
Single Pulse
ID
0
0.1
0.0001
0.001
0.01
0.1
tw – Pulse Duration – s
† Device mounted on 24 in2, 4 layer FR4 printed-circuit board with no heat sink.
NOTE A: ZθB(t) = r(t) RθJB
tw = pulse duration
tc = cycle time
d = duty cycle = tw/tc
Figure 26
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10
100
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