ETC LH28F800BVE-TV85

PRODUCT SPECIFICATIONS
®
Integrated Circuits Group
LH28F800BVE-TV85
Flash Memory
8M (1MB × 8/512K × 16)
(Model No.: LHF80V25)
Spec No.: EL109061B
Issue Date: September 16, 1999
sharp
LHF80V25
●Handle this document carefully for it contains material protected by international copyright law.
Any reproduction, full or in part, of this material is prohibited without the express written
permission of the company.
●When using the products covered herein, please observe the conditions written herein and the
precautions outlined in the following paragraphs. In no event shall the company be liable for any
damages resulting from failure to strictly adhere to these conditions and precautions.
(1) The products covered herein are designed and manufactured for the following application
areas. When using the products covered herein for the equipment listed in Paragraph (2),
even for the following application areas, be sure to observe the precautions given in
Paragraph (2). Never use the products for the equipment listed in Paragraph (3).
•Office electronics
•Instrumentation and measuring equipment
•Machine tools
•Audiovisual equipment
•Home appliance
•Communication equipment other than for trunk lines
(2) Those contemplating using the products covered herein for the following equipment which
demands high reliability, should first contact a sales representative of the company and then
accept responsibility for incorporating into the design fail-safe operation, redundancy, and
other appropriate measures for ensuring reliability and safety of the equipment and the
overall system.
•Control and safety devices for airplanes, trains, automobiles, and other
transportation equipment
•Mainframe computers
•Traffic control systems
•Gas leak detectors and automatic cutoff devices
•Rescue and security equipment
•Other safety devices and safety equipment, etc.
(3) Do not use the products covered herein for the following equipment which demands
extremely high performance in terms of functionality, reliability, or accuracy.
•Aerospace equipment
•Communications equipment for trunk lines
•Control equipment for the nuclear power industry
•Medical equipment related to life support, etc.
(4) Please direct all queries and comments regarding the interpretation of the above three
Paragraphs to a sales representative of the company.
●Please direct all queries regarding the products covered herein to a sales representative of the
company.
Rev. 1.1
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LHF80V25
1
CONTENTS
PAGE
PAGE
1 INTRODUCTION.............................................................. 3
5 DESIGN CONSIDERATIONS ...................................... 20
1.1 Features ........................................................................ 3
5.1 Three-Line Output Control ....................................... 20
1.2 Product Overview......................................................... 3
5.2 RY/BY# and Block Erase and Word/Byte Write
Polling...................................................................... 20
2 PRINCIPLES OF OPERATION........................................ 7
5.3 Power Supply Decoupling ........................................ 20
2.1 Data Protection............................................................. 8
5.4 VPP Trace on Printed Circuit Boards ........................ 20
5.5 VCC, VPP, RP# Transitions ....................................... 21
3 BUS OPERATION ............................................................ 8
5.6 Power-Up/Down Protection...................................... 21
3.1 Read.............................................................................. 8
5.7 Power Dissipation ..................................................... 21
3.2 Output Disable.............................................................. 8
3.3 Standby......................................................................... 8
6 ELECTRICAL SPECIFICATIONS ............................... 22
3.4 Deep Power-Down ....................................................... 8
6.1 Absolute Maximum Ratings ..................................... 22
3.5 Read Identifier Codes Operation .................................. 9
6.2 Operating Conditions ................................................ 22
3.6 Write............................................................................. 9
6.2.1 Capacitance ......................................................... 22
6.2.2 AC Input/Output Test Conditions ....................... 23
4 COMMAND DEFINITIONS............................................. 9
6.2.3 DC Characteristics .............................................. 24
4.1 Read Array Command................................................ 12
6.2.4 AC Characteristics - Read-Only Operations ....... 26
4.2 Read Identifier Codes Command ............................... 12
6.2.5 AC Characteristics - Write Operations ............... 29
4.3 Read Status Register Command ................................. 12
6.2.6 Alternative CE#-Controlled Writes..................... 31
4.4 Clear Status Register Command................................. 12
6.2.7 Reset Operations ................................................. 33
4.5 Block Erase Command............................................... 12
6.2.8 Block Erase and Word/Byte Write Performance 34
4.6 Word/Byte Write Command....................................... 13
4.7 Block Erase Suspend Command ................................ 13
7 PACKAGE AND PACKING SPECIFICATIONS......... 35
4.8 Word/Byte Write Suspend Command ........................ 14
4.9 Considerations of Suspend ......................................... 14
4.10 Block Locking .......................................................... 14
4.10.1 VPP=VIL for Complete Protection ...................... 14
4.10.2 WP#=VIL for Block Locking.............................. 14
4.10.3 WP#=VIH for Block Unlocking.......................... 14
Rev. 1.1
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LHF80V25
2
LH28F800BVE-TV85
8M-BIT (1Mbit × 8 / 512Kbit × 16)
Smart5 Flash MEMORY
■ Smart5 Technology
4.5V-5.5V VCC
4.5V-5.5V or 11.4V-12.6V VPP
■ User-Configurable ×8 or ×16 Operation
■ High-Performance Access Time
85ns(4.5V-5.5V)
■ Operating Temperature
0°C to +70°C
■ Optimized Array Blocking Architecture
Two 4K-word Boot Blocks
Six 4K-word Parameter Blocks
Fifteen 32K-word Main Blocks
Top Boot Location
■ Extended Cycling Capability
100,000 Block Erase Cycles
■ Enhanced Automated Suspend Options
Word/Byte Write Suspend to Read
Block Erase Suspend to Word/Byte Write
Block Erase Suspend to Read
■ Enhanced Data Protection Features
Absolute Protection with VPP=GND
Block Erase and Word/Byte Write Lockout
during Power Transitions
Boot Blocks Protection with WP#=VIL
■ Automated Word/Byte Write and Block Erase
Command User Interface
Status Register
■ Low Power Management
Deep Power-Down Mode
Automatic Power Savings Mode Decreases
ICC in Static Mode
■ SRAM-Compatible Write Interface
■ Industry-Standard Packaging
48-Lead TSOP
■ ETOXTM* Nonvolatile Flash Technology
■ CMOS Process (P-type silicon substrate)
■ Not designed or rated as radiation hardened
SHARP’s LH28F800BVE-TV85 Flash memory with Smart5 technology is a high-density, low-cost, nonvolatile, read/write
storage solution for a wide range of applications. LH28F800BVE-TV85 can operate at VCC=4.5V-5.5V and VPP=4.5V-5.5V.
Its low voltage operation capability realize battery life and suits for cellular phone application.
Its Boot, Parameter and Main-blocked architecture, flexible voltage and extended cycling provide for highly flexible
component suitable for portable terminals and personal computers. Its enhanced suspend capabilities provide for an ideal
solution for code + data storage applications. For secure code storage applications, such as networking, where code is either
directly executed out of flash or downloaded to DRAM, the LH28F800BVE-TV85 offers two levels of protection: absolute
protection with VPP at GND, selective hardware boot block locking. These alternatives give designers ultimate control of their
code security needs.
The LH28F800BVE-TV85 is manufactured on SHARP’s 0.35µm ETOXTM* process technology. It come in industry-standard
package: the 48-lead TSOP ideal for board constrained applications.
*ETOX is a trademark of Intel Corporation.
Rev. 1.1
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LHF80V25
1 INTRODUCTION
This datasheet contains LH28F800BVE-TV85
specifications. Section 1 provides a flash memory
overview. Sections 2, 3, 4 and 5 describe the memory
organization and functionality. Section 6 covers electrical
specifications.
1.1 Features
Key enhancements of LH28F800BVE-TV85 Smart5 Flash
memory are:
•Smart5 Technology
•Enhanced Suspend Capabilities
•Boot Block Architecture
Please note following important differences:
•VPPLK has been lowered to 1.5V to support 4.5V-5.5V
block erase and word/byte write operations. The VPP
voltage transitions to GND is recommended for
designs that switch VPP off during read operation.
•To take advantage of Smart5 technology, allow VCC
and VPP connection to 4.5V-5.5V.
1.2 Product Overview
The LH28F800BVE-TV85 is a high-performance 8M-bit
Smart5 Flash memory organized as 1M-byte of 8 bits or
512K-word of 16 bits. The 1M-byte/512K-word of data is
arranged in two 8K-byte/4K-word boot blocks, six 8Kbyte/4K-word parameter blocks and fifteen 64K-byte/32Kword main blocks which are individually erasable insystem. The memory map is shown in Figure 3.
3
eliminates the need for a separate 12V converter, while
VPP=12V maximizes block erase and word/byte write
performance. In addition to flexible erase and program
voltages, the dedicated VPP pin gives complete data
protection when VPP≤VPPLK.
Table 1. VCC and VPP Voltage Combinations Offered by
Smart5 Technology
VCC Voltage
VPP Voltage
4.5V-5.5V
4.5V-5.5V, 11.4V-12.6V
Internal VCC and VPP detection Circuitry automatically
configures the device for optimized read and write
operations.
A Command User Interface (CUI) serves as the interface
between the system processor and internal operation of the
device. A valid command sequence written to the CUI
initiates device automation. An internal Write State
Machine (WSM) automatically executes the algorithms
and timings necessary for block erase and word/byte write
operations.
A block erase operation erases one of the device’s 32Kword blocks typically within 0.39s (5V VCC, 12V VPP),
4K-word blocks typically within 0.25s (5V VCC, 12V
VPP) independent of other blocks. Each block can be
independently erased 100,000 times. Block erase suspend
mode allows system software to suspend block erase to
read or write data from any other block.
Writing memory data is performed in word/byte
increments of the device’s 32K-word blocks typically
within 8.4µs (5V VCC, 12V VPP), 4K-word blocks
typically within 17µs (5V VCC, 12V VPP). Word/byte
write suspend mode enables the system to read data or
execute code from any other flash memory array location.
Smart5 technology provides a choice of VCC and VPP
combinations, as shown in Table 1, to meet system
performance and power expectations. VPP at 4.5V-5.5V
Rev. 1.2
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LHF80V25
The boot blocks can be locked for the WP# pin. Block
erase or word/byte write for boot block must not be carried
out by WP# to Low and RP# to VIH.
The status register indicates when the WSM’s block erase
or word/byte write operation is finished.
The RY/BY# output gives an additional indicator of WSM
activity by providing both a hardware signal of status
(versus software polling) and status masking (interrupt
masking for background block erase, for example). Status
polling using RY/BY# minimizes both CPU overhead and
system power consumption. When low, RY/BY# indicates
that the WSM is performing a block erase or word/byte
write. RY/BY#-high Z indicates that the WSM is ready for
a new command, block erase is suspended (and word/byte
write is inactive), word/byte write is suspended, or the
device is in deep power-down mode.
4
The Automatic Power Savings (APS) feature substantially
reduces active current when the device is in static mode
(addresses not switching). In APS mode, the typical ICCR
current is 1mA at 5V VCC.
When CE# and RP# pins are at VCC, the ICC CMOS
standby mode is enabled. When the RP# pin is at GND,
deep power-down mode is enabled which minimizes
power consumption and provides write protection during
reset. A reset time (tPHQV) is required from RP# switching
high until outputs are valid. Likewise, the device has a
wake time (tPHEL) from RP#-high until writes to the CUI
are recognized. With RP# at GND, the WSM is reset and
the status register is cleared.
The device is available in 48-lead TSOP (Thin Small
Outline Package, 1.2 mm thick). Pinout is shown in Figure
2.
The access time is 85ns (tAVQV) over the commercial
temperature range (0°C to +70°C) and VCC supply voltage
range of 4.5V-5.5V.
Rev. 1.2
LHF80V25
sharp
5
DQ0-DQ15
Input
Buffer
Output
Buffer
I/O
Logic
Status
Register
Data
Register
Output
Multiplexer
Identifier
Register
A-1
BYTE#
VCC
CE#
WE#
OE#
RP#
WP#
Command
User
Interface
Data
Comparator
Main blocks
RY/BY#
Program/Erase
Voltage Switch
Main Block 14
15
32K-Word
Main Block 13
X
Decoder
Write
State
Machine
Y-Gating
Main Block 1
Address
Latch
Y
Decoder
Main Block 0
Input
Buffer
Boot Block 0
Boot Block 1
Parameter Block 0
Parameter Block 1
Parameter Block 2
Parameter Block 3
Parameter Block 4
Parameter Block 5
A0-A18
VPP
VCC
GND
Address
Counter
Figure 1. Block Diagram
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE#
RP#
VPP
WP#
RY/BY#
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48-LEAD TSOP
STANDARD PINOUT
12mm x 20mm
TOP VIEW
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
BYTE#
GND
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
GND
CE#
A0
Figure 2. TSOP 48-Lead Pinout
Rev. 1.1
sharp
Symbol
A-1
A0-A18
DQ0-DQ15
CE#
RP#
OE#
WE#
WP#
BYTE#
RY/BY#
VPP
LHF80V25
6
Table 2. Pin Descriptions
Name and Function
ADDRESS INPUTS: Addresses are internally latched during a write cycle.
A-1
: Byte Select Address. Not used in ×16 mode.
INPUT A0-A10 : Row Address. Selects 1 of 2048 word lines.
A11-A14 : Column Address. Selects 1 of 16 bit lines.
A15-A18 : Main Block Address. (Boot and Parameter block Addresses are A12-A18.)
DATA INPUT/OUTPUTS:
DQ0-DQ7:Inputs data and commands during CUI write cycles; outputs data during memory array,
status register and identifier code read cycles. Data pins float to high-impedance when the chip is
INPUT/ deselected or outputs are disabled. Data is internally latched during a write cycle.
OUTPUT DQ8-DQ15:Inputs data during CUI write cycles in ×16 mode; outputs data during memory array
read cycles in ×16 mode; not used for status register and identifier code read mode. Data pins float
to high-impedance when the chip is deselected, outputs are disabled, or in ×8 mode (Byte#=VIL).
Data is internally latched during a write cycle.
CHIP ENABLE: Activates the device’s control logic, input buffers, decoders and sense amplifiers.
INPUT
CE#-high deselects the device and reduces power consumption to standby levels.
RESET/DEEP POWER-DOWN: Puts the device in deep power-down mode and resets internal
automation. RP#-high enables normal operation. When driven low, RP# inhibits write operations
which provides data protection during power transitions. Exit from deep power-down sets the
INPUT
device to read array mode. With RP#=VHH, block erase or word/byte write can operate to all
blocks without WP# state. Block erase or word/byte write with VIH<RP#<VHH produce spurious
results and should not be attempted.
INPUT OUTPUT ENABLE: Gates the device’s outputs during a read cycle.
WRITE ENABLE: Controls writes to the CUI and array blocks. Addresses and data are latched on
INPUT
the rising edge of the WE# pulse.
WRITE PROTECT: Master control for boot blocks locking. When VIL, locked boot blocks cannot
INPUT
be erased and programmed.
BYTE ENABLE: BYTE# VIL places device in ×8 mode. All data is then input or output on DQ0-7,
INPUT
and DQ8-15 float. BYTE# VIH places the device in ×16 mode , and turns off the A-1 input buffer.
READY/BUSY#: Indicates the status of the internal WSM. When low, the WSM is performing an
OPEN
internal operation (block erase or word/byte write). RY/BY#-high Z indicates that the WSM is
DRAIN
ready for new commands, block erase is suspended, and word/byte write is inactive, word/byte
OUTPUT
write is suspended, or the device is in deep power-down mode.
BLOCK ERASE AND WORD/BYTE WRITE POWER SUPPLY: For erasing array blocks or
writing words/bytes. With VPP≤VPPLK, memory contents cannot be altered. Block erase and
SUPPLY
word/byte write with an invalid VPP (see DC Characteristics) produce spurious results and should
not be attempted.
Type
VCC
SUPPLY
GND
NC
SUPPLY
DEVICE POWER SUPPLY: Do not float any power pins. With VCC≤VLKO, all write attempts to
the flash memory are inhibited. Device operations at invalid VCC voltage (see DC Characteristics)
produce spurious results and should not be attempted.
GROUND: Do not float any ground pins.
NO CONNECT: Lead is not internal connected; it may be driven or floated.
Rev. 1.1
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LHF80V25
7
2 PRINCIPLES OF OPERATION
[A18-A0]
The LH28F800BVE-TV85 Smart5 Flash memory includes
an on-chip WSM to manage block erase and word/byte
write functions. It allows for: 100% TTL-level control
inputs, fixed power supplies during block erasure and
word/byte write, and minimal processor overhead with
RAM-like interface timings.
After initial device power-up or return from deep powerdown mode (see Bus Operations), the device defaults to
read array mode. Manipulation of external memory control
pins allow array read, standby and output disable
operations.
Status register and identifier codes can be accessed
through the CUI independent of the VPP voltage. High
voltage on VPP enables successful block erasure and
word/byte writing. All functions associated with altering
memory contents−block erase, word/byte write, status and
identifier codes−are accessed via the CUI and verified
through the status register.
Commands are written using standard microprocessor
write timings. The CUI contents serve as input to the
WSM, which controls the block erase and word/byte write.
The internal algorithms are regulated by the WSM,
including pulse repetition, internal verification and
margining of data. Addresses and data are internally latch
during write cycles. Writing the appropriate command
outputs array data, accesses the identifier codes or outputs
status register data.
Interface software that initiates and polls progress of block
erase and word/byte write can be stored in any block. This
code is copied to and executed from system RAM during
flash memory updates. After successful completion, reads
are again possible via the Read Array command. Block
erase suspend allows system software to suspend a block
erase to read/write data from/to blocks other than that
which is suspend. Word/byte write suspend allows system
software to suspend a word/byte write to read data from
any other flash memory array location.
Top Boot
7FFFF
7F000
7EFFF
7E000
7DFFF
7D000
7CFFF
7C000
7BFFF
7B000
7AFFF
7A000
79FFF
79000
78FFF
78000
77FFF
70000
6FFFF
68000
67FFF
60000
5FFFF
58000
57FFF
50000
4FFFF
48000
47FFF
40000
3FFFF
38000
37FFF
30000
2FFFF
28000
27FFF
20000
1FFFF
18000
17FFF
10000
0FFFF
08000
07FFF
00000
4K-word Boot Block
0
4K-word Boot Block
1
4K-word Parameter Block
0
4K-word Parameter Block
1
4K-word Parameter Block
2
4K-word Parameter Block
3
4K-word Parameter Block
4
4K-word Parameter Block
5
32K-word Main Block
0
32K-word Main Block
1
32K-word Main Block
2
32K-word Main Block
3
32K-word Main Block
4
32K-word Main Block
5
32K-word Main Block
6
32K-word Main Block
7
32K-word Main Block
8
32K-word Main Block
9
32K-word Main Block
10
32K-word Main Block
11
32K-word Main Block
12
32K-word Main Block
13
32K-word Main Block
14
Figure 3. Memory Map
Rev. 1.1
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LHF80V25
8
2.1 Data Protection
3.2 Output Disable
Depending on the application, the system designer may
choose to make the VPP power supply switchable
(available only when memory block erases or word/byte
writes are required) or hardwired to VPPH1/2. The device
accommodates either design practice and encourages
optimization of the processor-memory interface.
With OE# at a logic-high level (VIH), the device outputs
are disabled. Output pins (DQ0-DQ15) are placed in a
high-impedance state.
When VPP≤VPPLK, memory contents cannot be altered.
The CUI, with two-step block erase or word/byte write
command sequences, provides protection from unwanted
operations even when high voltage is applied to VPP. All
write functions are disabled when VCC is below the write
lockout voltage VLKO or when RP# is at VIL. The device’s
boot blocks locking capability for WP# provides
additional protection from inadvertent code or data
alteration by block erase and word/byte write operations.
Refer to Table 6 for write protection alternatives.
3 BUS OPERATION
The local CPU reads and writes flash memory in-system.
All bus cycles to or from the flash memory conform to
standard microprocessor bus cycles.
3.1 Read
Information can be read from any block, identifier codes
or status register independent of the VPP voltage. RP# can
be at either VIH or VHH.
The first task is to write the appropriate read mode
command (Read Array, Read Identifier Codes or Read
Status Register) to the CUI. Upon initial device power-up
or after exit from deep power-down mode, the device
automatically resets to read array mode. Six control pins
dictate the data flow in and out of the component: CE#,
OE#, WE#, RP#, WP# and BYTE#. CE# and OE# must be
driven active to obtain data at the outputs. CE# is the
device selection control, and when active enables the
selected memory device. OE# is the data output
(DQ0-DQ15) control and when active drives the selected
memory data onto the I/O bus. WE# must be at VIH and
RP# must be at VIH or VHH. Figure 11, 12 illustrates read
cycle.
3.3 Standby
CE# at a logic-high level (VIH) places the device in
standby mode which substantially reduces device power
consumption. DQ0-DQ15 outputs are placed in a highimpedance state independent of OE#. If deselected during
block erase or word/byte write, the device continues
functioning, and consuming active power until the
operation completes.
3.4 Deep Power-Down
RP# at VIL initiates the deep power-down mode.
In read modes, RP#-low deselects the memory, places
output drivers in a high-impedance state and turns off all
internal circuits. RP# must be held low for a minimum of
100 ns. Time tPHQV is required after return from powerdown until initial memory access outputs are valid. After
this wake-up interval, normal operation is restored. The
CUI is reset to read array mode and status register is set to
80H.
During block erase or word/byte write modes, RP#-low
will abort the operation. RY/BY# remains low until the
reset operation is complete. Memory contents being
altered are no longer valid; the data may be partially
erased or written. Time tPHWL is required after RP# goes
to logic-high (VIH) before another command can be
written.
As with any automated device, it is important to assert
RP# during system reset. When the system comes out of
reset, it expects to read from the flash memory. Automated
flash memories provide status information when accessed
during block erase or word/byte write modes. If a CPU
reset occurs with no flash memory reset, proper CPU
initialization may not occur because the flash memory
may be providing status information instead of array data.
SHARP’s flash memories allow proper CPU initialization
following a system reset through the use of the RP# input.
In this application, RP# is controlled by the same RESET#
signal that resets the system CPU.
Rev. 1.1
LHF80V25
sharp
9
3.5 Read Identifier Codes Operation
3.6 Write
The read identifier codes operation outputs the
manufacturer code and device code (see Figure 4). Using
the manufacturer and device codes, the system CPU can
automatically match the device with its proper algorithms.
Writing commands to the CUI enable reading of device
data and identifier codes. They also control inspection and
clearing of the status register. When VCC=4.5V-5.5V and
VPP=VPPH1/2, the CUI additionally controls block erasure
and word/byte write.
[A18-A0]
The Block Erase command requires appropriate command
data and an address within the block to be erased. The
Word/Byte Write command requires the command and
address of the location to be written.
7FFFF
Reserved for Future Implementation
00002
00001
Device Code
00000
Manufacturer Code
The CUI does not occupy an addressable memory
location. It is written when WE# and CE# are active. The
address and data needed to execute a command are latched
on the rising edge of WE# or CE# (whichever goes high
first). Standard microprocessor write timings are used.
Figures 13 and 14 illustrate WE# and CE# controlled write
operations.
4 COMMAND DEFINITIONS
Figure 4. Device Identifier Code Memory Map
When the VPP voltage ≤ VPPLK, Read operations from the
status register, identifier codes, or blocks are enabled.
Placing VPPH1/2 on VPP enables successful block erase
and word/byte write operations.
Device operations are selected by writing specific
commands into the CUI. Table 4 defines these commands.
Rev. 1.1
LHF80V25
sharp
Mode
Read
Notes
8
Output Disable
Standby
10
Deep Power-Down
Read Identifier Codes
Write
4,10
8
6,7,8
Mode
Read
Notes
8
Output Disable
Standby
10
Deep Power-Down
4,10
Read Identifier Codes
8,9
Write
6,7,8
Table 3.1. Bus Operations(BYTE#=VIH)(1,2)
RP#
CE#
OE#
WE#
Address
VIH or
VIL
VIL
VIH
X
VHH
VIH or
VIL
VIH
VIH
X
VHH
VIH or
VIH
X
X
X
VHH
VIL
X
X
X
X
VIH or
See
VIL
VIL
VIH
VHH
Figure 4
VIH or
VIL
VIH
VIL
X
VHH
Table 3.2. Bus Operations(BYTE#=VIL)(1,2)
RP#
CE#
OE#
WE# Address
VPP
VIH or
VIL
VIL
VIH
X
X
VHH
VIH or
VIL
VIH
VIH
X
X
VHH
VIH or
VIH
X
X
X
X
VHH
VIL
X
X
X
X
X
VIH or
See
VIL
VIL
VIH
X
VHH
Figure 4
VIH or
VIL
VIH
VIL
X
X
VHH
10
VPP
DQ0-15
RY/BY#(3)
X
DOUT
X
X
High Z
X
X
High Z
X
X
High Z
High Z
X
Note 5
High Z
X
DIN
X
DQ0-7
DQ8-15 RY/BY#(3)
DOUT
High Z
X
High Z
High Z
X
High Z
High Z
X
High Z
High Z
High Z
Note 5
High Z
High Z
DIN
X
X
NOTES:
1. Refer to DC Characteristics. When VPP≤VPPLK, memory contents can be read, but not altered.
2. X can be VIL or VIH for control pins and addresses, and VPPLK or VPPH1/2 for VPP. See DC Characteristics for VPPLK and
VPPH1/2 voltages.
3. RY/BY# is VOL when the WSM is executing internal block erase or word/byte write algorithms. It is High Z during when
the WSM is not busy, in block erase suspend mode (with word/byte write inactive), word/byte write suspend mode or
deep power-down mode.
4. RP# at GND±0.2V ensures the lowest deep power-down current.
5. See Section 4.2 for read identifier code data.
6. Command writes involving block erase or word/byte write are reliably executed when VPP=VPPH1/2 and VCC=4.5V-5.5V.
Block erase or word/byte write with VIH<RP#<VHH produce spurious results and should not be attempted.
7. Refer to Table 4 for valid DIN during a write operation.
8. Never hold OE# low and WE# low at the same timing.
9. A-1 set to VIL or VIH in byte mode (BYTE#=VIL).
10. WP# set to VIL or VIH.
Rev. 1.1
sharp
Command
Read Array/Reset
Read Identifier Codes
Read Status Register
Clear Status Register
Block Erase
Word/Byte Write
LHF80V25
Table 4. Command Definitions(7)
Bus Cycles
First Bus Cycle
(1)
Req’d.
Notes
Oper
Addr(2)
Data(3)
1
Write
X
FFH
4
Write
X
90H
≥2
2
Write
X
70H
1
Write
X
50H
2
5
Write
BA
20H
40H or
2
5,6
Write
WA
10H
11
Second Bus Cycle
Addr(2)
Data(3)
Oper(1)
Read
Read
IA
X
ID
SRD
Write
BA
D0H
Write
WA
WD
Block Erase and Word/Byte
1
5
Write
X
B0H
Write Suspend
Block Erase and Word/Byte
1
5
Write
X
D0H
Write Resume
NOTES:
1. BUS operations are defined in Table 3.1 and Table 3.2.
2. X=Any valid address within the device.
IA=Identifier Code Address: see Figure 4. A-1 set to VIL or VIH in Byte Mode (BYTE#=VIL).
BA=Address within the block being erased. The each block can select by the address pin A18 through A12 combination.
WA=Address of memory location to be written.
3. SRD=Data read from status register. See Table 7 for a description of the status register bits.
WD=Data to be written at location WA. Data is latched on the rising edge of WE# or CE# (whichever goes high first).
ID=Data read from identifier codes.
4. Following the Read Identifier Codes command, read operations access manufacturer and device codes. See Section 4.2 for
read identifier code data.
5. If the block is boot block, WP# must be at VIH or RP# must be at VHH to enable block erase or word/byte write
operations. Attempts to issue a block erase or word/byte write to a boot block while WP# is VIH or RP# is VIH.
6. Either 40H or 10H are recognized by the WSM as the word/byte write setup.
7. Commands other than those shown above are reserved by SHARP for future device implementations and should not be
used.
Rev. 1.1
sharp
LHF80V25
12
4.1 Read Array Command
4.4 Clear Status Register Command
Upon initial device power-up and after exit from deep
power-down mode, the device defaults to read array mode.
This operation is also initiated by writing the Read Array
command. The device remains enabled for reads until
another command is written. Once the internal WSM has
started a block erase or word/byte write, the device will
not recognize the Read Array command until the WSM
completes its operation unless the WSM is suspended via
an Erase Suspend or Word/Byte Write Suspend command.
The Read Array command functions independently of the
VPP voltage and RP# can be VIH or VHH.
Status register bits SR.5, SR.4, SR.3 or SR.1 are set to
"1"s by the WSM and can only be reset by the Clear Status
Register command. These bits indicate various failure
conditions (see Table 7). By allowing system software to
reset these bits, several operations (such as cumulatively
erasing multiple blocks or writing several words/bytes in
sequence) may be performed. The status register may be
polled to determine if an error occurred during the
sequence.
4.2 Read Identifier Codes Command
The identifier code operation is initiated by writing the
Read Identifier Codes command. Following the command
write, read cycles from addresses shown in Figure 4
retrieve the manufacturer and device codes (see Table 5
for identifier code values). To terminate the operation,
write another valid command. Like the Read Array
command, the Read Identifier Codes command functions
independently of the VPP voltage and RP# can be VIH or
VHH. Following the Read Identifier Codes command, the
following information can be read:
Table 5. Identifier Codes
Address
Code
[A18-A0]
Manufacture Code
00000H
Device Code
00001H
Data
[DQ7-DQ0]
B0H
4CH
4.3 Read Status Register Command
The status register may be read to determine when a block
erase or word/byte write is complete and whether the
operation completed successfully. It may be read at any
time by writing the Read Status Register command. After
writing this command, all subsequent read operations
output data from the status register until another valid
command is written. The status register contents are
latched on the falling edge of OE# or CE#, whichever
occurs. OE# or CE# must toggle to VIH before further
reads to update the status register latch. The Read Status
Register command functions independently of the VPP
voltage. RP# can be VIH or VHH.
To clear the status register, the Clear Status Register
command (50H) is written. It functions independently of
the applied VPP Voltage. RP# can be VIH or VHH. This
command is not functional during block erase or
word/byte write suspend modes.
4.5 Block Erase Command
Erase is executed one block at a time and initiated by a
two-cycle command. A block erase setup is first written,
followed by an block erase confirm. This command
sequence requires appropriate sequencing and an address
within the block to be erased (erase changes all block data
to FFFFH). Block preconditioning, erase, and verify are
handled internally by the WSM (invisible to the system).
After the two-cycle block erase sequence is written, the
device automatically outputs status register data when read
(see Figure 5). The CPU can detect block erase completion
by analyzing the output data of the RY/BY# pin or status
register bit SR.7.
When the block erase is complete, status register bit SR.5
should be checked. If a block erase error is detected, the
status register should be cleared before system software
attempts corrective actions. The CUI remains in read
status register mode until a new command is issued.
This two-step command sequence of set-up followed by
execution ensures that block contents are not accidentally
erased. An invalid Block Erase command sequence will
result in both status register bits SR.4 and SR.5 being set
to "1". Also, reliable block erasure can only occur when
VCC=4.5V-5.5V and VPP=VPPH1/2. In the absence of this
high voltage, block contents are protected against erasure.
If block erase is attempted while VPP≤VPPLK, SR.3 and
SR.5 will be set to "1". Successful block erase for boot
blocks requires that the corresponding if set, that
WP#=VIH or RP#=VHH. If block erase is attempted to
boot block when the corresponding WP#=VIL or
RP#=VIH, SR.1 and SR.5 will be set to "1". Block erase
operations with VIH<RP#<VHH produce spurious results
and should not be attempted.
Rev. 1.1
sharp
LHF80V25
13
4.6 Word/Byte Write Command
4.7 Block Erase Suspend Command
Word/byte write is executed by a two-cycle command
sequence. Word/byte write setup (standard 40H or
alternate 10H) is written, followed by a second write that
specifies the address and data (latched on the rising edge
of WE#). The WSM then takes over, controlling the
word/byte write and write verify algorithms internally.
After the word/byte write sequence is written, the device
automatically outputs status register data when read (see
Figure 6). The CPU can detect the completion of the
word/byte write event by analyzing the RY/BY# pin or
status register bit SR.7.
The Block Erase Suspend command allows block-erase
interruption to read or word/byte write data in another
block of memory. Once the block-erase process starts,
writing the Block Erase Suspend command requests that
the WSM suspend the block erase sequence at a
predetermined point in the algorithm. The device outputs
status register data when read after the Block Erase
Suspend command is written. Polling status register bits
SR.7 and SR.6 can determine when the block erase
operation has been suspended (both will be set to "1").
RY/BY# will also transition to High Z. Specification
tWHRZ2 defines the block erase suspend latency.
When word/byte write is complete, status register bit SR.4
should be checked. If word/byte write error is detected, the
status register should be cleared. The internal WSM verify
only detects errors for "1"s that do not successfully write
to "0"s. The CUI remains in read status register mode until
it receives another command.
Reliable word/byte writes can only occur when
VCC=4.5V-5.5V and VPP=VPPH1/2. In the absence of this
high voltage, memory contents are protected against
word/byte writes. If word/byte write is attempted while
VPP≤VPPLK, status register bits SR.3 and SR.4 will be set
to "1". Successful word/byte write for boot blocks requires
that the corresponding if set, that WP#=VIH or RP#=VHH.
If word/byte write is attempted to boot block when the
corresponding WP#=VIL or RP#=VIH, SR.1 and SR.4 will
be set to "1". Word/byte write operations with
VIH<RP#<VHH produce spurious results and should not be
attempted.
At this point, a Read Array command can be written to
read data from blocks other than that which is suspended.
A Word/Byte Write command sequence can also be issued
during erase suspend to program data in other blocks.
Using the Word/Byte Write Suspend command (see
Section 4.8), a word/byte write operation can also be
suspended. During a word/byte write operation with block
erase suspended, status register bit SR.7 will return to "0"
and the RY/BY# output will transition to VOL. However,
SR.6 will remain "1" to indicate block erase suspend
status.
The only other valid commands while block erase is
suspended are Read Status Register and Block Erase
Resume. After a Block Erase Resume command is written
to the flash memory, the WSM will continue the block
erase process. Status register bits SR.6 and SR.7 will
automatically clear and RY/BY# will return to VOL. After
the Erase Resume command is written, the device
automatically outputs status register data when read (see
Figure 7). VPP must remain at VPPH1/2 (the same VPP
level used for block erase) while block erase is suspended.
RP# must also remain at VIH or VHH (the same RP# level
used for block erase). WP# must also remain at VIL or VIH
(the same WP# level used for block erase). Block erase
cannot resume until word/byte write operations initiated
during block erase suspend have completed.
Rev. 1.1
LHF80V25
sharp
14
4.8 Word/Byte Write Suspend Command
4.10 Block Locking
The Word/Byte Write Suspend command allows
word/byte write interruption to read data in other flash
memory locations. Once the word/byte write process
starts, writing the Word/Byte Write Suspend command
requests that the WSM suspend the word/byte write
sequence at a predetermined point in the algorithm. The
device continues to output status register data when read
after the Word/Byte Write Suspend command is written.
Polling status register bits SR.7 and SR.2 can determine
when the word/byte write operation has been suspended
(both will be set to "1"). RY/BY# will also transition to
High Z. Specification tWHRZ1 defines the word/byte write
suspend latency.
This Boot Block Flash memory architecture features two
hardware-lockable boot blocks so that the kernel code for
the system can be kept secure while other blocks are
programmed or erased as necessary.
At this point, a Read Array command can be written to
read data from locations other than that which is
suspended. The only other valid commands while
word/byte write is suspended are Read Status Register and
Word/Byte Write Resume. After Word/Byte Write
Resume command is written to the flash memory, the
WSM will continue the word/byte write process. Status
register bits SR.2 and SR.7 will automatically clear and
RY/BY# will return to VOL. After the Word/Byte Write
Resume command is written, the device automatically
outputs status register data when read (see Figure 8). VPP
must remain at VPPH1/2 (the same VPP level used for
word/byte write) while in word/byte write suspend mode.
RP# must also remain at VIH or VHH (the same RP# level
used for word/byte write). WP# must also remain at VIL or
VIH (the same WP# level used for word/byte write).
4.10.1 VPP=VIL for Complete Protection
The VPP programming voltage can be held low for
complete write protection of all blocks in the flash device.
4.10.2 WP#=VIL for Block Locking
The lockable blocks are locked when WP#=VIL; any
program or erase operation to a locked block will result in
an error, which will be reflected in the status register. For
top configuration, the top two boot blocks are lockable.
For the bottom configuration, the bottom tow boot blocks
are lockable. Unlocked blocks can be programmed or
erased normally (Unless VPP is below VPPLK).
4.10.3 WP#=VIH for Block Unlocking
WP#=VIH unlocks all lockable blocks.
These blocks can now be programmed or erased.
WP# controls 2 boot blocks locking and VPP provides
protection against spurious writes. Table 6 defines the
write protection methods.
4.9 Considerations of Suspend
After the suspend command write to the CUI, read status
register command has to write to CUI, then status register
bit SR.6 or SR.2 should be checked for places the device
in suspend mode.
Operation
Block Erase
or
Word/Byte Write
VPP
VIL
>VPPLK
Table 6. Write Protection Alternatives
RP#
WP#
X
X
All Blocks Locked.
VIL
X
All Blocks Locked.
VHH
X
All Blocks Unlocked.
VIH
VIL
2 Boot Blocks Locked.
VIH
All Blocks Unlocked.
Effect
Rev. 1.1
LHF80V25
sharp
WSMS
ESS
ES
7
6
5
15
Table 7. Status Register Definition
WBWS
VPPS
WBWSS
4
3
2
DPS
R
1
0
NOTES:
SR.7 = WRITE STATE MACHINE STATUS (WSMS)
1 = Ready
0 = Busy
Check RY/BY# or SR.7 to determine block erase or
word/byte write completion. SR.6-0 are invalid while
SR.7="0".
SR.6 = ERASE SUSPEND STATUS (ESS)
1 = Block Erase Suspended
0 = Block Erase in Progress/Completed
SR.5 = ERASE STATUS (ES)
1 = Error in Block Erasure
0 = Successful Block Erase
If both SR.5 and SR.4 are "1"s after a block erase attempt,
an improper command sequence was entered.
SR.4 = WORD/BYTE WRITE STATUS (WBWS)
1 = Error in Word/Byte Write
0 = Successful Word/Byte Write
SR.3 = VPP STATUS (VPPS)
1 = VPP Low Detect, Operation Abort
0 = VPP OK
SR.2 = WORD/BYTE WRITE SUSPEND STATUS
(WBWSS)
1 = Word/Byte Write Suspended
0 = Word/Byte Write in Progress/Completed
SR.1 = DEVICE PROTECT STATUS (DPS)
1 = WP# or RP# Lock Detected, Operation Abort
0 = Unlock
SR.0 = RESERVED FOR FUTURE ENHANCEMENTS (R)
SR.3 does not provide a continuous indication of VPP level.
The WSM interrogates and indicates the VPP level only after
Block Erase or Word/Byte Write command sequences. SR.3
is not guaranteed to reports accurate feedback only when
VPP≠VPPH1/2.
The WSM interrogates the WP# and RP# only after Block
Erase or Word/Byte Write command sequences. It informs
the system, depending on the attempted operation, if the
WP# is not VIH, RP# is not VHH.
SR.0 is reserved for future use and should be masked out
when polling the status register.
Rev. 1.1
LHF80V25
sharp
Start
Bus
Operation
Write
Write 20H,
Block Address
Write
Write D0H,
16
Command
Erase Setup
Erase
Confirm
Comments
Data=20H
Addr=Within Block to be Erased
Data=D0H
Addr=Within Block to be Erased
Block Address
Status Register Data
Read
Read Status
Register
Suspend Block
Erase Loop
No
SR.7=
0
Suspend
Block Erase
Yes
Check SR.7
Standby
1=WSM Ready
0=WSM Busy
Repeat for subsequent block erasures.
Full status check can be done after each block erase or after a sequence of
block erasures.
1
Write FFH after the last operation to place device in read array mode.
Full Status
Check if Desired
Block Erase
Complete
FULL STATUS CHECK PROCEDURE
Bus
Read Status Register
Data(See Above)
Operation
Command
Standby
Comments
Check SR.3
1=VPP Error Detect
1
VPP Range Error
SR.3=
Standby
Check SR.1
1=Device Protect Detect
0
Standby
Check SR.4,5
Both 1=Command Sequence Error
1
Device Protect Error
SR.1=
Standby
Check SR.5
1=Block Erase Error
0
SR.5,SR.4,SR.3 and SR.1 are only cleared by the Clear Status
Register Command in cases where multiple blocks are erased
1
SR.4,5=
Command Sequence
Error
before full status is checked.
If error is detected, clear the Status Register before attempting
retry or other error recovery.
0
1
SR.5=
Block Erase Error
0
Block Erase Successful
Figure 5. Automated Block Erase Flowchart
Rev. 1.1
LHF80V25
sharp
Start
Bus
Operation
Write
Write 40H or 10H,
Address
Write
17
Command
Setup Word/Byte Write
Word/Byte Write
Comments
Data=40H or 10H
Addr=Location to Be Written
Data=Data to Be Written
Addr=Location to Be Written
Write Word/Byte
Data and Address
Status Register Data
Read
Read
Status Register
Suspend Word/Byte
Write Loop
No
SR.7=
0
Suspend
Word/Byte Write
Yes
Check SR.7
Standby
1=WSM Ready
0=WSM Busy
Repeat for subsequent byte writes.
SR full status check can be done after each Word/Byte write, or after a sequence of
Word/Byte writes.
1
Write FFH after the last Word/Byte write operation to place device in
read array mode.
Full Status
Check if Desired
Word/Byte Write
Complete
FULL STATUS CHECK PROCEDURE
Read Status Register
Data(See Above)
Bus
Operation
Command
Standby
1
Comments
Check SR.3
1=VPP Error Detect
VPP Range Error
SR.3=
Standby
0
Standby
1
Check SR.1
1=Device Protect Detect
Check SR.4
1=Data Write Error
Device Protect Error
SR.1=
SR.4,SR.3 and SR.1 are only cleared by the Clear Status Register
command in cases where multiple locations are written before
0
full status is checked.
If error is detected, clear the Status Register before attempting
retry or other error recovery.
1
SR.4=
Word/Byte Write Error
0
Word/Byte Write
Successful
Figure 6. Automated Word/Byte Write Flowchart
Rev. 1.1
LHF80V25
sharp
Start
Bus
Operation
Write
Write B0H
18
Command
Erase
Suspend
Comments
Data=B0H
Addr=X
Status Register Data
Read
Addr=X
Read
Status Register
Check SR.7
1=WSM Ready
Standby
0=WSM Busy
0
SR.7=
Check SR.6
1=Block Erase Suspended
Standby
0=Block Erase Completed
1
Write
0
SR.6=
Erase
Resume
Data=D0H
Addr=X
Block Erase Completed
1
Read or
Word/Byte
Write?
Read
Read Array Data
Word/Byte Write
Word/Byte Write Loop
No
Done?
Yes
Write D0H
Block Erase Resumed
Write FFH
Read Array Data
Figure 7. Block Erase Suspend/Resume Flowchart
Rev. 1.1
LHF80V25
sharp
Start
Bus
Operation
Write
Write B0H
19
Command
Word/Byte Write
Suspend
Comments
Data=B0H
Addr=X
Status Register Data
Read
Addr=X
Read
Status Register
Check SR.7
1=WSM Ready
Standby
0=WSM Busy
SR.7=
0
Check SR.2
1=Word/Byte Write Suspended
Standby
0=Word/Byte Write Completed
1
Write
SR.2=
0
Read Array
Data=FFH
Addr=X
Word/Byte Write
Completed
Read Array locations other
Read
than that being written.
1
Write
Write FFH
Word/Byte Write
Resume
Data=D0H
Addr=X
Read Array Data
Done
No
Reading
Yes
Write D0H
Word/Byte Write
Resumed
Write FFH
Read Array Data
Figure 8. Word/Byte Write Suspend/Resume Flowchart
Rev. 1.1
sharp
LHF80V25
20
5 DESIGN CONSIDERATIONS
5.3 Power Supply Decoupling
5.1 Three-Line Output Control
Flash memory power switching characteristics require
careful device decoupling. System designers are interested
in three supply current issues; standby current levels,
active current levels and transient peaks produced by
falling and rising edges of CE# and OE#. Transient current
magnitudes depend on the device outputs’ capacitive and
inductive loading. Two-line control and proper decoupling
capacitor selection will suppress transient voltage peaks.
Each device should have a 0.1µF ceramic capacitor
connected between its VCC and GND and between its VPP
and GND. These high-frequency, low inductance
capacitors should be placed as close as possible to package
leads. Additionally, for every eight devices, a 4.7µF
electrolytic capacitor should be placed at the array’s power
supply connection between VCC and GND. The bulk
capacitor will overcome voltage slumps caused by PC
board trace inductance.
The device will often be used in large memory arrays.
SHARP provides three control inputs to accommodate
multiple memory connections. Three-line control provides
for:
a. Lowest possible memory power dissipation.
b. Complete assurance that data bus contention will not
occur.
To use these control inputs efficiently, an address decoder
should enable CE# while OE# should be connected to all
memory devices and the system’s READ# control line.
This assures that only selected memory devices have
active outputs while deselected memory devices are in
standby mode. RP# should be connected to the system
POWERGOOD signal to prevent unintended writes during
system power transitions. POWERGOOD should also
toggle during system reset.
5.2 RY/BY#, Block Erase and Word/Byte
Write Polling
RY/BY# is an open drain output that should be connected
to VCC by a pull up resistor to provide a hardware method
of detecting block erase and word/byte write completion.
It transitions low after block erase or word/byte write
commands and returns to High Z when the WSM has
finished executing the internal algorithm.
5.4 VPP Trace on Printed Circuit Boards
Updating flash memories that reside in the target system
requires that the printed circuit board designer pay
attention to the VPP Power supply trace. The VPP pin
supplies the memory cell current for word/byte writing
and block erasing. Use similar trace widths and layout
considerations given to the VCC power bus. Adequate VPP
supply traces and decoupling will decrease VPP voltage
spikes and overshoots.
RY/BY# can be connected to an interrupt input of the
system CPU or controller. It is active at all times. RY/BY#
is also High Z when the device is in block erase suspend
(with word/byte write inactive), word/byte write suspend
or deep power-down modes.
Rev. 1.2
sharp
LHF80V25
5.5 VCC, VPP, RP# Transitions
Block erase and word/byte write are not guaranteed if VPP
falls outside of a valid VPPH1/2 range, VCC falls outside of
a valid 4.5V-5.5V range, or RP#≠VIH or VHH. If VPP error
is detected, status register bit SR.3 is set to "1" along with
SR.4 or SR.5, depending on the attempted operation. If
RP# transitions to VIL during block erase or word/byte
write, RY/BY# will remain low until the reset operation is
complete. Then, the operation will abort and the device
will enter deep power-down. The aborted operation may
leave data partially altered. Therefore, the command
sequence must be repeated after normal operation is
restored. Device power-off or RP# transitions to VIL clear
the status register.
The CUI latches commands issued by system software and
is not altered by VPP or CE# transitions or WSM actions.
Its state is read array mode upon power-up, after exit from
deep power-down or after VCC transitions below VLKO.
After block erase or word/byte write, even after VPP
transitions down to VPPLK, the CUI must be placed in read
array mode via the Read Array command if subsequent
access to the memory array is desired.
5.6 Power-Up/Down Protection
The device is designed to offer protection against
accidental block erasure or word/byte writing during
power transitions. Upon power-up, the device is
indifferent as to which power supply (VPP or VCC)
powers-up first. Internal circuitry resets the CUI to read
array mode at power-up.
21
A system designer must guard against spurious writes for
VCC voltages above VLKO when VPP is active. Since both
WE# and CE# must be low for a command write, driving
either to VIH will inhibit writes. The CUI’s two-step
command sequence architecture provides added level of
protection against data alteration.
WP# provide additional protection from inadvertent code
or data alteration. The device is disabled while RP#=VIL
regardless of its control inputs state.
5.7 Power Dissipation
When designing portable systems, designers must consider
battery power consumption not only during device
operation, but also for data retention during system idle
time. Flash memory’s nonvolatility increases usable
battery life because data is retained when system power is
removed.
In addition, deep power-down mode ensures extremely
low power consumption even when system power is
applied. For example, portable computing products and
other power sensitive applications that use an array of
devices for solid-state storage can consume negligible
power by lowering RP# to VIL standby or sleep modes. If
access is again needed, the devices can be read following
the tPHQV and tPHWL wake-up cycles required after RP# is
first raised to VIH. See AC Characteristics− Read Only
and Write Operations and Figures 11, 12, 13 and 14 for
more information.
Rev. 1.1
sharp
LHF80V25
6 ELECTRICAL SPECIFICATIONS
6.1 Absolute Maximum Ratings*
Operating Temperature
During Read, Block Erase and
Word/Byte Write.................................0°C to +70°C(1)
Temperature under Bias ...................... -10°C to +80°C
Storage Temperature ................................ -65°C to +125°C
Voltage On Any Pin
(except VCC, VPP, and RP#) ............ -0.5V to +7.0V(2)
VCC Supply Voltage................................ -0.2V to +7.0V(2)
VPP Update Voltage during Block
Erase and Word/Byte Write ......... -0.2V to +14.0V(2,3)
RP# Voltage ........................................ -0.5V to +14.0V(2,3)
22
*WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage. These
are stress ratings only. Operation beyond the "Operating
Conditions" is not recommended and extended exposure
beyond the "Operating Conditions" may affect device
reliability.
NOTES:
1. Operating temperature is for commercial temperature
product defined by this specification.
2. All specified voltages are with respect to GND.
Minimum DC voltage is -0.5V on input/output pins
and -0.2V on VCC and VPP pins. During transitions,
this level may undershoot to -2.0V for periods <20ns.
Maximum DC voltage on input/output pins and VCC is
VCC+0.5V which, during transitions, may overshoot to
VCC+2.0V for periods <20ns.
3. Maximum DC voltage on VPP and RP# may overshoot
to +14.0V for periods <20ns.
4. Output shorted for no more than one second. No more
than one output shorted at a time.
Output Short Circuit Current................................100mA(4)
6.2 Operating Conditions
Temperature and VCC Operating Conditions
Symbol
Parameter
Min.
Max.
Unit
TA
Operating Temperature
0
+70
°C
VCC
VCC Supply Voltage (4.5V-5.5V)
4.5
5.5
V
Test Condition
Ambient Temperature
6.2.1 CAPACITANCE(1)
Symbol
Parameter
CIN
Input Capacitance
COUT
Output Capacitance
NOTE:
1. Sampled, not 100% tested.
TA=+25°C, f=1MHz
Typ.
Max.
7
10
9
12
Unit
pF
pF
Condition
VIN=0.0V
VOUT=0.0V
Rev. 1.2
LHF80V25
sharp
23
6.2.2 AC INPUT/OUTPUT TEST CONDITIONS
3.0
INPUT
TEST POINTS
1.5
1.5
OUTPUT
0.0
AC test inputs are driven at 3.0V for a Logic "1" and 0.0V for a Logic "0." Input timing begins, and output timing ends, at 1.5V.
Input rise and fall times (10% to 90%) <10 ns.
Figure 9. Transient Input/Output Reference Waveform for VCC=4.5V-5.5V
Test Configuration Capacitance Loading Value
Test Configuration
CL(pF)
VCC=4.5V-5.5V
50
1.3V
1N914
RL=3.3kΩ
DEVICE
UNDER
TEST
CL Includes Jig
Capacitance
OUT
CL
Figure 10. Transient Equivalent Testing Load
Circuit
Rev. 1.1
LHF80V25
sharp
24
6.2.3 DC CHARACTERISTICS
Sym.
ILI
Parameter
Input Load Current
ILO
Output Leakage Current
ICCS
VCC Standby Current
DC Characteristics
VCC=5V±0.5V
Notes
Typ.
Max.
1
±1
±10
µA
30
100
µA
0.4
2
mA
10
µA
50
mA
65
mA
35
30
30
25
mA
mA
mA
mA
Test
Conditions
VCC=VCCMax.
VIN=VCC or GND
VCC=VCCMax.
VOUT=VCC or GND
CMOS Inputs
VCC=VCCMax.
CE#=RP#=VCC±0.2V
TTL Inputs
VCC=VCCMax.
CE#=RP#=VIH
RP#=GND±0.2V
IOUT(RY/BY#)=0mA
CMOS Inputs
VCC=VCCMax., CE#=GND
f=8MHz, IOUT=0mA
TTL Inputs
VCC=VCCMax., CE#=GND
f=8MHz, IOUT=0mA
VPP=4.5V-5.5V
VPP=11.4V-12.6V
VPP=4.5V-5.5V
VPP=11.4V-12.6V
1
10
mA
CE#=VIH
±2
10
0.1
±15
200
5
40
30
25
20
µA
µA
µA
mA
mA
mA
mA
VPP≤VCC
VPP>VCC
RP#=GND±0.2V
VPP=4.5V-5.5V
VPP=11.4V-12.6V
VPP=4.5V-5.5V
VPP=11.4V-12.6V
10
200
µA
VPP=VPPH1/2
1
1,3,6,
10
Unit
µA
1,3,6
ICCD
VCC Deep Power-Down Current
1,10
ICCR
VCC Read Current
1,5,6
ICCW
VCC Word/Byte Write Current
1,7
ICCE
VCC Block Erase Current
1,7
ICCWS
ICCES
IPPS
VCC Word/Byte Write or Block
Erase Suspend Current
VPP Standby or Read Current
1,2
IPPR
IPPD
IPPW
VPP Deep Power-Down Current
VPP Word/Byte Write Current
1
1,7
IPPE
VPP Block Erase Current
1,7
IPPWS
IPPES
VPP Word/Byte Write or Block Erase
Suspend Current
1
1
Rev. 1.1
sharp
Sym.
VIL
VIH
Parameter
Input Low Voltage
Input High Voltage
VOL
Output Low Voltage
VOH1
Output High Voltage
(TTL)
Output High Voltage
(CMOS)
VOH2
VPPLK
VPPH1
VPPH2
LHF80V25
25
DC Characteristics (Continued)
VCC=5V±0.5V
Notes
Min.
Max.
7
-0.5
0.8
7
VCC
2.4
+0.5
3,7
0.45
VPP Lockout Voltage during Normal
Operations
VPP Voltage during Word/Byte Write
or Block Erase Operations
VPP Voltage during Word/Byte Write
or Block Erase Operations
VCC Lockout Voltage
RP# Unlock Voltage
3,7
3,7
2.4
Test Conditions
V
V
V
0.85
VCC
VCC
-0.4
4,7
Unit
V
V
V
1.5
V
4.5
5.5
V
11.4
12.6
V
VCC=VCC Min.
IOL=5.8mA
VCC=VCC Min.
IOH=-2.5mA
VCC=VCC Min.
IOH=-2.0mA
VCC=VCC Min.
IOH=-100µA
VLKO
2.0
V
VHH
8,9
11.4
12.6
V
Unavailable WP#
NOTES:
1. All currents are in RMS unless otherwise noted. Typical values at nominal VCC voltage and TA=+25°C.
2. ICCWS and ICCES are specified with the device de-selected. If read or word/byte written while in erase suspend mode, the
device’s current draw is the sum of ICCWS or ICCES and ICCR or ICCW, respectively.
3. Includes RY/BY#.
4. Block erases and word/byte writes are inhibited when VPP≤VPPLK, and not guaranteed in the range between VPPLK(max.)
and VPPH1(min.), between VPPH1(max.) and VPPH2(min.) and above VPPH2(max.).
5. Automatic Power Savings (APS) reduces typical ICCR to 1mA at 5V VCC in static operation.
6. CMOS inputs are either VCC±0.2V or GND±0.2V. TTL inputs are either VIL or VIH.
7. Sampled, not 100% tested.
8. Boot block erases and word/byte writes are inhibited when the corresponding RP#=VIH and WP#=VIL. Block erase and
word/byte write operations are not guaranteed with VIH<RP#<VHH and should not be attempted.
9. RP# connection to a VHH supply is allowed for a maximum cumulative period of 80 hours.
10. BYTE# input level is VCC±0.2V in word mode or GND±0.2V in byte mode. WP# input level is VCC±0.2V or GND±0.2V.
Rev. 1.2
sharp
LHF80V25
26
6.2.4 AC CHARACTERISTICS - READ-ONLY OPERATIONS(1)
Sym.
tAVAV
tAVQV
tELQV
tPHQV
tGLQV
tELQX
tEHQZ
tGLQX
tGHQZ
tOH
VCC=4.5V-5.5V, TA=0°C to +70°C
Parameter
Notes
Read Cycle Time
Address to Output Delay
CE# to Output Delay
RP# High to Output Delay
OE# to Output Delay
CE# to Output in Low Z
CE# High to Output in High Z
OE# to Output in Low Z
OE# High to Output in High Z
Output Hold from Address, CE# or OE# Change, Whichever
Occurs First
BYTE# and A-1 to Output Delay
BYTE# Low to Output in High Z
CE# to BYTE# High or Low
Min.
85
85
85
400
45
2
2
3
3
3
3
3
Max.
0
55
0
10
0
tFVQV
3
tFLQZ
3
tELFV
3,4
NOTES:
1. See AC Input/Output Reference Waveform for maximum allowable input slew rate.
2. OE# may be delayed up to tELQV-tGLQV after the falling edge of CE# without impact on tELQV.
3. Sampled, not 100% tested.
4. If BYTE# transfer during reading cycle, exist the regulations separately.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
85
30
5
ns
ns
ns
Rev. 1.1
LHF80V25
sharp
VIH
Standby
Device
Address Selection
ADDRESSES(A)
27
Data Valid
Address Stable
VIL
tAVAV
VIH
CE#(E)
tEHQZ
VIL
VIH
OE#(G)
tGHQZ
VIL
VIH
WE#(W)
tGLQV
tELQV
VIL
tGLQX
tELQX
tOH
VOH
DATA(D/Q)
(DQ0-DQ15)
HIGH Z
Valid Output
VOL
HIGH Z
tAVQV
VCC
tPHQV
VIH
RP#(P)
VIL
Figure 11. AC Waveform for Read Operations
Rev. 1.1
LHF80V25
sharp
VIH
Standby
Device
Address Selection
ADDRESSES(A)
28
Data Valid
Address Stable
VIL
tAVAV
VIH
CE#(E)
tEHQZ
VIL
VIH
OE#(G)
VIL
tGHQZ
tELFV
tGLQV
tFVQV
VIH
BYTE#(F)
VIL
tELQV
tGLQX
tOH
VOH
DATA(D/Q)
(DQ0-DQ7)
HIGH Z
tELQX
VOL
Data Output
Valid
Output
HIGH Z
tAVQV
tFLQZ
VOH
DATA(D/Q)
(DQ8-DQ15)
HIGH Z
Data
Output
HIGH Z
VOL
Figure 12. BYTE# timing Waveform
Rev. 1.1
sharp
LHF80V25
29
6.2.5 AC CHARACTERISTICS - WRITE OPERATIONS(1)
VCC=4.5V-5.5V, TA=0°C to +70°C
Parameter
Notes
Sym.
Min.
Max.
Unit
tAVAV
Write Cycle Time
85
ns
tPHWL
RP# High Recovery to WE# Going Low
2
1
µs
tELWL
CE# Setup to WE# Going Low
10
ns
tWLWH WE# Pulse Width
40
ns
tPHHWH RP# VHH Setup to WE# Going High
2
100
ns
tSHWH
WP# VIH Setup to WE# Going High
2
100
ns
tVPWH
VPP Setup to WE# Going High
2
100
ns
tAVWH
Address Setup to WE# Going High
3
40
ns
tDVWH
Data Setup to WE# Going High
3
40
ns
tWHDX
Data Hold from WE# High
0
ns
tWHAX
Address Hold from WE# High
5
ns
tWHEH
CE# Hold from WE# High
10
ns
tWHWL WE# Pulse Width High
30
ns
tWHRL
WE# High to RY/BY# Going Low
90
ns
tWHGL
Write Recovery before Read
0
ns
tQVVL
VPP Hold from Valid SRD, RY/BY# High Z
2,4
0
ns
tQVPH
RP# VHH Hold from Valid SRD, RY/BY# High Z
2,4
0
ns
tQVSL
WP# VIH Hold from Valid SRD, RY/BY# High Z
2,4
0
ns
tFVWH
BYTE# Setup to WE# Going High
5
40
ns
tWHFV
BYTE# Hold from WE# High
5
85
ns
NOTES:
1. Read timing characteristics during block erase and word/byte write operations are the same as during read-only operations.
Refer to AC Characteristics for read-only operations.
2. Sampled, not 100% tested.
3. Refer to Table 4 for valid AIN and DIN for block erase or word/byte write.
4. VPP should be held at VPPH1/2 (and if necessary RP# should be held at VHH) until determination of block erase or
word/byte write success (SR.1/3/4/5=0).
5. If BYTE# switch during reading cycle, exist the regulations separately.
Rev. 1.1
sharp
LHF80V25
AIN
AIN
4
5
6
Valid
SRD
DIN
}
}
3
}
2
}
}
}
1
30
VIH
ADDRESSES(A)
VIL
tWHAX
tAVWH
tAVAV
VIH
CE#(E)
VIL
tWHEH
tELWL
tWHGL
VIH
OE#(G)
VIL
tWHQV1,2
tWHWL
VIH
WE#(W)
VIL
VIH
DATA(D/Q)
High Z
tWLWH
tDVWH
tWHDX
DIN
DIN
VIL
tPHWL
tFVWH
tWHFV
VIH
BYTE#(F)
VIL
tWHRL
High Z
RY/BY#(R)
VOL
tSHWH
tQVSL
tPHHWH
tQVPH
VIH
WP#(S)
VIL
VHH
RP#(P)
VIH
VIL
tVPWH
VPPH2,1
VPP(V)
tQVVL
VPPLK
VIL
NOTES:
1. VCC power-up and standby.
2. Write block erase or word/byte write setup.
3. Write block erase confirm or valid address and data.
4. Automated erase or program delay.
5. Read status register data.
6. Write Read Array command.
Figure 13. AC Waveform for WE#-Controlled Write Operations
Rev. 1.2
sharp
LHF80V25
31
6.2.6 ALTERNATIVE CE#-CONTROLLED WRITES(1)
VCC=4.5V-5.5V, TA=0°C to +70°C
Parameter
Notes
Sym.
Min.
Max.
Unit
tAVAV
Write Cycle Time
85
ns
tPHEL
RP# High Recovery to CE# Going Low
2
1
µs
tWLEL
WE# Setup to CE# Going Low
0
ns
tELEH
CE# Pulse Width
50
ns
tPHHEH RP# VHH Setup to CE# Going High
2
100
ns
tSHEH
WP# VIH Setup to CE# Going High
2
100
ns
tVPEH
VPP Setup to CE# Going High
2
100
ns
tAVEH
Address Setup to CE# Going High
3
40
ns
tDVEH
Data Setup to CE# Going High
3
40
ns
tEHDX
Data Hold from CE# High
0
ns
tEHAX
Address Hold from CE# High
5
ns
tEHWH
WE# Hold from CE# High
0
ns
tEHEL
CE# Pulse Width High
25
ns
tEHRL
CE# High to RY/BY# Going Low
90
ns
tEHGL
Write Recovery before Read
0
ns
tQVVL
VPP Hold from Valid SRD, RY/BY# High Z
2,4
0
ns
tQVPH
RP# VHH Hold from Valid SRD, RY/BY# High Z
2,4
0
ns
tQVSL
WP# VIH Hold from Valid SRD, RY/BY# High Z
2,4
0
ns
tFVEH
BYTE# Setup to CE# Going High
5
40
ns
tEHFV
BYTE# Hold from CE# High
5
85
ns
NOTES:
1. In systems where CE# defines the write pulse width (within a longer WE# timing waveform), all setup, hold, and inactive
WE# times should be measured relative to the CE# waveform.
2. Sampled, not 100% tested.
3. Refer to Table 4 for valid AIN and DIN for block erase or word/byte write.
4. VPP should be held at VPPH1/2 (and if necessary RP# should be held at VHH) until determination of block erase or
word/byte write success (SR.1/3/4/5=0).
5. If BYTE# switch during reading cycle, exist the regulations separately.
Rev. 1.1
sharp
LHF80V25
AIN
AIN
4
5
6
Valid
SRD
DIN
}
}
3
}
2
}
}
}
1
32
VIH
ADDRESSES(A)
VIL
tEHAX
tAVEH
tAVAV
VIH
tEHEL
CE#(E)
VIL
tELEH
tDVEH
VIH
tEHGL
OE#(G)
VIL
VIH
WE#(W)
VIL
VIH
DATA(D/Q)
High Z
tEHQV1,2
tEHWH
tEHDX
tWLEL
DIN
DIN
VIL
tPHEL
tFVEH
tEHFV
VIH
BYTE#(F)
VIL
tEHRL
High Z
RY/BY#(R)
VOL
tSHEH
tQVSL
tPHHEH
tQVPH
VIH
WP#(S)
VIL
VHH
RP#(P)
VIH
VIL
tVPEH
VPPH2,1
VPP(V)
tQVVL
VPPLK
VIL
NOTES:
1. VCC power-up and standby.
2. Write block erase or word/byte write setup.
3. Write block erase confirm or valid address and data.
4. Automated erase or program delay.
5. Read status register data.
6. Write Read Array command.
Figure 14. AC Waveform for CE#-Controlled Write Operations
Rev. 1.2
LHF80V25
sharp
33
6.2.7 RESET OPERATIONS
High Z
RY/BY#(R)
VOL
VIH
RP#(P)
VIL
tPLPH
(A)Reset During Read Array Mode
High Z
RY/BY#(R)
VOL
tPLRZ
VIH
RP#(P)
VIL
tPLPH
(B)Reset During Block Erase or Word/Byte Write
5V
VCC
VIL
t5VPH
VIH
RP#(P)
VIL
(C)RP# rising Timing
Figure 15. AC Waveform for Reset Operation
Reset AC Specifications
Sym.
tPLPH
Parameter
RP# Pulse Low Time
(If RP# is tied to VCC, this specification is not applicable)
RP# Low to Reset during Block Erase or Word/Byte Write
VCC 4.5V to RP# High
Notes
VCC=4.5V-5.5V
Min.
Max.
100
Unit
ns
tPLRZ
1,2
12
µs
t5VPH
3
100
ns
NOTES:
1. If RP# is asserted while a block erase or word/byte write operation is not executing, the reset will complete within 100ns.
2. A reset time, tPHQV, is required from the later of RY/BY# going High Z or RP# going high until outputs are valid.
3. When the device power-up, holding RP# low minimum 100ns is required after VCC has been in predefined range and also
has been in stable there.
Rev. 1.1
sharp
LHF80V25
34
6.2.8 BLOCK ERASE AND WORD/BYTE WRITE PERFORMANCE(3)
Sym.
tWHQV1
tEHQV1
VCC=5V±0.5V, TA=0°C to +70°C
VPP=4.5V-5.5V
Parameter
Notes
Typ.(1)
Max.
Word/Byte Write Time 32K word Block
2
12.2
4K word Block
2
18.3
Block Write Time
32K word Block
2,4
0.4
4K word Block
2,4
0.08
Block Erase Time
32K word Block
2
0.46
4K word Block
2
0.26
Word/Byte Write Suspend Latency Time
5
6
to Read
VPP=11.4V-12.6V
Typ.(1)
Max.
8.4
17
0.28
0.07
0.39
0.25
tWHQV2
tEHQV2
tWHRZ1
4
5
tEHRZ1
tWHRZ2
Erase Suspend Latency Time to Read
9.6
12
9.6
12
tEHRZ2
NOTES:
1. Typical values measured at TA=+25°C and nominal voltages. Subject to change based on device characterization.
2. Excludes system-level overhead.
3. Sampled but not 100% tested.
4. All values are in word mode (BYTE#=VIH). At byte mode (BYTE#=VIL), those values are double.
Unit
µs
µs
s
s
s
s
µs
µs
Rev. 1.1
i
sharp
A-1 RECOMMENDED OPERATING CONDITIONS
A-1.1 At Device Power-Up
AC timing illustrated in Figure A-1 is recommended for the supply voltages and the control signals at device power-up.
If the timing in the figure is ignored, the device may not operate correctly.
VCC(min)
VCC
GND
tVR
t2VPH *1
tR
tPHQV
VIH
RP# (P)
(RST#)
VCCW *2
(VPP)
(V)
VIL
VCCWH1/2
(VPPH1/2)
GND
VIH
tR or tF
tR or tF
tAVQV
Valid
Address
ADDRESS (A)
VIL
tF
tR
tELQV
VIH
CE#
(E)
VIL
VIH
WE# (W)
VIL
tF
tR
tGLQV
VIH
OE#
(G)
VIL
VIH
WP#
(S)
VIL
VOH
DATA (D/Q)
VOL
High Z
Valid
Output
*1 t5VPH for the device in 5V operations.
*2 To prevent the unwanted writes, system designers should consider the VCCW (VPP) switch, which connects VCCW (VPP)
to GND during read operations and VCCWH1/2 (VPPH1/2) during write or erase operations.
See the application note AP-007-SW-E for details.
Figure A-1. AC Timing at Device Power-Up
For the AC specifications tVR, tR, tF in the figure, refer to the next page. See the “ELECTRICAL SPECIFICATIONS“
described in specifications for the supply voltage range, the operating temperature and the AC specifications not shown in
the next page.
Rev. 1.10
ii
sharp
A-1.1.1 Rise and Fall Time
Symbol
Parameter
Notes
Min.
Max.
Unit
1
0.5
30000
µs/V
tVR
VCC Rise Time
tR
Input Signal Rise Time
1, 2
1
µs/V
tF
Input Signal Fall Time
1, 2
1
µs/V
NOTES:
1. Sampled, not 100% tested.
2. This specification is applied for not only the device power-up but also the normal operations.
tR(Max.) and tF(Max.) for RP# (RST#) are 100µs/V.
Rev. 1.10
iii
sharp
A-1.2 Glitch Noises
Do not input the glitch noises which are below VIH (Min.) or above VIL (Max.) on address, data, reset, and control signals,
as shown in Figure A-2 (b). The acceptable glitch noises are illustrated in Figure A-2 (a).
Input Signal
Input Signal
VIH (Min.)
VIH (Min.)
VIL (Max.)
VIL (Max.)
Input Signal
Input Signal
(a) Acceptable Glitch Noises
(b) NOT Acceptable Glitch Noises
Figure A-2. Waveform for Glitch Noises
See the “DC CHARACTERISTICS“ described in specifications for VIH (Min.) and VIL (Max.).
Rev. 1.10
iv
sharp
A-2 RELATED DOCUMENT INFORMATION(1)
Document No.
Document Name
AP-001-SD-E
Flash Memory Family Software Drivers
AP-006-PT-E
Data Protection Method of SHARP Flash Memory
AP-007-SW-E
RP#, VPP Electric Potential Switching Circuit
NOTE:
1. International customers should contact their local SHARP or distribution sales office.
Rev. 1.10
SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE.
Suggested applications (if any) are for standard use; See Important Restrictions for limitations on special applications. See Limited Warranty
for SHARP’s product warranty. The Limited Warranty is in lieu, and exclusive of, all other warranties, express or implied. ALL EXPRESS
AND IMPLIED WARRANTIES, INCLUDING THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR USE AND FITNESS FOR A
PARTICULAR PURPOSE, ARE SPECIFICALLY EXCLUDED. In no event will SHARP be liable, or in any way responsible, for any incidental
or consequential economic or property damage.
NORTH AMERICA
EUROPE
ASIA
SHARP Microelectronics
of the Americas
5700 NW Pacific Rim Blvd.
Camas, WA 98607, U.S.A.
Phone: (360) 834-2500
Fax: (360) 834-8903
http://www.sharpsma.com
SHARP Microelectronics Europe
Sonninstraße 3
20097 Hamburg, Germany
Phone: (49) 40 2376-2286
Fax: (49) 40 2376-2232
http://www.sharpsme.com
SHARP Corporation
Integrated Circuits Group
2613-1 Ichinomoto-Cho
Tenri-City, Nara, 632, Japan
Phone: +81-743-65-1321
Fax: +81-743-65-1532
http://www.sharp.co.jp