TI TPS51916RUKT

TPS51916
SLUSAE1B – DECEMBER 2010 – REVISED AUGUST 2011
www.ti.com
Complete DDR2, DDR3 and DDR3L Memory Power Solution Synchronous Buck
Controller, 2-A LDO, Buffered Reference
FEATURES
DESCRIPTION
•
The TPS51916 provides a complete power supply for
DDR2, DDR3 and DDR3L memory systems in the
lowest total cost and minimum space. It integrates a
synchronous buck regulator controller (VDDQ) with a
2-A sink/source tracking LDO (VTT) and buffered low
noise reference (VTTREF). The TPS51916 employs
D-CAP™ mode coupled with 300 kHz/400 kHz
frequencies for ease-of-use and fast transient
response or D-CAP2™ mode coupled with higher
500 kHz/670 kHz frequencies to support ceramic
output capacitor without an external compensation
circuit. The VTTREF tracks VDDQ/2 within excellent
0.8% accuracy. The VTT, which provides 2-A
sink/source peak current capabilities, requires only
10-μF of ceramic capacitance. In addition, a
dedicated LDO supply input is available.
1
2
•
•
•
Synchronous Buck Controller (VDDQ)
– Conversion Voltage Range: 3 V to 28 V
– Output Voltage Range: 0.7 V to 1.8 V
– 0.8% VREF Accuracy
– Selectable Control Architecture
– D-CAP™ Mode for Fast Transient
Response
– D-CAP2™ Mode for Ceramic Output
Capacitors
– Selectable 300 kHz/ 400 kHz/ 500 kHz/
670 kHz Switching Frequencies
– Optimized Efficiency at Light and Heavy
Loads with Auto-skip Function
– Supports Soft-Off in S4/S5 States
– OCL/OVP/UVP/UVLO Protections
– Powergood Output
2-A LDO(VTT), Buffered Reference(VTTREF)
– 2-A (Peak) Sink and Source Current
– Requires Only 10-μF of Ceramic Output
Capacitance
– Buffered, Low Noise, 10-mA VTTREF
Output
– 0.8% VTTREF, 20-mV VTT Accuracy
– Support High-Z in S3 and Soft-Off in S4/S5
Thermal Shutdown
20-Pin, 3 mm × 3 mm, QFN Package
APPLICATIONS
•
•
The TPS51916 provides rich useful functions as well
as excellent power supply performance. It supports
flexible power state control, placing VTT at high-Z in
S3 and discharging VDDQ, VTT and VTTREF
(soft-off) in S4/S5 state. Programmable OCL with
low-side MOSFET RDS(on) sensing, OVP/UVP/UVLO
and thermal shutdown protections are also available.
The TPS51916 is available in a 20-pin, 3 mm × 3
mm, QFN package and is specified for ambient
temperature from –40°C to 85°C.
VIN
5VIN
PGND
PGND
TPS51916
VBST 15
12 V5IN
S3
17 S3
S5
16 S5
DDR2/DDR3/DDR3L Memory Power Supplies
SSTL_18, SSTL_15, SSTL_135 and HSTL
Termination
VDDQ
DRVH 14
SW 13
DRVL 11
6
VREF
8
REFIN
PGND 10
PGOOD 20
VDDQSNS
9
VLDOIN
2
VTT
3
19 MODE
VTTSNS
1
18 TRIP
VTTGND
4
VTTREF
5
7
GND
Powergood
VTT
VTTREF
UDG-10193
AGND PGND
AGND
PGND
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
D-CAP, D-CAP2 are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010–2011, Texas Instruments Incorporated
TPS51916
SLUSAE1B – DECEMBER 2010 – REVISED AUGUST 2011
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION (1)
TA
PACKAGE
–40°C to 85°C
Plastic Quad Flat Pack (QFN)
(1)
ORDERABLE DEVICE
NUMBER
TPS51916RUKR
TPS51916RUKT
PINS
20
OUTPUT
SUPPLY
MINIMUM
QUANTITY
Tape and reel
3000
Mini reel
250
For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
VALUE
MAX
VBST
–0.3
36
VBST (3)
–0.3
6
–5
30
VLDOIN, VDDQSNS, REFIN
–0.3
3.6
VTTSNS
–0.3
3.6
PGND, VTTGND
–0.3
0.3
V5IN, S3, S5, TRIP, MODE
–0.3
6
–5
36
SW
Input voltage range (2)
DRVH
Output voltage range (2)
DRVH (3)
–0.3
6
VTTREF, VREF
–0.3
3.6
VTT
–0.3
3.6
DRVL
–0.3
6
PGOOD
–0.3
Junction temperature range, TJ
–55
Storage temperature range, TSTG
(1)
(2)
(3)
UNIT
MIN
V
V
6
125
°C
150
°C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to the network ground terminal unless otherwise noted.
Voltage values are with respect to the SW terminal.
THERMAL INFORMATION
THERMAL METRIC
TPS51916
QFN (20) PINS
θJA
Junction-to-ambient thermal resistance
94.1
θJCtop
Junction-to-case (top) thermal resistance
58.1
θJB
Junction-to-board thermal resistance
64.3
ψJT
Junction-to-top characterization parameter
31.8
ψJB
Junction-to-board characterization parameter
58.0
θJCbot
Junction-to-case (bottom) thermal resistance
5.9
2
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UNITS
°C/W
Copyright © 2010–2011, Texas Instruments Incorporated
TPS51916
SLUSAE1B – DECEMBER 2010 – REVISED AUGUST 2011
www.ti.com
RECOMMENDED OPERATING CONDITIONS
MIN
Supply voltage
5.5
VBST
–0.1
33.5
VBST (1)
–0.1
5.5
-3
28
SW (2)
–4.5
28
VLDOIN, VDDQSNS, REFIN
–0.1
3.5
VTTSNS
–0.1
3.5
PGND, VTTGND
–0.1
0.1
S3, S5, TRIP, MODE
–0.1
5.5
–3
33.5
DRVH
Output voltage range
TA
(1)
(2)
MAX
4.5
SW
Input voltage range
TYP
V5IN
DRVH (1)
–0.1
5.5
DRVH (2)
–4.5
33.5
VTTREF, VREF
–0.1
3.5
VTT
–0.1
3.5
DRVL
–0.1
5.5
PGOOD
–0.1
5.5
Operating free-air temperature
–40
85
UNIT
V
V
V
°C
Voltage values are with respect to the SW terminal.
This voltage should be applied for less than 30% of the repetitive period.
Copyright © 2010–2011, Texas Instruments Incorporated
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ELECTRICAL CHARACTERISTICS
over operating free-air temperature range, VV5IN = 5 V, VLDOIN is connected to VDDQ output, VMODE= 0 V, VS3= VS5= 5 V
(unless otherwise noted)
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
SUPPLY CURRENT
μA
IV5IN(S0)
V5IN supply current, in S0
TA = 25°C, No load, VS3 = VS5 = 5 V
590
IV5IN(S3)
V5IN supply current, in S3
TA = 25°C, No load, VS3 = 0 V, VS5 = 5 V
500
IV5INSDN
V5IN shutdown current
TA = 25°C, No load, VS3 = VS5 = 0 V
1
μA
IVLDOIN(S0)
VLDOIN supply current, in S0
TA = 25°C, No load, VS3 = VS5 = 5 V
5
μA
IVLDOIN(S3)
VLDOIN supply current, in S3
TA = 25°C, No load, VS3 = 0 V, VS5 = 5 V
5
μA
IVLDOINSDN
VLDOIN shutdown current
TA = 25°C, No load, VS3 = VS5 = 0 V
5
μA
V
μA
VREF OUTPUT
IVREF = 30 μA, TA = 25°C
VVREF
Output voltage
IVREFOCL
Current limit
1.8000
0 μA ≤ IVREF <300 μA, TA = –10°C to 85°C
1.7856
1.8144
0 μA ≤ IVREF <300 μA, TA = –40°C to 85°C
1.7820
1.8180
VVREF = 1.7 V
0.4
0.8
mA
VTTREF OUTPUT
VVTTREF
Output voltage
VVDDQSNS/2
|IVTTREF| <100 μA, 1.2 V ≤ VVDDQSNS ≤ 1.8 V
49.2%
|IVTTREF| <10 mA, 1.2 V ≤ VVDDQSNS ≤ 1.8 V
49%
V
50.8%
VVTTREF
Output voltage tolerance to VVDDQ
IVTTREFOCLSRC
Source current limit
VVDDQSNS = 1.8 V, VVTTREF= 0 V
10
18
mA
IVTTREFOCLSNK
Sink current limit
VVDDQSNS = 1.8 V, VVTTREF = 1.8 V
10
17
mA
IVTTREFDIS
VTTREF discharge current
TA = 25°C, VS3 = VS5 = 0 V, VVTTREF = 0.5 V
0.8
1.3
mA
|IVTT| ≤ 10 mA, 1.2 V ≤ VVDDQSNS ≤ 1.8 V, IVTTREF= 0 A
–20
20
|IVTT| ≤ 1 A, 1.2 ≤ VVDDQSNS ≤ 1.8 V, IVTTREF= 0 A
–30
30
|IVTT| ≤ 2 A, 1.4 V ≤ VVDDQSNS ≤ 1.8 V, IVTTREF= 0 A
–40
40
|IVTT| ≤ 1.5 A, 1.2 V ≤ VVDDQSNS ≤ 1.4 V, IVTTREF= 0 A
–40
51%
VTT OUTPUT
VVTT
Output voltage
VVTTREF
V
VVTTTOL
Output voltage tolerance to VTTREF
IVTTOCLSRC
Source current limit
VVDDQSNS = 1.8 V, VVTT = VVTTSNS = 0.7 V, IVTTREF= 0 A
2
3
IVTTOCLSNK
Sink current limit
VVDDQSNS = 1.8V, VVTT = VVTTSNS = 1.1 V, IVTTREF= 0 A
2
3
IVTTLK
Leakage current
TA = 25°C , VS3 = 0 V, VS5 = 5 V, VVTT = VVTTREF
IVTTSNSBIAS
VTTSNS input bias current
VS3 = 5 V, VS5 = 5 V, VVTTSNS = VVTTREF
–0.5
0.0
0.5
IVTTSNSLK
VTTSNS leakage current
VS3 = 0 V, VS5 = 5 V, VVTTSNS = VVTTREF
–1
0
1
IVTTDIS
VTT Discharge current
TA = 25°C, VS3 = VS5 = 0 V, VVDDQSNS = 1.8 V,
VVTT = 0.5 V, IVTTREF= 0 A
mV
40
A
5
7.8
μA
mA
VDDQ OUTPUT
VVDDQSNS
VDDQ sense voltage
VVDDQSNSTOL
VDDQSNS regulation voltage
tolerance to REFIN
VREFIN
TA = 25°C
IVDDQSNS
VDDQSNS input current
VVDDQSNS = 1.8 V
IREFIN
REFIN input current
VREFIN = 1.8 V
IVDDQDIS
VDDQ discharge current
VS3 = VS5 = 0 V, VVDDQSNS = 0.5 V, MODE pin pulled
down to GND through 47kΩ (Non-tracking)
12
mA
IVLDOINDIS
VLDOIN discharge current
VS3 = VS5 = 0 V, VVDDQSNS = 0.5 V, MODE pin pulled
down to GND through 100kΩ (Non-tracking)
1.2
A
–3
3
μA
39
–0.1
0.0
mV
0.1
μA
SWITCH MODE POWER SUPPLY (SMPS) FREQUENCY
VIN = 12 V, VVDDQSNS = 1.8 V, RMODE = 100 kΩ
300
VIN = 12 V, VVDDQSNS = 1.8 V, RMODE = 200 kΩ
400
VIN = 12 V, VVDDQSNS = 1.8 V, RMODE = 1 kΩ
500
VIN = 12 V, VVDDQSNS = 1.8 V, RMODE = 12 kΩ
670
fSW
VDDQ switching frequency
tON(min)
Minimum on time
DRVH rising to falling (1)
tOFF(min)
Minimum off time
DRVH falling to rising
(1)
4
kHz
60
200
320
450
ns
Ensured by design. Not production tested.
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Copyright © 2010–2011, Texas Instruments Incorporated
TPS51916
SLUSAE1B – DECEMBER 2010 – REVISED AUGUST 2011
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
over operating free-air temperature range, VV5IN = 5 V, VLDOIN is connected to VDDQ output, VMODE= 0 V, VS3= VS5= 5 V
(unless otherwise noted)
PARAMETER
TEST CONDITION
MIN
TYP
MAX
Source, IDRVH = –50 mA
1.6
3.0
Sink, IDRVH = 50 mA
0.6
1.5
Source, IDRVL = –50 mA
0.9
2.0
Sink, IDRVL = 50 mA
0.5
1.2
DRVH-off to DRVL-on
10
DRVL-off to DRVH-on
20
UNIT
VDDQ MOSFET DRIVER
RDRVH
RDRVL
tDEAD
DRVH resistance
DRVL resistance
Dead time
Ω
ns
INTERNAL BOOT STRAP SW
VFBST
Forward Voltage
VV5IN-VBST, TA = 25°C, IF = 10 mA
IVBSTLK
VBST leakage current
TA = 25°C, VVBST = 33 V, VSW = 28 V
0.1
0.2
V
0.01
1.5
μA
μA
LOGIC THRESHOLD
IMODE
VTHMODE
MODE source current
MODE threshold voltage
VIL
S3/S5 low-level voltage
VIH
S3/S5 high-level voltage
VIHYST
S3/S5 hysteresis voltage
IILK
S3/S5 input leak current
14
15
16
MODE 0-1
109
129
149
MODE 1-2
235
255
275
MODE 2-3
392
412
432
MODE 3-4
580
600
620
MODE 4-5
829
854
879
MODE 5-6
1202
1232
1262
MODE 6-7
1760
1800
1840
mV
0.5
1.8
V
0.25
–1
0
1
μA
SOFT START
tSS
VDDQ soft-start time
Internal soft-start time, CVREF = 0.1 μF,
S5 rising to VVDDQSNS > 0.99 × VREFIN
1.1
ms
PGOOD COMPARATOR
VTHPG
VDDQ PGOOD threshold
IPG
PGOOD sink current
tPGDLY
PGOOD delay time
tPGSSDLY
PGOOD start-up delay
Copyright © 2010–2011, Texas Instruments Incorporated
PGOOD in from higher
106%
108%
PGOOD in from lower
90%
92%
94%
PGOOD out to higher
114%
116%
118%
PGOOD out to lower
82%
84%
86%
3
5.9
0.8
1
VPGOOD = 0.5 V
Delay for PGOOD in
110%
mA
1.2
ms
Delay for PGOOD out, with 100 mV over drive
330
ns
CVREF = 0.1 μF, S5 rising to PGOOD rising
2.5
ms
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TPS51916
SLUSAE1B – DECEMBER 2010 – REVISED AUGUST 2011
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ELECTRICAL CHARACTERISTICS (continued)
over operating free-air temperature range, VV5IN = 5 V, VLDOIN is connected to VDDQ output, VMODE= 0 V, VS3= VS5= 5 V
(unless otherwise noted)
PARAMETER
TEST CONDITION
MIN
TYP
MAX
9
10
11
UNIT
PROTECTIONS
ITRIP
TRIP source current
TCITRIP
TRIP source current temperature
coefficient (2)
VTRIP
VTRIP voltage range
VOCL
Current limit threshold
VOCLN
Negative current limit threshold
VZC
TA = 25°C, VTRIP = 0.4 V
4700
0.2
ppm/°C
3
VTRIP = 3.0 V
360
375
390
VTRIP = 1.6 V
190
200
210
VTRIP = 0.2 V
20
25
30
VTRIP = 3.0 V
–390
–375
–360
VTRIP = 1.6 V
–210
–200
–190
VTRIP = 0.2 V
–30
–25
–20
Wake-up
4.2
4.4
4.5
Shutdown
3.7
3.9
4.1
118%
120%
122%
Zero cross detection offset
0
VUVLO
V5IN UVLO threshold voltage
VOVP
VDDQ OVP threshold voltage
OVP detect voltage
tOVPDLY
VDDQ OVP propagation delay
With 100 mV over drive
VUVP
VDDQ UVP threshold voltage
UVP detect voltage
tUVPDLY
VDDQ UVP delay
tUVPENDLY
VDDQ UVP enable delay
VOOB
OOB Threshold voltage
68%
V
mV
mV
mV
430
66%
μA
V
ns
70%
1
ms
1.2
ms
108%
THERMAL SHUTDOWN
TSDN
(2)
6
Thermal shutdown threshold
Shutdown temperature (2)
Hysteresis (2)
140
10
°C
Ensured by design. Not production tested.
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Copyright © 2010–2011, Texas Instruments Incorporated
TPS51916
SLUSAE1B – DECEMBER 2010 – REVISED AUGUST 2011
www.ti.com
DEVICE INFORMATION
PGOOD
MODE
TRIP
S3
S5
RUK PACKAGE (TOP VIEW)
20
19
18
17
16
VTTSNS
1
15
VBST
VLDOIN
2
14
DRVH
VTT
3
13
SW
VTTGND
4
12
V5IN
11
DRVL
7
8
REFIN
9
10
PGND
6
GND
5
VDDQSNS
Thermal Pad
VREF
VTTREF
TPS51916
PIN FUNCTIONS
PIN
I/O
DESCRIPTION
NAME
NO.
DRVH
14
O
High-side MOSFET gate driver output.
DRVL
11
O
Low-side MOSFET gate driver output.
GND
7
–
Signal ground.
MODE
19
I
Connect resistor to GND to configure switching frequency, control mode and discharge mode. (See Table 2)
PGND
10
–
Gate driver power ground. RDS(on) current sensing input(+).
PGOOD
20
O
Powergood signal open drain output. PGOOD goes high when VDDQ output voltage is within the target range.
REFIN
8
I
Reference input for VDDQ. Connect to the midpoint of a resistor divider from VREF to GND. Add a capacitor for
stable operation.
SW
13
S3
17
I
S3 signal input. (See Table 1)
S5
16
I
S5 signal input. (See Table 1)
TRIP
18
I
Connect resistor to GND to set OCL at VTRIP/8. Output 10-μA current at room temperature, TC = 4700 ppm/°C.
VBST
15
I
High-side MOSFET gate driver bootstrap voltage input. Connect a capacitor from the VBST pin to the SW pin.
VDDQSNS
9
I
VDDQ output voltage feedback. Reference input for VTTREF. Also serves as power supply for VTTREF.
VLDOIN
2
I
Power supply input for VTT LDO. Connect VDDQ in typical application.
VREF
6
O
1.8-V reference output.
VTT
3
O
VTT 2-A LDO output. Need to connect 10 μF or larger capacitance for stability.
VTTGND
4
–
Power ground for VTT LDO.
VTTREF
5
O
Buffered VTT reference output. Need to connect 0.22 μF or larger capacitance for stability.
VTTSNS
1
I
VTT output voltage feedback.
V5IN
12
I
5-V power supply input for internal circuits and MOSFET gate drivers.
Thermal
pad
–
–
Thermal pad. Connect directly to system GND plane with multiple vias.
I/O High-side MOSFET gate driver return. RDS(on) current sensing input(–).
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FUNCTIONAL BLOCK DIAGRAM
VREFIN –32%
+
UV
+
OV
VREFIN +8/16 %
20 PGOOD
+
Delay
+
VREFIN +20%
VREFIN –8/16 %
15 mA
REFIN
8
VREF
6
UVP
+
+
PWM
19 MODE
15 VBST
9
14 DRVH
10 mA
13 SW
8R
+
TRIP 18
OC
XCON
+
S5 16
7R
tON
OneShot
R
S3 17
GND
Control Mode
On-Time
Discharge Type
Selection
OVP
Reference
Soft-Start
VDDQSNS
Control Logic
NOC
+
7
12 V5IN
R
11 DRVL
+
ZC
VTT Discharge
VDDQ
Discharge V5OK VTTREF Discharge
VTTREF
5
10
PGND
2
VLDOIN
3
VTT
4
VTTGND
+
+
+
VTTSNS
+
4.4 V/3.9 V
1
+
TPS51916
UDG-10135
8
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TPS51916
SLUSAE1B – DECEMBER 2010 – REVISED AUGUST 2011
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TYPICAL CHARACTERISTICS
10
V5IN Shutdown Current (µA)
V5IN Suppy Current (µA)
1000
800
600
400
200
0
−50
−25
0
25
50
75
Junction Temperature (°C)
100
4
2
−25
0
25
50
75
Junction Temperature (°C)
100
125
Figure 2. V5IN Shutdown Current vs Junction Temperature
10
16
14
8
TRIP Source Current (µA)
VLDOIN Suppy Current (µA)
6
0
−50
125
Figure 1. V5IN Supply Current vs Junction Temperature
6
4
2
12
10
8
6
0
−50
−25
0
25
50
75
Junction Temperature (°C)
100
4
−50
125
Figure 3. VLDOIN Supply Current vs Junction
Temperature
0
25
50
75
Junction Temperature (°C)
100
125
130
120
110
100
90
80
70
60
−25
0
25
50
75
Junction Temperature (°C)
100
125
Figure 5. OVP/UVP Threshold vs Junction Temperature
Copyright © 2010–2011, Texas Instruments Incorporated
VDDQSNS Discharge Current (mA)
15
OVP
UVP
140
50
−50
−25
Figure 4. Current Sense Current vs Junction Temperature
150
OVP/UVP Threshold (%)
8
12
9
6
3
0
−50
−25
0
25
50
75
Junction Temperature (°C)
100
125
Figure 6. VDDQSNS Discharge Current vs Junction
Temperature
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TYPICAL CHARACTERISTICS (continued)
800
8
Switching Frequency (kHz)
VTT Discharge Current (mA)
10
6
4
2
700
600
500
400
300
0
−50
−25
0
25
50
75
Junction Temperature (°C)
100
200
125
Figure 7. VTT Discharge Current vs Junction Temperature
500
400
Switching Frequency (kHz)
Switching Frequency (kHz)
600
300
12
14
16
Input Voltage (V)
18
20
22
VVDDQ = 1.20 V
VVDDQ = 1.35 V
VVDDQ = 1.50 V
600
500
400
300
6
8
10
12
14
16
Input Voltage (V)
18
20
200
22
6
8
10
12
14
16
Input Voltage (V)
18
20
22
Figure 10. Switching Frequency vs Input Voltage
800
800
RMODE = 100 kΩ
VIN = 12 V
700
700
600
500
400
300
VVDDQ = 1.20 V
VVDDQ = 1.35 V
VVDDQ = 1.50 V
RMODE = 12 kΩ
IVDDQ = 5 A
6
8
10
12
14
16
Input Voltage (V)
18
20
Figure 11. Switching Frequency vs Input Voltage
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Switching Frequency (kHz)
Switching Frequency (kHz)
10
RMODE = 1 kΩ
IVDDQ = 5 A
700
Figure 9. Switching Frequency vs Input Voltage
10
8
800
VVDDQ = 1.20 V
VVDDQ = 1.35 V
VVDDQ = 1.50 V
RMODE = 200 kΩ
IVDDQ = 10 A
700
200
6
Figure 8. Switching Frequency vs Input Voltage
800
200
VVDDQ = 1.20 V
VVDDQ = 1.35 V
VVDDQ = 1.50 V
RMODE = 100 kΩ
IVDDQ = 10 A
VVDDQ = 1.20 V
VVDDQ = 1.35 V
VVDDQ = 1.50 V
600
500
400
300
200
100
0
0
2
4
6
8
10
12
14
VDDQ Output Current (A)
16
18
20
Figure 12. Switching Frequency vs Load Current
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TYPICAL CHARACTERISTICS (continued)
800
800
600
500
400
300
200
100
0
600
500
400
300
200
0
2
4
6
8
10
12
14
VDDQ Output Current (A)
16
18
0
20
800
1.55
700
1.54
600
500
400
RMODE = 1 kΩ
VIN = 12 V
300
200
VVDDQ = 1.20 V
VVDDQ = 1.35 V
VVDDQ = 1.50 V
100
0
2
4
6
VDDQ Output Current (A)
8
0
4
6
VDDQ Output Current (A)
8
10
RMODE = 200 kΩ
VIN = 12 V
1.53
1.52
1.51
1.50
1.49
1.48
1.47
1.46
1.45
10
0
Figure 15. Switching Frequency vs Load Current
2
4
6
8
10
12
14
VDDQ Output Current (A)
16
18
20
Figure 16. Load Regulation
1.55
0.770
IVDDQ = 0 A
IVDDQ = 20 A
RMODE = 200 kΩ
1.54
0.765
1.53
VTTREF Voltage (V)
VDDQ Output Voltage (V)
2
Figure 14. Switching Frequency vs Load Current
VDDQ Output Voltage (V)
Switching Frequency (kHz)
VVDDQ = 1.20 V
VVDDQ = 1.35 V
VVDDQ = 1.50 V
100
Figure 13. Switching Frequency vs Load Current
0
RMODE = 1 kΩ
VIN = 12 V
700
Switching Frequency (kHz)
700
Switching Frequency (kHz)
VVDDQ = 1.20 V
VVDDQ = 1.35 V
VVDDQ = 1.50 V
RMODE = 200 kΩ
VIN = 12 V
1.52
1.51
1.50
1.49
1.48
0.760
0.755
0.750
0.745
0.740
1.47
1.46
0.735
1.45
0.730
−10
VVDDQ = 1.5 V
6
8
10
12
14
16
Input Voltage (V)
18
Figure 17. Line Regulation
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20
22
−5
0
VTTREF Current (mA)
5
10
Figure 18. VTTREF Load Regulation
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TYPICAL CHARACTERISTICS (continued)
0.695
0.620
0.690
0.615
VTTREF Voltage (V)
VTTREF Voltage (V)
0.685
0.680
0.675
0.670
0.665
0.660
0.655
0.610
0.605
0.600
0.595
0.590
0.585
VVDDQ = 1.35 V
0.650
−10
−5
VVDDQ = 1.2 V
0
VTTREF Current (mA)
5
0.580
−10
10
−5
5
10
Figure 20. VTTREF Load Regulation
0.790
0.715
0.780
0.705
0.770
0.695
VTT Voltage (V)
VTT Voltage (V)
Figure 19. VTTREF Load Regulation
0
VTTREF Current (mA)
0.760
0.750
0.740
0.730
0.685
0.675
0.665
0.655
0.720
0.645
VVDDQ = 1.5 V
0.710
−2.0
−1.5
−1.0
−0.5
0.0
0.5
VTT Current (A)
1.0
1.5
VVDDQ = 1.35 V
0.635
−2.0 −1.5 −1.0
2.0
Figure 21. VTT Load Regulation
−0.5
0.0
0.5
VTT Current (A)
1.0
1.5
2.0
Figure 22. VTT Load Regulation
0.640
100
0.630
90
80
70
Efficiency (%)
VTT Voltage (V)
0.620
0.610
0.600
0.590
60
50
40
30
0.580
20
0.570
VVDDQ = 1.2 V
0.560
−2.0 −1.5 −1.0
10
−0.5
0.0
0.5
VTT Current (A)
1.0
Figure 23. VTT Load Regulation
12
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1.5
2.0
VVDDQ = 1.5 V
RMODE = 200 kΩ
0
0.001
0.01
0.1
1
VDDQ Output Current (A)
VIN = 20 V
VIN = 12 V
VIN = 8 V
10
100
Figure 24. Efficiency
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TYPICAL CHARACTERISTICS (continued)
Figure 25. 1.5-V Load Transient Response
Figure 26. VTT Load Transient Response
Figure 27. 1.5-V Startup Waveforms
Figure 28. 1.5-V Startup Waveforms (0.5-V Pre-Biased)
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TYPICAL CHARACTERISTICS (continued)
180
80
180
60
135
60
135
40
90
40
90
20
45
20
45
0
0
0
0
−40
−60
−80
100
−20
−45
−90
−40
−90
−135
−60
−45
VIN = 12 V
IVDDQ = 10 A
Gain
Phase
Gain
Phase
IVTT = −1 A
1000
10000
Frequency (Hz)
100000
−180
1000000
−80
10000
100000
1000000
Frequency (Hz)
Gain (dB)
Figure 31. VDDQ Bode Plot
−180
10000000
Figure 32. VTT Bode Plot (Sink)
80
180
60
135
40
90
20
45
0
0
−20
−45
−40
−90
−60
Gain
Phase
IVTT = 1 A
−80
10000
−135
Phase (°)
−20
Gain (dB)
80
Phase (°)
Figure 30. 1.5-V Soft-Stop Waveforms (Non-Tracking
Discharge)
Phase (°)
Gain (dB)
Figure 29. 1.5-V Soft-Stop Waveforms (Tracking
Discharge)
−135
−180
10000000
100000
1000000
Frequency (Hz)
Figure 33. VTT Bode Plot (Source)
14
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APPLICATION INFORMATION
VDDQ Switch Mode Power Supply Control
The TPS51916 supports two SMPS control architectures, D-CAP™ mode and D-CAP2™ mode. Both control
modes do not require complex external compensation networks and are suitable for designs with small external
components counts. The D-CAP™ mode provides fast transient response with appropriate amount of equivalent
series resistance (ESR) on the output capacitors. The D-CAP2™ mode is dedicated for a configuration with very
low ESR output capacitors such as multi-layer ceramic capacitors (MLCC). For the both modes, an adaptive
on-time control scheme is used to achieve pseudo-constant frequency. The TPS51916 adjusts the on-time (tON)
to be inversely proportional to the input voltage (VIN) and proportional to the output voltage (VVDDQ). This makes
a switching frequency fairy constant over the variation of input voltage at the steady state condition. These
control modes and switching frequencies are selected by the MODE pin described in Table 2.
VREF and REFIN, VDDQ Output Voltage
The part provides a 1.8-V, ±0.8% accurate, voltage reference from VREF. This output has a 300-μA (max)
current capability to drive the REFIN input voltage through a voltage divider circuit. A capacitor with a value of
0.1-μF or larger should be attached close to the VREF terminal.
The VDDQ switch-mode power supply (SMPS) output voltage is defined by REFIN voltage, within the range
between 0.7 V and 1.8 V, programmed by the resister-divider connected between VREF and GND. (See External
Components Selection section.) A few nano farads of capacitance from REFIN to GND is recommended for
stable operation.
Soft-Start and Powergood
Provide a voltage supply to VIN and V5IN before asserting S5 to high. TPS51916 provides integrated VDDQ
soft-start functions to suppress in-rush current at start-up. The soft-start is achieved by controlling internal
reference voltage ramping up. Figure 34 shows the start-up waveforms. The switching regulator waits for 400μs
after S5 assertion. The MODE pin voltage is read in this period. A typical VDDQ ramp up duration is 700μs.
TPS51916 has a powergood open-drain output that indicates the VDDQ voltage is within the target range. The
target voltage window and transition delay times of the PGOOD comparator are ±8% (typ) and 1-ms delay for
assertion (low to high), and ±16% (typ) and 330-ns delay for de-assertion (high to low) during running. The
PGOOD start-up delay is 2.5 ms after S5 is asserted to high. Note that the time constant which is composed of
the REFIN capacitor and a resistor divider needs to be short enough to reach the target value before PGOOD
comparator enabled.
S5
VREF
VDDQ
PGOOD
400 ms
700 ms
1.4 ms
UDG-10137
Figure 34. Typical Start-up Waveforms
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Power State Control
The TPS51916 has two input pins, S3 and S5, to provide simple control scheme of power state. All of VDDQ,
VTTREF and VTT are turned on at S0 state (S3=S5=high). In S3 state (S3=low, S5=high), VDDQ and VTTREF
voltages are kept on while VTT is turned off and left at high impedance state (high-Z). The VTT output floats and
does not sink or source current in this state. In S4/S5 states (S3=S5=low), all of the three outputs are turned off
and discharged to GND according to the discharge mode selected by MODE pin. Each state code represents as
follow; S0 = full ON, S3 = suspend to RAM (STR), S4 = suspend to disk (STD), S5 = soft OFF. (See Table 1)
Table 1. S3/S5 Power State Control
STATE
S3
S5
VREF
VDDQ
VTTREF
S0
HI
HI
ON
ON
ON
VTT
ON
S3
LO
HI
ON
ON
ON
OFF(High-Z)
S4/S5
LO
LO
OFF
OFF(Discharge)
OFF(Discharge)
OFF(Discharge)
MODE Pin Configuration
The TPS51916 reads the MODE pin voltage when the S5 signal is raised high and stores the status in a register.
A 15-μA current is sourced from the MODE pin during this time to read the voltage across the resistor connected
between the pin and GND. Table 2 shows resistor values, corresponding control mode, switching frequency and
discharge mode configurations.
Table 2. MODE Selection
MODE NO.
RESISTANCE BETWEEN
MODE AND GND (kΩ)
CONTROL
MODE
7
200
400
6
100
300
5
68
4
47
400
3
33
500
2
22
1
12
0
1
D-CAP™
D-CAP2™
SWITCHING
FREQUENCY (kHz)
DISCHARGE MODE
Tracking
300
Non-tracking
670
670
500
Tracking
Discharge Control
In S4/S5 state, VDDQ, VTT, and VTTREF outputs are discharged based on the respective discharge mode
selected above. The tracking discharge mode discharges VDDQ output through the internal VTT regulator
transistors enabling quick discharge operation. The VTT output maintains tracking of the VTTREF voltage in this
mode. (Please refer to Figure 29) After 4 ms of tracking discharge operation, the mode changes to non-tracking
discharge. The VDDQ output must be connected to the VLDOIN pin in this mode. The non-tracking mode
discharges the VDDQ and VTT pins using internal MOSFETs that are connected to corresponding output
terminals. The non-tracking discharge is slow compared with the tracking discharge due to the lower current
capability of these MOSFETs. (Please refer to Figure 30)
16
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D-CAP™ Mode
Figure 35 shows a simplified model of D-CAP™ mode architecture.
VIN
VDDQSNS
DRVH
9
14
Lx
PWM
+
REFIN
Control
Logic
and
Driver
8
R1 VREF
R2
DRVL
1.8 V
VDDQ
ESR
6
+
High-Side
MOSFET
11
Low-Side
MOSFET
RLOAD
COUT
UDG-10136
Figure 35. Simplified D-CAP™ Model
The VDDQSNS voltage is compared with REFIN voltage. The PWM comparator creates a set signal to turn on
the high-side MOSFET. The gain and speed of the comparator is high enough to maintain the voltage at the
beginning of each on-cycle (or the end of each off-cycle) to be substantially constant. The DC output voltage
monitored at VDDQ may have line regulation due to ripple amplitude that slightly increases as the input voltage
increase. The D-CAP™ mode offers flexibility on output inductance and capacitance selections with ease-of-use
without complex feedback loop calculation and external components. However, it does require a sufficient level
of ESR that represents inductor current information for stable operation and good jitter performance. Organic
semiconductor capacitor(s) or specialty polymer capacitor(s) are recommended.
The requirement for loop stability is simple and is described in Equation 1. The 0-dB frequency, f0 defined in
Equation 1, is recommended to be lower than 1/3 of the switching frequency to secure proper phase margin.
f
1
£ SW
f0 =
2p ´ ESR ´ COUT
3
where
•
•
•
ESR is the effective series resistance of the output capacitor
COUT is the capacitance of the output capacitor
fsw is switching frequency
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Jitter is another attribute caused by signal-to-noise ratio of the feedback signal. One of the major factors that
determine jitter performance in D-CAP™ mode is the down-slope angle of the VDDQSNS ripple voltage.
Figure 36 shows, in the same noise condition, that jitter is improved by making the slope angle larger.
VVDDQSNS
Slope (1)
Jitter
(2)
Slope (2)
Jitter
20 mV
(1)
VREFIN
VREFIN +Noise
tON
tOFF
UDG-10139
Figure 36. Ripple Voltage Slope and Jitter Performance
For a good jitter performance, use the recommended down slope of approximately 20 mV per switching period as
shown in Figure 36 and Equation 2.
VOUT ´ ESR
³ 20mV
fSW ´ L X
where
•
•
18
VOUT is the VDDQ output voltage
LX is the inductance
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D-CAP2™ Mode Operation
Figure 37 shows simplified model of D-CAP2™ architecture.
VIN
VDDQSNS
CC1
SW
RC1
9
13
CC2
RC2
DVRH
14
G
+
–
+
REFIN
PWM
Comparator
8
R1
Control
Logic
and
Driver
LX
VDDQ
DVRL
11
COUT
RLOAD
VREF
6
+
R2
1.8 V
TPS51916
UDG-10198
Figure 37. Simplified Modulator Using D-CAP2™ Mode
The D-CAP2™ mode in the TPS51916 includes an internal feedback network enabling the use of very low ESR
output capacitor(s) such as multi-layer ceramic capacitors. The role of the internal network is to sense the ripple
component of the inductor current information and combine it with voltage feedback signal. Using RC1=RC2≡RC
and CC1=CC2≡CC, 0-dB frequency of the D-CAP2™ mode is given by Equation 3. It is recommended that the
0-dB frequency (f0) be lower than 1/3 of the switching frequency to secure the proper phase margin
RC ´ CC
f
£ SW
f0 =
2p ´ G ´ L X ´ COUT
3
where
•
G is gain of the amplifier which amplifies the ripple current information generated by the compensation
circuit
(3)
The typical G value is 0.25, and typical RCCC time constant values for 500 kHz and 670 kHz operation are 23 µs
and 14.6 µs, respectively.
For example, when fSW=500 kHz and LX=1 µH, COUT should be larger than 88 µF.
When selecting the capacitor, pay attention to its characteristics. For MLCC use X5R or better dielectric and
consider the derating of the capacitance by both DC bias and AC bias. When derating by DC bias and AC bias
are 80% and 50%, respectively, the effective derating is 40% because 0.8 x 0.5 = 0.4. The capacitance of
specialty polymer capacitors may change depending on the operating frequency. Consult capacitor
manufacturers for specific characteristics.
Light-Load Operation
In auto-skip mode, the TPS51916 SMPS control logic automatically reduces its switching frequency to improve
light-load efficiency. To achieve this intelligence, a zero cross detection comparator is used to prevent negative
inductor current by turning off the low-side MOSFET. Equation 4 shows the boundary load condition of this skip
mode and continuous conduction operation.
ILOAD(LL) =
(VIN - VOUT ) ´ VOUT ´
2 ´ LX
VIN
1
fSW
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VTT and VTTREF
TPS51916 integrates two high performance, low-drop-out linear regulators, VTT and VTTREF, to provide
complete DDR2/DDR3/DDR3L power solutions. The VTTREF has a 10-mA sink/source current capability, and
tracks ½ of VDDQSNS with ±1% accuracy using an on-chip ½ divider. A 0.22-μF (or larger) ceramic capacitor
must be connected close to the VTTREF terminal for stable operation. The VTT responds quickly to track
VTTREF within ±40 mV at all conditions, and the current capability is 2 A for both sink and source. A 10-μF (or
larger) ceramic capacitor(s) need to be connected close to the VTT terminal for stable operation. To achieve tight
regulation with minimum effect of wiring resistance, a remote sensing terminal, VTTSNS, should be connected to
the positive node of VTT output capacitor(s) as a separate trace from the high-current line to the VTT pin.
(Please refer to the Layout Considerations section for details.)
VDDQ Overvoltage and Undervoltage Protection
The TPS51916 sets the overvoltage protection (OVP) when VDDQSNS voltage reaches a level 20% (typ) higher
than the REFIN voltage. When an OV event is detected, the controller changes the output target voltage to 0 V.
This usually turns off DRVH and forces DRVL to be on. When the inductor current begins to flow through the
low-side MOSFET and reaches the negative OCL, DRVL is turned off and DRVH is turned on, for a minimum
on-time.
After the minimum on-time expires, DRVH is turned off and DRVL is turned on again. This action minimizes the
output node undershoot due to LC resonance. When the VDDQSNS reaches 0 V, the driver output is latched as
DRVH off, DRVL on. VTTREF and VTT are turned off and discharged using the non-tracking discharge
MOSFETs regardless of the tracking mode.
The undervoltage protection (UVP) latch is set when the VDDQSNS voltage remains lower than 68% (typ) of the
REFIN voltage for 1 ms or longer. In this fault condition, the controller latches DRVH low and DRVL low and
discharges the VDDQ, VTT and VTTREF outputs. UVP detection function is enabled after 1.2 ms of SMPS
operation to ensure startup.
To release the OVP and UVP latches, toggle S5 or adjust the V5IN voltage down and up beyond the
undervoltage lockout threshold.
VDDQ Out-of-Bound Operation
When the output voltage rises to 8% above the target value, the out-of-bound operation starts. During the
out-of-bound condition, the controller operates in forced PWM-only mode. Turning on the low-side MOSFET
beyond the zero inductor current quickly discharges the output capacitor. During this operation, the
cycle-by-cycle negative overcurrent limit is also valid. Once the output voltage returns to within regulation range,
the controller resumes to auto-skip mode.
VDDQ Overcurrent Protection
The VDDQ SMPS has cycle-by-cycle overcurrent limiting protection. The inductor current is monitored during the
off-state using the low-side MOSFET RDS(on), and the controller maintains the off-state when the inductor current
is larger than the overcurrent trip level. The current monitor circuit inputs are PGND and SW pins so that those
should be properly connected to the source and drain terminals of low-side MOSFET. The overcurrent trip level,
VOCTRIP, is determined by Equation 5, where RTRIP is the value of the resistor connected between the TRIP pin
and GND, and ITRIP is the current sourced from the TRIP pin. ITRIP is 10 μA typically at room temperature, and
has 4700ppm/°C temperature coefficient to compensate the temperature dependency of the low-side MOSFET
RDS(on).
I
VOCTRIP = RTRIP ´ TRIP
8
(5)
Because the comparison is done during the off-state, VOCTRIP sets the valley level of the inductor current. The
load current OCL level, IOCL, can be calculated by considering the inductor ripple current as shown in Equation 6.
æV
IOCL = ç OCTRIP
ç RDS(on )
è
ö I
æ
÷ + IND(ripple) = ç VOCTRIP
÷
ç RDS(on )
2
ø
è
ö 1 V -V
VOUT
OUT
÷ + ´ IN
´
÷ 2
LX
fSW ´ VIN
ø
where
•
20
IIND(ripple) is inductor ripple current
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In an overcurrent condition, the current to the load exceeds the current to the output capacitor, thus the output
voltage tends to fall down. Eventually, it crosses the undervoltage protection threshold and shuts down.
VTT Overcurrent Protection
The LDO has an internally fixed constant overcurrent limiting of 3-A (typ) for both sink and source operation.
V5IN Undervoltage Lockout Protection
The TPS51916 has a 5-V supply undervoltage lockout protection (UVLO) threshold. When the V5IN voltage is
lower than UVLO threshold voltage, typically 3.9 V, VDDQ, VTT and VTTREF are shut off. This is a non-latch
protection.
Thermal Shutdown
The TPS51916 includes an internal temperature monitor. If the temperature exceeds the threshold value, 140°C
(typ), VDDQ, VTT and VTTREF are shut off. The state of VDDQ is open, and that of VTT and VTTREF are high
impedance (high-Z) at thermal shutdown. The discharge functions of all outputs are disabled. This is a non-latch
protection and the operation is restarted with soft-start sequence when the device temperature is reduced by
10°C (typ).
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External Components Selection
The external components selection is simple in D-CAP™ mode.
1. DETERMINE THE VALUE OF R1 AND R2
The output voltage is determined by the value of the voltage-divider resistor, R1 and R2 as shown in Figure 35.
R1 is connected between VREF and REFIN pins, and R2 is connected between the REFIN pin and GND. Setting
R1 as 10-kΩ is a good starting point. Determine R2 using Equation 7.
R1
R2 =
æ
ö
ç
÷
ç
÷
1.8
ç
÷ -1
æ IIND(ripple ) ´ ESR ö ÷
ç
÷÷
ç VOUT - ç
ç
÷÷
2
ç
è
øø
è
(7)
2. CHOOSE THE INDUCTOR
The inductance value should be determined to yield a ripple current of approximately ¼ to ½ of maximum output
current. Larger ripple current increases output ripple voltage and improves the signal-to-noise ratio and helps
stable operation.
LX =
1
IIND(ripple ) ´ fSW
IN(max ) - VOUT
´
(V
VIN(max )
)´ V
OUT
=
3
IO(max ) ´ fSW
IN(max ) - VOUT
´
(V
VIN(max )
)´ V
OUT
(8)
The inductor needs a low direct current resistance (DCR) to achieve good efficiency, as well as enough room
above peak inductor current before saturation. The peak inductor current can be estimated in Equation 9.
(
IIND(peak ) =
)
VIN(max ) - VOUT ´ VOUT
RTRIP ´ ITRIP
1
+
´
8 ´ RDS(on )
L ´ fSW
VIN(max )
(9)
3. CHOOSE THE OCL SETTING RESISTANCE, RTRIP
Combining Equation 5 and Equation 6, RTRIP can be obtained using Equation 10.
RTRIP
æ
ö
æ (V - VOUT ) ö
VOUT
÷ ´ RDS(on)
´
8 ´ ç IOCL - ç IN
÷
ç (2 ´ L X ) ÷ (fSW ´ VIN ) ÷
ç
è
ø
è
ø
=
ITRIP
(10)
4. CHOOSE THE OUTPUT CAPACITORS
D-CAP™ Mode
Organic semiconductor capacitor(s) or specialty polymer capacitor(s) are recommended. Determine ESR to meet
small signal stability and recommended ripple voltage. A quick reference is shown in Equation 11 and
Equation 12.
f
1
£ SW
2p ´ ESR ´ COUT
3
(11)
VOUT ´ ESR
³ 20mV
fSW ´ L X
(12)
D-CAP2™ Mode
Determine output capacitance to meet small signal stability as shown in Equation 13.
22
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Copyright © 2010–2011, Texas Instruments Incorporated
TPS51916
SLUSAE1B – DECEMBER 2010 – REVISED AUGUST 2011
www.ti.com
RC ´ CC
f
£ SW
2p ´ G ´ L X ´ COUT
3
where
•
•
RC×CC time constant is 23 µs for 500 kHz operation (or 14.6 µs for 670 kHz operation)
G = 0.25
(13)
TPS51916 Application Circuits
V5IN
4.5 V to 5.5
V
R2 200 kW
R1
100 kW
R3 36 kW
S5
S3
16
MODE
TRIP
S3
S5
1
VTTSNS
2
VLDOIN
3
VTT
4
VTTGND
5
VTTREF
DRVH 14
U1
TPS51916RUK
R6
0W
C5
0.1 mF
C7
0.1 mF
C8
10 mF
C9
10 mF
C10
10 mF
R7 0 W
PGND
Q1
FDMS8680
L1
0.56 mH
VDDQ
1.5 V/20 A
SW 13
V5IN 12
PGND
VTTREF
0.75 V
VIN
8 V to 20 V
VBST 15
VDDQSNS
PGND
17
REFIN
VTTGND
18
GND
C1
10 mF
19
VREF
VTT
0.75 V/2 A
20
PGOOD
PGND
21
PwPad
AGND
C12
10 mF
6
7
8
9
10
Q2
FDMS8670AS
DRVL 11
Q3
FDMS8670AS
C6
1 mF
C11
330 mF
VDDQ_GND
R4
10 kW
C2
C3
0.22 mF 0.1 mF
R5
49 kW
C4
10 nF
PGND
UDG-10195
AGND
PGND
Figure 38. DDR3, D-CAP™ 400-kHz Application Circuit, Tracking Discharge
Table 3. DDR3, D-CAP™ 400-kHz Application Circuit, List of Materials
REFERENCE
DESIGNATOR
QTY
SPECIFICATION
MANUFACTURE
PART NUMBER
Taiyo Yuden
TMK325BJ106MM
C8, C9, C10
3
10 µF, 25 V
C11
1
330 µF, 2V, 6 mΩ
Panasonic
EEFSX0D331XE
L1
1
0.56 µH, 21 A, 1.56 mΩ
Panasonic
ETQP4LR56WFC
Q1
1
30 V, 35 A, 8.5 mΩ
Fairchild
FDMS8680
Q2, Q3
2
30 V, 42 A, 3.5 mΩ
Fairchild
FDMS8670AS
Copyright © 2010–2011, Texas Instruments Incorporated
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TPS51916
SLUSAE1B – DECEMBER 2010 – REVISED AUGUST 2011
V5IN
4.5 V to 5.5
V
www.ti.com
R2 1 kW
R1
100 kW
R3 36 kW
S5
S3
16
MODE
TRIP
S3
S5
1
VTTSNS
2
VLDOIN
DRVH 14
U1
TPS51916RUK
VTT
4
VTTGND
5
VTTREF
C7
0.1 mF
C5
0.1 mF
R7 0 W
Q1
FDMS8680
V5IN 12
6
7
8
9
10
VTTREF
0.75 V
R6
0W
C8
10 mF
C9
10 mF
L1
1 mH
PGND
VDDQ
1.5 V/10 A
SW 13
PGND
3
VIN
8 V to 20 V
VBST 15
VDDQSNS
PGND
17
REFIN
VTTGND
18
GND
C1
10 mF
19
VREF
VTT
0.75 V/2 A
20
PGOOD
PGND
21
PwPad
AGND
C12
10 mF
Q2
FDMS8670AS
DRVL 11
C6
1 mF
C10
4 x 47 mF
VDDQ_GND
R4
10 kW
C2
C3
0.22 mF 0.1 mF
C4
10 nF
PGND
R5
49.9 kW
UDG-10196
AGND PGND
Figure 39. DDR3, DCAP-2™ 500-kHz Application Circuit, Tracking Discharge
Table 4. DDR3, DCAP-2™ 500-kHz Application Circuit, List of Materials
REFERENCE
DESIGNATOR
QTY
SPECIFICATION
MANUFACTURE
PART NUMBER
C8, C9
2
10 µF, 25 V
Taiyo Yuden
TMK325BJ106MM
C10
4
47 µF, 6.3 V
TDK
C2012X5R0J476M
L1
1
1 µH, 18.5 A, 2.3 mΩ
NEC Tokin
MPC1055L1R0C
Q1
1
30 V, 35 A, 8.5 mΩ
Fairchild
FDMS8680
Q2
1
30 V, 42 A, 3.5 mΩ
Fairchild
FDMS8670AS
24
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Copyright © 2010–2011, Texas Instruments Incorporated
TPS51916
SLUSAE1B – DECEMBER 2010 – REVISED AUGUST 2011
www.ti.com
Layout Considerations
Certain issues must be considered before designing a layout using the TPS51916.
2
VLDOIN
VTT
VTT
TPS51916
VIN
3
10 mF
VTTGND
VTTGND
4
V5IN
VTTREF
#2
1 mF
5
VOUT
DRVL
MODE
0.22 mF
#1
12
11
19
TRIP
#3
PGND
18
10
VREF
6
REFIN
8
GND
7
0.1 mF
10 nF
AGND
UDG-10197
PGND
Figure 40. DC/DC Converter Ground System
•
•
•
•
VIN capacitor(s), VOUT capacitor(s) and MOSFETs are the power components and should be placed on one
side of the PCB (solder side). Other small signal components should be placed on another side (component
side). At least one inner system GND plane should be inserted, in order to shield and isolate the small signal
traces from noisy power lines.
All sensitive analog traces and components such as VDDQSNS, VTTSNS, MODE, REFIN, VREF and TRIP
should be placed away from high-voltage switching nodes such as SW, DRVL, DRVH or VBST to avoid
coupling. Use internal layer(s) as system GND plane(s) and shield feedback trace from power traces and
components.
The DC/DC converter has several high-current loops. The area of these loops should be minimized in order to
suppress generating switching noise.
– The most important loop to minimize the area of is the path from the VIN capacitor(s) through the high and
low-side MOSFETs, and back to the negative node of the VIN capacitor(s). Connect the negative node of
the VIN capacitor(s) and the source of the low-side MOSFET as close as possible. (Refer to loop #1 of
Figure 40)
– The second important loop is the path from the low-side MOSFET through inductor and VOUT
capacitor(s), and back to source of the low-side MOSFET. Connect the source of the low-side MOSFET
and negative node of VOUT capacitor(s) as close as possible. (Refer to loop #2 of Figure 40)
– The third important loop is of gate driving system for the low-side MOSFET. To turn on the low-side
MOSFET, high current flows from V5IN capacitor through gate driver and the low-side MOSFET, and back
to negative node of the capacitor. To turn off the low-side MOSFET, high current flows from gate of the
low-side MOSFET through the gate driver and PGND pin, and back to source of the low-side MOSFET.
Connect negative node of V5IN capacitor, source of the low-side MOSFET and PGND pin as close as
possible. (Refer to loop #3 of Figure 40)
Connect negative nodes of the VTTREF output capacitor, VREF capacitor and REFIN capacitor and
bottom-side resistance of VREF voltage-divider to GND pin as close as possible. The negative node of the
Copyright © 2010–2011, Texas Instruments Incorporated
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25
TPS51916
SLUSAE1B – DECEMBER 2010 – REVISED AUGUST 2011
•
•
•
•
•
•
•
•
•
•
26
www.ti.com
VTT output capacitor(s), VTTGND, GND and PGND pins should be connected to system GND plane near the
device as shown in Figure 40.
Because the TPS51916 controls output voltage referring to voltage across VOUT capacitor, VDDQSNS
should be connected to the positive node of VOUT capacitor using different trace from that for VLDOIN.
Remember that this sensing potential is the reference voltage of VTTREF. Avoid any noise generative lines.
GND pin refers to the negative node of VOUT capacitor.
Connect the overcurrent setting resistor from TRIP pin to GND pin and make the connections as close as
possible to the device to avoid coupling from a high-voltage switching node.
Connect the frequency and mode setting resistor from MODE pin to GND pin ground, and make the
connections as close as possible to the device to avoid coupling from a high-voltage switching node.
Connections from gate drivers to the respective gate of the high-side or the low-side MOSFET should be as
short as possible to reduce stray inductance. Use 0.65 mm (25 mils) or wider trace and via(s) of at least 0.5
mm (20 mils) diameter along this trace.
The PCB trace defined as SW node, which connects to the source of the high-side MOSFET, the drain of the
low-side MOSFET and the high-voltage side of the inductor, should be as short and wide as possible.
VLDOIN should be connected to VOUT with short and wide traces. An input bypass capacitor should be
placed as close as possible to the pin with short and wide connections. The negative node of the capacitor
should be connected to system GND plane.
The output capacitor for VTT should be placed close to the pins with a short and wide connection in order to
avoid additional ESR and/or ESL of the trace.
VTTSNS should be connected to the positive node of the VTT output capacitor(s) using a separate trace from
the high-current power line. When remote sensing is required attach the output capacitor(s) at that point.
Also, it is recommended to minimize any additional ESR and/or ESL of ground trace between GND pin and
the output capacitor(s).
Consider adding a low pass filter (LPF) at VTTSNS in case the ESR of the VTT output capacitor(s) is larger
than 2 mΩ.
In order to effectively remove heat from the package, prepare a thermal land and solder to the package
thermal pad. Wide trace of the component-side copper, connected to this thermal land, helps heat spreading.
Numerous vias with a 0.3-mm diameter connected from the thermal land to the internal/solder-side ground
plane(s) should be used to help dissipation. The thermal land can be connected to either AGND or PGND but
is recommended to be connected to PGND, the system GND plane(s), which has better heat radiation.
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Copyright © 2010–2011, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
8-Sep-2011
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package
Drawing
Pins
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
(3)
TPS51916RUKR
ACTIVE
QFN
RUK
20
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
TPS51916RUKT
ACTIVE
QFN
RUK
20
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
Samples
(Requires Login)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Dec-2011
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
TPS51916RUKR
QFN
RUK
20
3000
330.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
TPS51916RUKT
QFN
RUK
20
250
180.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Dec-2011
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS51916RUKR
QFN
RUK
20
3000
346.0
346.0
29.0
TPS51916RUKT
QFN
RUK
20
250
210.0
185.0
35.0
Pack Materials-Page 2
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