3N165, 3N166 MONOLITHIC DUAL P-CHANNEL ENHANCEMENT MODE MOSFET Linear Integrated Systems FEATURES VERY HIGH INPUT IMPEDANCE HIGH GATE BREAKDOWN ULTRA LOW LEAKAGE LOW CAPACITANCE ABSOLUTE MAXIMUM RATINGS (NOTE 1) (TA= 25°C unless otherwise noted) Drain-Source or Drain-Gate Voltage (NOTE 2) 3N165 3N166 Transient G-S Voltage (NOTE 3) Gate-Gate Voltage Drain Current (NOTE 2) Storage Temperature Operating Temperature Lead Temperature (Soldering, 10 sec.) Power Dissipation (One Side) Total Derating above 25°C 1 7 C G2 G1 40 V 30 V ±125 V ±80 V 50 mA -65°C to +200°C -55°C to +150°C +300°C 300 mW 4.2 mW/°C 5 3 D2 D1 S 8 4 Device Schematic TO-99 Bottom View ELECTRICAL CHARACTERISTICS (TA=25°C and VBS=0 unless otherwise specified) SYMBOL CHARACTERISTICS LIMITS MIN. MAX. UNITS CONDITIONS IGSSR Gate Reverse Leakage Current -- 10 VGS= 40 V IGSSF Gate Forward Leakage Current -- -10 VGS= -40 V -- -25 IDSS Drain to Source Leakage Current -- -200 VDS= -20 V ISDS Source to Drain Leakage Current -- -400 VSD= -20 V VDB= 0 ID(on) On Drain Current -5 -30 mA VDS= -15 V VGS= -10 V VGS(th) Gate Source Threshold Voltage -2 -5 V VDS= -15 V ID= -10 µA VGS(th) Gate Source Threshold Voltage -2 -5 V VDS= VGS ID= -10 µA rDS(on) Drain Source ON Resistance -- 300 ohms VGS= -20 V ID= -100 µA gfs Forward Transconductance 1500 3000 µs VDS= -15V ID= -10mA f=1kHz gos Output Admittance -- 300 µs Ciss Input Capacitance -- 3.0 Crss Reverse Transfer Capacitance -- 0.7 VDS= -15V ID= -10mA f=1MHz Coss Output Capacitance -- 3.0 RE(Yfs) Common Source Forward Transconductance 1200 ID= -10mA f=100MHz -- pA pF TA=+125°C (NOTE 4) µs VDS= -15V (NOTE 4) Linear Integrated Systems 4042 Clipper Ct., Fremont, CA 94538 TEL: (510) 490-9160 • FAX: (510) 353-0261 MATCHING CHARACTERISTICS 3N165 LIMITS MIN. MAX. SYMBOL CHARACTERISTICS Yfs1/Yfs2 Forward Transconductance Ratio VGS1-2 0.90 1.0 Gate Source Threshold Voltage Differential -- 100 ∆VGS1-2/∆T Gate Source Threshold Voltage Differential -- 100 UNITS CONDITIONS VDS= -15 V ID= -500 µA mV VDS= -15 V ID= -500 µA µV/°C VDS= -15 V IA= -500 µA Change with Temperature f=1kHz TA= -55°C to = +25°C TYPICAL SWITCHING WAVEFORM VDD 10% 10% R1 tr R2 VOUT t on 90% 10% 10% t off 50 Ω INPUT PULSE Rise Time ≤2ns Pulse Width ≥200ns Switching Times Test Circuit SAMPLING SCOPE Tr ≤0.2ns CIN≤2pF RIN≥10M Switching Times Test Circuit NOTES: 1. MOS field-effect transistors have extremely high input resistance and can be damaged by the accumulation of excess static charge. To avoid possible damage to the device while wiring, testing, or in actual operation, follow these procedures: To avoid the build-up of static charge, the leads of the devices should remain shorted together with a metal ring except when being tested or used. Avoid unnecessary handling. Pick up devices by the case instead of the leads. Do not insert or remove devices from circuits with the power on, as transient voltages may cause permanant damage to the devices. 2. Per transistor. 3. Devices must mot be tested at ±125V more than once, nor for longer than 300ms. 4. For design reference only, not 100% tested. Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Linear Integrated Systems 4042 Clipper Ct., Fremont, CA 94538 TEL: (510) 490-9160 • FAX: (510) 353-0261