LMU18 LMU18 DEVICES INCORPORATED 16 x 16-bit Parallel Multiplier 16 x 16-bit Parallel Multiplier DEVICES INCORPORATED FEATURES DESCRIPTION ❑ 35 ns Worst-Case Multiply Time ❑ Low Power CMOS Technology ❑ Full 32-bit Output Port — No Multiplexing Required ❑ Two’s Complement, Unsigned, or Mixed Operands ❑ Three-State Outputs ❑ 84-pin PLCC, J-Lead The LMU18 is a high-speed, low power 16-bit parallel multiplier. The LMU18 is an 84-pin device which provides simultaneous access to all outputs. The LMU18 produces the 32-bit product of two 16-bit numbers. Data present at the A inputs, along with the TCA control bit, is loaded into the A register on the rising edge of CLK. B data and the TCB control bit are similarly loaded. Loading of the A and B registers is controlled LMU18 BLOCK DIAGRAM TCA A 15-0 TCB B 15-0 16 CLK ENA 16 A REGISTER B REGISTER RND REGISTER ENB FORMAT ADJUST 16 16 FT ENR RESULT REGISTER MSPSEL OEM OEL 16 16 R 31 R 31-16 RND is loaded on the rising edge of CLK, providing either ENA or ENB are LOW. RND, when HIGH, adds ‘1’ to the most significant bit position of the least significant half of the product. Subsequent truncation of the 16 least significant bits produces a result correctly rounded to 16-bit precision. At the output, the Right Shift control (RS) selects either of two output formats. RS LOW produces a 31-bit product with a copy of the sign bit inserted in the MSB postion of the least significant half. RS HIGH gives a full 32-bit product. Two 16-bit output registers are provided to hold the most and least significant halves of the result (MSP and LSP) as defined by RS. These registers are loaded on the rising edge of CLK, subject to the ENR control. When ENR is HIGH, clocking of the result registers is prevented. For asynchronous output these registers may be made transparent by setting the feed through control (FT) HIGH and ENR LOW. 32 RS by the ENA and ENB controls. When HIGH, these controls prevent application of the clock to the respective register. The TCA and TCB controls specify the operands as two’s complement when HIGH, or unsigned magnitude when LOW. The two halves of the product may be routed to a single 16-bit three-state output port (MSP) via a multiplexer. MSPSEL LOW causes the MSP outputs to be driven by the most significant half of the result. MSPSEL HIGH routes the least significant half of the result to the MSP pins. The MSB of the result is available in both true and complemented form to aid implementation of higher precision multipliers. R 15-0 Multipliers 1 08/16/2000–LDS.18-O LMU18 DEVICES INCORPORATED FIGURE 1A. 16 x 16-bit Parallel Multiplier INPUT FORMATS AIN BIN Fractional Two’s Complement (TCA, TCB = 1) 15 14 13 –20 2–1 2–2 2 1 0 2–13 2–14 2–15 15 14 13 –20 2–1 2–2 (Sign) 2 1 0 2–13 2–14 2–15 (Sign) Integer Two’s Complement (TCA, TCB = 1) 15 14 13 –215 214 213 2 1 0 22 21 20 15 14 13 –215 214 213 (Sign) 2 1 0 22 21 20 (Sign) Unsigned Fractional (TCA, TCB = 0) 15 14 13 2–1 2–2 2–3 2 1 0 2–14 2–15 2–16 15 14 13 2–1 2–2 2–3 2 1 0 2–14 2–15 2–16 Unsigned Integer (TCA, TCB = 0) 15 14 13 215 214 213 FIGURE 1B. 2 1 0 22 21 20 15 14 13 215 214 213 2 1 0 22 21 20 OUTPUT FORMATS MSP LSP Fractional Two’s Complement (RS = 0) 31 30 29 –20 2–1 2–2 18 17 16 2–13 2–14 2–15 15 14 13 –20 2–16 2–17 (Sign) 2 1 0 2–28 2–29 2–30 (Sign) Fractional Two’s Complement (RS = 1) 31 30 29 –21 20 2–1 18 17 16 2–12 2–13 2–14 15 14 13 2–15 2–16 2–17 2 1 0 2–28 2–29 2–30 (Sign) Integer Two’s Complement (RS = 1) 31 30 29 –231 230 229 18 17 16 218 217 216 15 14 13 215 214 213 2 1 0 22 21 20 (Sign) Unsigned Fractional (RS = 1) 31 30 29 2–1 2–2 2–3 18 17 16 2–14 2–15 2–16 15 14 13 2–17 2–18 2–19 2 1 0 2–30 2–31 2–32 Unsigned Integer (RS = 1) 31 30 29 231 230 229 18 17 16 218 217 216 15 14 13 215 214 213 2 1 0 22 21 20 Multipliers 2 08/16/2000–LDS.18-O LMU18 DEVICES INCORPORATED 16 x 16-bit Parallel Multiplier MAXIMUM RATINGS Above which useful life may be impaired (Notes 1, 2, 3, 8) Storage temperature ........................................................................................................... –65°C to +150°C Operating ambient temperature ........................................................................................... –55°C to +125°C VCC supply voltage with respect to ground ............................................................................ –0.5 V to +7.0 V Input signal with respect to ground ........................................................................................ –3.0 V to +7.0 V Signal applied to high impedance output ............................................................................... –3.0 V to +7.0 V Output current into low outputs ............................................................................................................. 25 mA Latchup current ............................................................................................................................... > 400 mA OPERATING CONDITIONS To meet specified electrical and switching characteristics Mode Temperature Range (Ambient) Active Operation, Commercial Active Operation, Military Supply Voltage 0°C to +70°C 4.75 V ≤ VCC ≤ 5.25 V –55°C to +125°C 4.50 V ≤ VCC ≤ 5.50 V ELECTRICAL CHARACTERISTICS Over Operating Conditions (Note 4) Symbol Parameter Test Condition Min VOH Output High Voltage VCC = Min., IOH = –2.0 mA 2.4 VOL Output Low Voltage VCC = Min., IOL = 8.0 mA VIH Input High Voltage VIL Input Low Voltage (Note 3) IIX Input Current IOZ Typ Max Unit V 0.5 V 2.0 VCC V 0.0 0.8 V Ground ≤ VIN ≤ VCC (Note 12) ±20 µA Output Leakage Current Ground ≤ VOUT ≤ VCC (Note 12) ±20 µA ICC1 VCC Current, Dynamic (Notes 5, 6) 45 mA ICC2 VCC Current, Quiescent (Note 7) 1.5 mA 25 Multipliers 3 08/16/2000–LDS.18-O LMU18 DEVICES INCORPORATED 16 x 16-bit Parallel Multiplier SWITCHING CHARACTERISTICS COMMERCIAL OPERATING RANGE (0°C to +70°C) Notes 9, 10 (ns) Symbol Parameter tMC Clocked Multiply Time tMUC Unclocked Multiply Time tPW Clock Pulse Width tS Input Setup Time tH Input Hold Time tD Output Delay tSEL Output Select Delay tENA Three-State Output Enable Delay (Note 11) tDIS Three-State Output Disable Delay (Note 11) 123456789012 123456789012 123456789012 65* 123456789012 123456789012 Min Max 123456789012 123456789012 123456789012 65 123456789012 123456789012 123456789012 85 123456789012 123456789012 123456789012 15 123456789012 123456789012 123456789012 15 123456789012 123456789012 5 123456789012 123456789012 123456789012 30 123456789012 123456789012 123456789012 25 123456789012 123456789012 123456789012 25 123456789012 123456789012 123456789012 24 123456789012 LMU18– 45 Min 35 Max Min Max 45 35 65 55 15 15 15 12 5 5 30 28 25 25 20 20 20 20 123456789012 123456789012 123456789012 20* 123456789012 123456789012 Min Max 123456789012 123456789012 123456789012 20 123456789012 123456789012 123456789012 30 123456789012 123456789012 123456789012 9 123456789012 123456789012 123456789012 11 123456789012 123456789012 1 123456789012 123456789012 123456789012 18 123456789012 123456789012 123456789012 18 123456789012 123456789012 123456789012 18 123456789012 123456789012 123456789012 18 123456789012 MILITARY OPERATING RANGE (–55°C to +125°C) Notes 9, 10 (ns) Symbol Parameter tMC Clocked Multiply Time tMUC Unclocked Multiply Time tPW Clock Pulse Width tS Input Setup Time tH Input Hold Time tD Output Delay tSEL Output Select Delay tENA Three-State Output Enable Delay (Note 11) tDIS Three-State Output Disable Delay (Note 11) LMU18– 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123456789012345678901234567890121234567890123 5 5 5 2 123456789012345678901234567890121234567890123 123456789012345678901234567890121234567890123 123456789012345678901234567890121234567890123 35 35 33 20 123456789012345678901234567890121234567890123 123456789012345678901234567890121234567890123 30 30 30 20 123456789012345678901234567890121234567890123 123456789012345678901234567890121234567890123 123456789012345678901234567890121234567890123 25 20 20 20 123456789012345678901234567890121234567890123 123456789012345678901234567890121234567890123 123456789012345678901234567890121234567890123 24 20 20 20 123456789012345678901234567890121234567890123 SWITCHING WAVEFORMS tS tH INPUT ENA, ENB tS tH ENR tPW tPW tPW CLOCK tD tMC tMUC MSPSEL tSEL OEM OEL tDIS R31-0 tENA HIGH IMPEDANCE 123456789012345678901234 123456789012345678901234 123456789012345678901234 *DISCONTINUED SPEED GRADE Multipliers 4 08/16/2000–LDS.18-O LMU18 DEVICES INCORPORATED 16 x 16-bit Parallel Multiplier NOTES 1. Maximum Ratings indicate stress specifications only. Functional operation of these products at values beyond those indicated in the Operating Conditions table is not implied. Exposure to maximum rating conditions for extended periods may affect reliability. 9. AC specifications are tested with input transition times less than 3 ns, output reference levels of 1.5 V (except tDIS test), and input levels of nominally 0 to 3.0 V. Output loading may be a resistive divider which provides for specified IOH and IOL at an output voltage of VOH min and VOL max 2. The products described by this spec- respectively. Alternatively, a diode ification include internal circuitry de- bridge with upper and lower current signed to protect the chip from damagsources of I OH and I OL respectively, ing substrate injection currents and ac- and a balancing voltage of 1.5 V may be cumulations of static charge. Neverthe- used. Parasitic capacitance is 30 pF less, conventional precautions should minimum, and may be distributed. be observed during storage, handling, and use of these circuits in order to This device has high-speed outputs caavoid exposure to excessive electrical pable of large instantaneous current stress values. pulses and fast turn-on/turn-off times. As a result, care must be exercised in the 3. This device provides hard clamping of testing of this device. The following transient undershoot and overshoot. In- measures are recommended: put levels below ground or above VCC will be clamped beginning at –0.6 V and a. A 0.1 µF ceramic capacitor should be VCC + 0.6 V. The device can withstand installed between VCC and Ground indefinite operation with inputs in the leads as close to the Device Under Test range of –0.5 V to +7.0 V. Device opera- (DUT) as possible. Similar capacitors tion will not be adversely affected, how- should be installed between device VCC ever, input current levels will be well in and the tester common, and device ground and tester common. excess of 100 mA. 4. Actual test conditions may vary from b. Ground and VCC supply planes those designated but operation is guar- must be brought directly to the DUT anteed as specified. socket or contactor fingers. 5. Supply current for a given applica- c. Input voltages should be adjusted to tion can be accurately approximated by: compensate for inductive ground and VCC noise to maintain required DUT input NCV2 F levels relative to the DUT ground pin. 4 where 10. Each parameter is shown as a min- 11. For the tENA test, the transition is measured to the 1.5 V crossing point with datasheet loads. For the tDIS test, the transition is measured to the ±200mV level from the measured steady-state output voltage with ±10mA loads. The balancing voltage, V TH , is set at 3.5 V for Z-to-0 and 0-to-Z tests, and set at 0 V for Zto-1 and 1-to-Z tests. 12. These parameters are only tested at the high temperature extreme, which is the worst case for leakage current. FIGURE A. OUTPUT LOADING CIRCUIT S1 DUT IOL VTH CL IOH FIGURE B. THRESHOLD LEVELS tENA OE Z tDIS 1.5 V 1.5 V 3.5V Vth 0 1.5 V 1.5 V Z 1 VOL* 0.2 V VOH* 0.2 V 0 Z 1 Z 0V Vth VOL* Measured VOL with IOH = –10mA and IOL = 10mA VOH* Measured VOH with IOH = –10mA and IOL = 10mA imum or maximum value. Input requirements are specified from the point of view of the external system driving the chip. Setup time, for example, is specified as a minimum since the exter6. Tested with all outputs changing ev- nal system must supply at least that ery cycle and no load, at a 5 MHz clock much time to meet the worst-case requirements of all parts. Responses from rate. the internal circuitry are specified from 7. Tested with all inputs within 0.1 V of the point of view of the device. Output VCC or Ground, no load. delay, for example, is specified as a 8. These parameters are guaranteed maximum since worst-case operation of any device always provides data within but not 100% tested. that time. N = total number of device outputs C = capacitive load per output V = supply voltage F = clock frequency Multipliers 5 08/16/2000–LDS.18-O LMU18 DEVICES INCORPORATED 16 x 16-bit Parallel Multiplier ORDERING INFORMATION B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 84-pin 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 12 74 13 73 14 72 15 71 16 70 17 69 18 68 19 67 20 66 Top View 21 22 23 65 64 63 24 62 25 61 26 60 27 59 28 58 29 57 30 56 31 55 32 54 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 A11 A12 A13 A14 A15 ENA RND TCA TCB VCC GND GND MSPSEL FT RS OEM ENR R31 R31 R30 R29 R10 R11 R12 R13 R14 R15 VCC GND R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 B10 B11 B12 B13 B14 B15 ENB CLK OEL GND VCC R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 Plastic J-Lead Chip Carrier (J3) Speed 0°C to +70°C — COMMERCIAL SCREENING 45 ns 35 ns LMU18JC45 LMU18JC35 Multipliers 6 08/16/2000–LDS.18-O LMU18 DEVICES INCORPORATED 16 x 16-bit Parallel Multiplier 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 ORDERING INFORMATION 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 84-pin 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 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1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 F 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 GND GND RND R0 ENB VCC (i.e., Component Side Pinout) 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 G 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 R3 RS FT MSPSEL R1 R2 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 H 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 ENR OEM R5 R4 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 J 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 R17 R18 R22 R30 R31 R8 R6 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 K 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 R7 R10 R11 R14 GND VCC R21 R24 R27 R29 R31 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 L 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 R12 R13 R15 R16 R19 R20 R23 R25 R26 R28 R9 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 Discontinued Package 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 Ceramic Pin Grid Array (G3) Speed 0°C to +70°C — COMMERCIAL SCREENING –55°C to +125°C — COMMERCIAL SCREENING –55°C to +125°C — MIL-STD-883 COMPLIANT Multipliers 7 08/16/2000–LDS.18-O