LPR520 LPR520 DEVICES INCORPORATED 4 x 16-bit Multilevel Pipeline Register 4 x 16-bit Multilevel Pipeline Register DEVICES INCORPORATED FEATURES DESCRIPTION ❑ Four 16-bit Registers ❑ Implements Double 2-Stage Pipeline or Single 4-Stage Pipeline Register The LPR520 is functionally compatible with the L29C520 but have 16-bit inputs and outputs. The LPR520 is implemented in low power CMOS. ❑ Hold, Shift, and Load Instructions ❑ Separate Data In and Data Out Pins ❑ High-Speed, Low Power CMOS Technology The LPR520 contains four registers which can be configured as two independent, 2-level pipelines or as one 4-level pipeline. ❑ Three-State Outputs ❑ 44-pin PLCC, J-Lead The Instruction pins, I1-0, control the loading of the registers. The registers may be configured as a four-stage delay line, with data loaded into R1 and shifted sequentially through R2, R3, and R4. Also, data may be loaded from the inputs into either R1 or R3 with only R2 or R4 shifting. Finally, I1-0 may be set to prevent any register from changing. TABLE 1. LPR520 INSTRUCTION TABLE MUX I1 I0 Description L L D➞R1 R1➞R2 R2➞R3 R3➞R4 L H HOLD HOLD D➞R3 R3➞R4 H L D➞R1 R1➞R2 HOLD HOLD H H ALL REGISTERS ON HOLD 16 Y15-0 OE REGISTER 4 REGISTER 3 REG 1 REG 2 REG 3 REG 4 MUX D15-0 REGISTER 2 REGISTER 1 LPR520 BLOCK DIAGRAM 16 The S1-0 select lines control a 4-to-1 multiplexer which routes the contents of any of the registers to the Y output pins. The independence of the I and S controls allows simultaneous write and read operations on different registers. 2 S1-0 TABLE 2. 2 I1-0 CLK OUTPUT SELECT S1 S0 Register Selected L L Register 4 L H Register 3 H L Register 2 H H Register 1 Pipeline Registers 1 08/02/2000–LDS.P520-C LPR520 DEVICES INCORPORATED 4 x 16-bit Multilevel Pipeline Register MAXIMUM RATINGS Above which useful life may be impaired (Notes 1, 2, 3, 8) Storage temperature ........................................................................................................... –65°C to +150°C Operating ambient temperature ........................................................................................... –55°C to +125°C VCC supply voltage with respect to ground ............................................................................ –0.5 V to +7.0 V Input signal with respect to ground ........................................................................................ –3.0 V to +7.0 V Signal applied to high impedance output ............................................................................... –3.0 V to +7.0 V Output current into low outputs ............................................................................................................. 25 mA Latchup current ............................................................................................................................... > 400 mA OPERATING CONDITIONS To meet specified electrical and switching characteristics Mode Temperature Range (Ambient) Active Operation, Commercial Active Operation, Military Supply Voltage 0°C to +70°C 4.75 V ≤ VCC ≤ 5.25 V –55°C to +125°C 4.50 V ≤ VCC ≤ 5.50 V ELECTRICAL CHARACTERISTICS Over Operating Conditions (Note 4) Symbol Parameter Test Condition Min VOH Output High Voltage VCC = Min., IOH = –2.0 mA 2.4 VOL Output Low Voltage VCC = Min., IOL = 8.0 mA VIH Input High Voltage VIL Input Low Voltage (Note 3) IIX Input Current IOZ Typ Max Unit V 0.5 V 2.0 VCC V 0.0 0.8 V Ground ≤ VIN ≤ VCC (Note 12) ±20 µA Output Leakage Current Ground ≤ VOUT ≤ VCC (Note 12) ±20 µA ICC1 VCC Current, Dynamic (Notes 5, 6) 40 mA ICC2 VCC Current, Quiescent (Note 7) 1.0 mA 10 Pipeline Registers 2 08/02/2000–LDS.P520-C LPR520 DEVICES INCORPORATED 4 x 16-bit Multilevel Pipeline Register SWITCHING CHARACTERISTICS COMMERCIAL OPERATING RANGE (0°C to +70°C) Notes 9, 10 (ns) Symbol LPR520– 1234567890123456 1234567890123456 1234567890123456 * 25 22 1234567890123456 1234567890123456 1234567890123456 Min Max Min Max 1234567890123456 1234567890123456 25 22 1234567890123456 1234567890123456 1234567890123456 1234567890123456 25 20 1234567890123456 1234567890123456 1234567890123456 10 10 1234567890123456 1234567890123456 1234567890123456 13 10 1234567890123456 1234567890123456 1234567890123456 3 3 1234567890123456 1234567890123456 1234567890123456 13 10 1234567890123456 1234567890123456 1234567890123456 1234567890123456 3 3 1234567890123456 1234567890123456 1234567890123456 25 21 1234567890123456 1234567890123456 1234567890123456 25 15 1234567890123456 Parameter tPD Clock to Output Delay tSEL Select to Output Delay tPW Clock Pulse Width tSI Instruction Setup Time tHI Instruction Hold Time tSD Data Setup Time tHD Data Hold Time tENA Three-State Output Enable Delay (Note 11) tDIS Three-State Output Disable Delay (Note 11) 1234567890123456 1234567890123456 1234567890123456 15* 1234567890123456 1234567890123456 1234567890123456 Min Max 1234567890123456 1234567890123456 15 1234567890123456 1234567890123456 1234567890123456 1234567890123456 15 1234567890123456 1234567890123456 1234567890123456 8 1234567890123456 1234567890123456 1234567890123456 6 1234567890123456 1234567890123456 1234567890123456 1 1234567890123456 1234567890123456 1234567890123456 6 1234567890123456 1234567890123456 1234567890123456 1234567890123456 1 1234567890123456 1234567890123456 1234567890123456 15 1234567890123456 1234567890123456 1234567890123456 12 1234567890123456 MILITARY OPERATING RANGE (–55°C to +125°C) Notes 9, 10 (ns) Symbol 1234567890123456789012345678901212345678901234 LPR520– 1234567890123456789012345678901212345678901234 1234567890123456789012345678901212345678901234 * 30 24* 18* 1234567890123456789012345678901212345678901234 1234567890123456789012345678901212345678901234 1234567890123456789012345678901212345678901234 Min Max Min Max Min Max 1234567890123456789012345678901212345678901234 1234567890123456789012345678901212345678901234 1234567890123456789012345678901212345678901234 30 24 18 1234567890123456789012345678901212345678901234 1234567890123456789012345678901212345678901234 1234567890123456789012345678901212345678901234 30 22 18 1234567890123456789012345678901212345678901234 1234567890123456789012345678901212345678901234 1234567890123456789012345678901212345678901234 15 10 9 1234567890123456789012345678901212345678901234 1234567890123456789012345678901212345678901234 1234567890123456789012345678901212345678901234 15 10 8 1234567890123456789012345678901212345678901234 1234567890123456789012345678901212345678901234 1234567890123456789012345678901212345678901234 1234567890123456789012345678901212345678901234 5 3 2 1234567890123456789012345678901212345678901234 1234567890123456789012345678901212345678901234 1234567890123456789012345678901212345678901234 15 10 8 1234567890123456789012345678901212345678901234 1234567890123456789012345678901212345678901234 1234567890123456789012345678901212345678901234 5 3 2 1234567890123456789012345678901212345678901234 1234567890123456789012345678901212345678901234 1234567890123456789012345678901212345678901234 25 22 16 1234567890123456789012345678901212345678901234 1234567890123456789012345678901212345678901234 1234567890123456789012345678901212345678901234 20 16 13 1234567890123456789012345678901212345678901234 1234567890123456789012345678901212345678901234 Parameter tPD Clock to Output Delay tSEL Select to Output Delay tPW Clock Pulse Width tSI Instruction Setup Time tHI Instruction Hold Time tSD Data Setup Time tHD Data Hold Time tENA Three-State Output Enable Delay (Note 11) tDIS Three-State Output Disable Delay (Note 11) SWITCHING WAVEFORMS I1-0 tSI tHI tSD tHD D15-0 tPW CLK tPW S1-0 tPD tSEL OE tDIS tENA HIGH IMPEDANCE Y15-0 123456789012345678901234 123456789012345678901234 123456789012345678901234 *DISCONTINUED SPEED GRADE Pipeline Registers 3 08/02/2000–LDS.P520-C LPR520 DEVICES INCORPORATED 4 x 16-bit Multilevel Pipeline Register NOTES 1. Maximum Ratings indicate stress specifications only. Functional operation of these products at values beyond those indicated in the Operating Conditions table is not implied. Exposure to maximum rating conditions for extended periods may affect reliability. 9. AC specifications are tested with input transition times less than 3 ns, output reference levels of 1.5 V (except tDIS test), and input levels of nominally 0 to 3.0 V. Output loading may be a resistive divider which provides for specified IOH and IOL at an output voltage of VOH min and VOL max 2. The products described by this spec- respectively. Alternatively, a diode ification include internal circuitry de- bridge with upper and lower current signed to protect the chip from damagsources of IOH and I OL respectively, ing substrate injection currents and ac- and a balancing voltage of 1.5 V may be cumulations of static charge. Neverthe- used. Parasitic capacitance is 30 pF less, conventional precautions should minimum, and may be distributed. be observed during storage, handling, and use of these circuits in order to This device has high-speed outputs caavoid exposure to excessive electrical pable of large instantaneous current stress values. pulses and fast turn-on/turn-off times. As a result, care must be exercised in the 3. This device provides hard clamping of testing of this device. The following transient undershoot and overshoot. In- measures are recommended: put levels below ground or above VCC will be clamped beginning at –0.6 V and a. A 0.1 µF ceramic capacitor should be VCC + 0.6 V. The device can withstand installed between VCC and Ground indefinite operation with inputs in the leads as close to the Device Under Test range of –0.5 V to +7.0 V. Device opera- (DUT) as possible. Similar capacitors tion will not be adversely affected, how- should be installed between device VCC ever, input current levels will be well in and the tester common, and device ground and tester common. excess of 100 mA. 4. Actual test conditions may vary from b. Ground and VCC supply planes those designated but operation is guar- must be brought directly to the DUT anteed as specified. socket or contactor fingers. 5. Supply current for a given applica- c. Input voltages should be adjusted to tion can be accurately approximated by: compensate for inductive ground and VCC noise to maintain required DUT input NCV2 F levels relative to the DUT ground pin. 4 where 10. Each parameter is shown as a minN = total number of device outputs C = capacitive load per output V = supply voltage F = clock frequency 6. Tested with all outputs changing every cycle and no load, at a 5 MHz clock rate. 7. Tested with all inputs within 0.1 V of VCC or Ground, no load. 8. These parameters are guaranteed but not 100% tested. 11. For the tENA test, the transition is measured to the 1.5 V crossing point with datasheet loads. For the tDIS test, the transition is measured to the ±200mV level from the measured steady-state output voltage with ±10mA loads. The balancing voltage, V TH , is set at 3.5 V for Z-to-0 and 0-to-Z tests, and set at 0 V for Zto-1 and 1-to-Z tests. 12. These parameters are only tested at the high temperature extreme, which is the worst case for leakage current. FIGURE A. OUTPUT LOADING CIRCUIT S1 DUT IOL VTH CL IOH FIGURE B. THRESHOLD LEVELS tENA OE Z tDIS 1.5 V 1.5 V 3.5V Vth 0 1.5 V 1.5 V Z 1 VOL* 0.2 V VOH* 0.2 V 0 Z 1 Z 0V Vth VOL* Measured VOL with IOH = –10mA and IOL = 10mA VOH* Measured VOH with IOH = –10mA and IOL = 10mA imum or maximum value. Input requirements are specified from the point of view of the external system driving the chip. Setup time, for example, is specified as a minimum since the external system must supply at least that much time to meet the worst-case requirements of all parts. Responses from the internal circuitry are specified from the point of view of the device. Output delay, for example, is specified as a maximum since worst-case operation of any device always provides data within that time. Pipeline Registers 4 08/02/2000–LDS.P520-C LPR520 DEVICES INCORPORATED Speed Plastic DIP (P3) D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 NC 7 6 5 4 3 2 1 44 43 42 41 40 39 8 38 9 37 10 36 11 Top View 12 13 35 34 33 14 32 15 31 16 30 17 29 18 19 20 21 22 23 24 25 26 27 28 NC Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 D13 D14 D15 CLK GND OE Y15 Y14 Y13 Y12 NC LPR520 — ORDERING INFORMATION 123456789012345678901234567890121234567890123456 123456789012345678901234567890121234567890123456 123456789012345678901234567890121234567890123456 123456789012345678901234567890121234567890123456 40-pin — 0.6" wide 44-pin 123456789012345678901234567890121234567890123456 123456789012345678901234567890121234567890123456 123456789012345678901234567890121234567890123456 123456789012345678901234567890121234567890123456 123456789012345678901234567890121234567890123456 123456789012345678901234567890121234567890123456 123456789012345678901234567890121234567890123456 123456789012345678901234567890121234567890123456 123456789012345678901234567890121234567890123456 123456789012345678901234567890121234567890123456 40 VCC I0 1 123456789012345678901234567890121234567890123456 123456789012345678901234567890121234567890123456 39 2 I1 S0 123456789012345678901234567890121234567890123456 123456789012345678901234567890121234567890123456 38 3 D0 S1 123456789012345678901234567890121234567890123456 123456789012345678901234567890121234567890123456 37 4 D1 Y0 123456789012345678901234567890121234567890123456 123456789012345678901234567890121234567890123456 36 5 D2 Y1 123456789012345678901234567890121234567890123456 123456789012345678901234567890121234567890123456 35 6 D3 Y2 123456789012345678901234567890121234567890123456 123456789012345678901234567890121234567890123456 34 7 D4 Y3 123456789012345678901234567890121234567890123456 123456789012345678901234567890121234567890123456 33 8 D5 Y4 123456789012345678901234567890121234567890123456 32 9 D6 Y5 123456789012345678901234567890121234567890123456 123456789012345678901234567890121234567890123456 31 10 D7 Y6 123456789012345678901234567890121234567890123456 123456789012345678901234567890121234567890123456 30 11 D8 Y7 123456789012345678901234567890121234567890123456 123456789012345678901234567890121234567890123456 29 12 D9 Y8 123456789012345678901234567890121234567890123456 123456789012345678901234567890121234567890123456 28 13 D10 Y9 123456789012345678901234567890121234567890123456 123456789012345678901234567890121234567890123456 27 14 D11 Y10 123456789012345678901234567890121234567890123456 123456789012345678901234567890121234567890123456 26 15 D12 Y11 123456789012345678901234567890121234567890123456 123456789012345678901234567890121234567890123456 25 16 D13 Y12 123456789012345678901234567890121234567890123456 24 17 D14 Y13 123456789012345678901234567890121234567890123456 123456789012345678901234567890121234567890123456 23 18 D15 Y14 123456789012345678901234567890121234567890123456 123456789012345678901234567890121234567890123456 22 19 CLK Y15 123456789012345678901234567890121234567890123456 123456789012345678901234567890121234567890123456 21 20 GND OE 123456789012345678901234567890121234567890123456 123456789012345678901234567890121234567890123456 123456789012345678901234567890121234567890123456 123456789012345678901234567890121234567890123456 123456789012345678901234567890121234567890123456 123456789012345678901234567890121234567890123456 123456789012345678901234567890121234567890123456 123456789012345678901234567890121234567890123456 123456789012345678901234567890121234567890123456 123456789012345678901234567890121234567890123456 123456789012345678901234567890121234567890123456 Discontinued Package 123456789012345678901234567890121234567890123456 123456789012345678901234567890121234567890123456 123456789012345678901234567890121234567890123456 123456789012345678901234567890121234567890123456 123456789012345678901234567890121234567890123456 123456789012345678901234567890121234567890123456 123456789012345678901234567890121234567890123456 123456789012345678901234567890121234567890123456 NC D2 D1 D0 I1 I0 VCC S0 S1 Y0 Y1 4 x 16-bit Multilevel Pipeline Register Plastic J-Lead Chip Carrier (J1) Ceramic DIP (C11) 0°C to +70°C — COMMERCIAL SCREENING 22 ns LPR520JC22 –55°C to +125°C — COMMERCIAL SCREENING –55°C to +125°C — MIL-STD-883 COMPLIANT Pipeline Registers 5 08/02/2000–LDS.P520-C