LOGIC L4C383JC20

L4C383
L4C383
DEVICES INCORPORATED
16-bit Cascadable ALU (Extended Set)
16-bit Cascadable ALU (Extended Set)
DEVICES INCORPORATED
FEATURES
DESCRIPTION
The L4C383 is a flexible, high speed,
cascadable 16-bit Arithmetic and Logic
Unit. The L4C383 is capable of
performing up to 32 different
arithmetic or logic functions.
❑ High-Speed (15ns), Low Power
16-bit Cascadable ALU
❑ Extended Function Set
(32 Advanced ALU Functions)
❑ All Registers Have a Bypass Path
for Complete Flexibility
The L4C383 can be cascaded to perform
32-bit or greater operations. See
“Cascading the L4C383” on the next
page.
❑ Replaces IDT7383
❑ 68-pin PLCC, J-Lead
ARCHITECTURE
bit result (F). Five select lines control
the ALU and provide 19 arithmetic and
13 logical functions. Registers are
provided on both the ALU inputs and
the output, but these may be bypassed
under user control. An internal feedback path allows the registered ALU
output to be routed to one or both of
the ALU inputs, accommodating chain
operations and accumulation.
ALU OPERATIONS
The L4C383 operates on two 16-bit
operands (A and B) and produces a 16-
L4C383 BLOCK DIAGRAM
The S4–S0 lines specify the operation to
be performed. The ALU functions and
their select codes are shown in Table 1.
ALU STATUS
A15-A0
B15-B0
16
16
A REGISTER
ENA
ENB
B REGISTER
FTAB
FFFFH
FFFFH
5
N, C16
OVF, Z
S4-0
4
ALU
C0
16
ENF
RESULT REGISTER
FTF
16
16
TO ALL REGISTERS
OPERAND REGISTERS
The L4C383 has two 16-bit wide input
registers for operands A and B. These
registers are rising edge triggered by a
common clock. The A register is
enabled for input by setting the ENA
control LOW, and the B register is
enabled for input by setting the ENB
control LOW. When either the ENA
control or ENB control is HIGH, the
data in the corresponding input register
will not change.
This architecture allows the L4C383 to
accept arguments from a single 16-bit
data bus. For those applications that do
not require registered inputs, both the
A and B operand registers can be
bypassed with the FTAB control line.
OE
CLK
The ALU provides Overflow and Zero
status bits. A Carry output is also
provided for cascading multiple
devices, however it is only defined for
the 19 arithmetic functions. The ALU
sets the Zero output when all 16 output
bits are zero. The N, C16 and OVF flags
for the arithmetic operations are
defined in Table 2.
F15-F0
Arithmetic Logic Units
1
08/16/2000–LDS.383-E
L4C383
DEVICES INCORPORATED
TABLE 1. ALU FUNCTIONS
S4-S0
FUNCTION
16-bit Cascadable ALU (Extended Set)
TABLE 2.
ALU STATUS FLAGS
Bit Carry Generate = gi = AiBi
Bit Carry Propagate = pi = Ai + Bi
for i = 0 ... 15
for i = 0 ... 15
P0 = p0
Pi = pi (Pi–1)
for i = 1 ... 15
00000
A + B + C0
00001
A OR B
00010
A + B + C0
00011
A + B + C0
00100
A + C0
00101
A OR F
00110
A – 1 + C0
00111
A + C0
01000
A + F + C0
01001
A OR F
then
01010
A + F + C0
01011
A + F + C0
01100
F + B + C0
01101
A OR B
C16
OVF
Zero
N =
01110
F + B + C0
01111
F + B + C0
OUTPUT REGISTER
10000
A XOR B
10001
A AND B
10010
A AND B
The output of the ALU drives the input of
a 16-bit register. This rising-edgetriggered register is clocked by the same
clock as the input registers. When the
ENF control is LOW, data from the ALU
will be clocked into the output register.
By disabling the output register, intermediate results can be held while loading
new input operands. Three-state drivers
controlled by the OE input allow the
L4C383 to be configured in a single
bidirectional bus system.
10011
A XNOR B
10100
A XOR F
10101
A AND F
10110
A AND F
10111
ALL 1's + C0
11000
B + C0
11001
A AND B
11010
B + C0
11011
B – 1 + C0
11100
F + C0
11101
A OR B
11110
F – 1 + C0
11111
F + C0
When the FTAB control is asserted
(FTAB = HIGH), data is routed
around the A and B input registers;
however, they continue to function
normally via the ENA and ENB
controls. The contents of the input
registers will again be available to the
ALU if the FTAB control is released.
and
G0 = g0
Gi = gi + pi (Gi–1)
Ci = Gi–1 + Pi–1 (C0)
for i = 1 ... 15
for i = 1 ... 15
= G15 + P15C0
= C15 XOR C16
= All Output Bits Equal Zero
Sign Bit of ALU Operation
The output register can be bypassed by
asserting the FTF control signal (FTF =
HIGH). When the FTF control is asserted,
output data is routed around the output
register, however, it continues to function
normally via the ENF control. The
contents of the output register will again
be available on the output pins if FTF is
released.
CASCADING THE L4C383
Cascading the L4C383 to 32 bits is
accomplished simply by connecting the
C16 output of the least significant slice to
the C0 input of the most sig-nificant slice.
The S4-S0, ENA, ENB, and ENF lines are
common to both devices. The Zero output
flags should be logically ANDed to
produce the Zero flag for the 32-bit result.
The OVF and C16 outputs of the most
significant slice are valid for the 32-bit
result.
Propagation delay calculations for this
configuration require two steps: First
determine the propagation delay from the
input of interest to the C16 output of the
lower slice. Add this number to the delay
from the C0 input of the upper slice to the
output of interest (of the C0 setup time, if
the F register is used). The sum gives the
overall input-to-output delay (or setup
time) for the 32-bit configuration. This
method gives a conservative result, since
the C16 output is very lightly loaded.
Formulas for calculation of all critical
delays for a 32-bit system are shown in
Figures 4A through 4D.
Cascading to greater than 32 bits can be
accomplished by simply connecting the
C16 output of each slice to the C0 input of
the next more significant slice.
Propagation delays are calculated as
for the 32-bit case, except that the C0
to C16 delays for all intermediate slices
must be added to the overall delay for
each path.
Arithmetic Logic Units
2
08/16/2000–LDS.383-E
L4C383
DEVICES INCORPORATED
FIGURE 4A.
16-bit Cascadable ALU (Extended Set)
FTAB = 0, FTF = 0
From
Clock
Clock
C0
S4-S0
A, B
C0
S4-S0
ENA, ENB, ENF
Minimum cycle time
To
➞ F
➞ Other
➞ Other
➞ Other
Setup time
Setup time
Setup time
Setup time
=
=
=
=
=
=
=
=
=
Calculated Specification Limit
Same as 16-bit case
(Clock ➞ C16) + (C0 ➞ Out)
(C0 ➞ C16) + (C0 ➞ Out)
(S4-S0 ➞ C16) + (C0 ➞ Out)
Same as 16-bit case
(C0 ➞ C16) + (C0 Setup time)
(S4-S0 ➞ C16) + (C0 Setup time)
Same as 16-bit case
(Clock ➞ C16) + (C0 Setup time)
A 31 -A 16
B 31 -B 16
A 15 -A 0
D
Q
D
D
Q
Q
B 15 -B 0
D
Q
CLOCK
C0, S 4 –S 0
A
B
C0
F
D
FIGURE 4B.
C 16
F
B
C0
D
CLOCK
Q
MOST
SIGNIFICANT
SLICE
A
CLOCK
Q
16
LEAST
SIGNIFICANT
SLICE
16
F 15 -F 0
F 31 -F 16
FTAB = 0, FTF = 1
From
Clock
Clock
C0
C0
S4-S0
S4-S0
A, B
C0
S4-S0
ENA, ENB, ENF
Minimum cycle time
To
➞ F
➞ Other
➞ F
➞ Other
➞ F
➞ Other
Setup time
Setup time
Setup time
Setup time
Calculated Specification Limit
(Clock ➞ C16) + (C0 ➞ F)
(Clock ➞ C16) + (C0 ➞ Out)
(C0 ➞ C16) + (C0 ➞ F)
(C0 ➞ C16) + (C0 ➞ Out)
(S4-S0 ➞ C16) + (C0 ➞ F)
(S4-S0 ➞ C16) + (C0 ➞ Out)
Same as 16-bit case
(C0 ➞ C16) + (C0 Setup time)
(S4-S0 ➞ C16) + (C0 Setup time)
Same as 16-bit case
(Clock ➞ C16) + (C0 Setup time)
=
=
=
=
=
=
=
=
=
=
=
A 31 -A 16
B 31 -B 16
A 15 -A 0
D
Q
D
D
Q
Q
B 15 -B 0
D
Q
CLOCK
C0, S 4 –S 0
A
F
MOST
SIGNIFICANT
SLICE
B
C0
A
C 16
16
F
16
F 15 -F 0
F 31 -F 16
B
C0
LEAST
SIGNIFICANT
SLICE
Arithmetic Logic Units
3
08/16/2000–LDS.383-E
L4C383
DEVICES INCORPORATED
FIGURE 4C.
16-bit Cascadable ALU (Extended Set)
FTAB = 1, FTF = 0
From
To
Clock
➞ F
A, B
➞ Other
C0
➞ Other
S4-S0
➞ Other
A, B
Setup time
C0
Setup time
S4-S0
Setup time
ENA, ENB, ENF
Setup time
Minimum cycle time
(F register accumulate loop)
A 31 -A 16
Calculated Specification Limit
Same as 16-bit case
(A, B ➞ C16) + (C0 ➞ Out)
(C0 ➞ C16) + (C0 ➞ Out)
(S4-S0 ➞ C16) + (C0 ➞ Out)
(A, B ➞ C16) + (C0 Setup time)
(C0 ➞ C16) + (C0 Setup time)
(S4-S0 ➞ C16) + (C0 Setup time)
Same as 16-bit case
(Clock ➞ C16) + (C0 Setup time)
=
=
=
=
=
=
=
=
=
B 31 -B 16
A 15 -A 0
B 15 -B 0
C0, S 4 –S 0
A
B
C0
F
D
FIGURE 4D.
C 16
B
C0
F
D
CLOCK
Q
MOST
SIGNIFICANT
SLICE
A
Q
16
CLOCK
LEAST
SIGNIFICANT
SLICE
16
F 15 -F 0
F 31 -F 16
FTAB = 1, FTF = 1
From
To
A, B
➞ F
A, B
➞ Other
C0
➞ F
C0
➞ Other
S4-S0
➞ F
➞ Other
S4-S0
A, B
Setup time
C0
Setup time
S4-S0
Setup time
ENA, ENB, ENF
Setup time
Minimum cycle time
(F register accumulate loop)
A 31 -A 16
=
=
=
=
=
=
=
=
=
=
=
B 31 -B 16
Calculated Specification Limit
(A, B ➞ C16) + (C0 ➞ F)
(A, B ➞ C16) + (C0 ➞ Out)
(C0 ➞ C16) + (C0 ➞ F)
(C0 ➞ C16) + (C0 ➞ Out)
(S4-S0 ➞ C16) + (C0 ➞ F)
(S4-S0 ➞ C16) + (C0 ➞ Out)
(A, B ➞ C16) + (C0 Setup time)
(C0 ➞ C16) + (C0 Setup time)
(S4-S0 ➞ C16) + (C0 Setup time)
Same as 16-bit case
(Clock ➞ C16) + (C0 Setup time)
A 15 -A 0
B 15 -B 0
C0, S 4 –S 0
A
F
MOST
SIGNIFICANT
SLICE
B
C0
A
C 16
16
F
16
F 15 -F 0
F 31 -F 16
B
C0
LEAST
SIGNIFICANT
SLICE
Arithmetic Logic Units
4
08/16/2000–LDS.383-E
L4C383
DEVICES INCORPORATED
16-bit Cascadable ALU (Extended Set)
MAXIMUM RATINGS Above which useful life may be impaired (Notes 1, 2, 3, 8)
Storage temperature ........................................................................................................... –65°C to +150°C
Operating ambient temperature ........................................................................................... –55°C to +125°C
VCC supply voltage with respect to ground ............................................................................ –0.5 V to +7.0 V
Input signal with respect to ground ........................................................................................ –3.0 V to +7.0 V
Signal applied to high impedance output ............................................................................... –3.0 V to +7.0 V
Output current into low outputs ............................................................................................................. 25 mA
Latchup current ............................................................................................................................... > 400 mA
OPERATING CONDITIONS To meet specified electrical and switching characteristics
Mode
Temperature Range (Ambient)
Active Operation, Commercial
Active Operation, Military
Supply Voltage
0°C to +70°C
4.75 V ≤ VCC ≤ 5.25 V
–55°C to +125°C
4.50 V ≤ VCC ≤ 5.50 V
ELECTRICAL CHARACTERISTICS Over Operating Conditions (Note 4)
Symbol
Parameter
Test Condition
Min
VOH
Output High Voltage
VCC = Min., IOH = –2.0 mA
VOL
Output Low Voltage
VCC = Min., IOL = 8.0 mA
VIH
Input High Voltage
VIL
Input Low Voltage
(Note 3)
IIX
Input Current
IOZ
Typ
Max
2.4
Unit
V
0.5
V
2.0
VCC
V
0.0
0.8
V
Ground ≤ VIN ≤ VCC (Note 12)
±20
µA
Output Leakage Current
Ground ≤ VOUT ≤ VCC (Note 12)
±20
µA
ICC1
VCC Current, Dynamic
(Notes 5, 6)
30
mA
ICC2
VCC Current, Quiescent
(Note 7)
1.5
mA
15
Arithmetic Logic Units
5
08/16/2000–LDS.383-E
L4C383
DEVICES INCORPORATED
16-bit Cascadable ALU (Extended Set)
SWITCHING CHARACTERISTICS — COMMERCIAL OPERATING RANGE (0°C to +70°C)
GUARANTEED MAXIMUM C1234567890123456789012345678901212345678901234567890
OMBINATIONAL DELAYS Notes 9, 10 (ns)
1234567890123456789012345678901212345678901234567890
To Output 1234567890123456789012345678901212345678901234567890
L4C383-55*
L4C383-40*
1234567890123456789012345678901212345678901234567890
From Input
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
F15-F0
N
OVF, Z C16 F15-F0
N
OVF, Z C16 F15-F0
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
32
38
53
36
26
30
44
32
22
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
—
—
34
22
—
—
28
20
1234567890123456789012345678901212345678901234567890 —
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
—
42
42
42
—
32
34
35
—
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
56
38
53
36
46
30
44
32
28
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
37
—
34
22
30
—
28
20
22
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
55
42
42
42
40
32
34
35
26
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
—
36
46
37
—
30
40
32
—
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
32
—
—
—
26
—
—
—
22
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
—
—
34
22
—
—
28
20
1234567890123456789012345678901212345678901234567890 —
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
—
42
42
42
—
32
34
35
—
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
55
36
46
37
40
30
40
32
26
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
56
38
53
36
46
30
44
32
28
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
37
—
34
22
30
—
28
20
22
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
55
42
42
42
40
32
34
35
26
1234567890123456789012345678901212345678901234567890
FTAB = 0, FTF = 0
Clock
C0
S4-S0
FTAB = 0, FTF = 1
Clock
C0
S4-S0
FTAB = 1, FTF = 0
A15-A0, B15-B0
Clock
C0
S4-S0
FTAB = 1, FTF = 1
A15-A0, B15-B0
Clock
C0
S4-S0
L4C383-26
N
OVF, Z
C16
22
—
22
26
18
22
22
18
22
22
—
22
26
18
22
22
18
22
22
—
—
22
22
—
18
22
22
—
18
22
22
22
—
22
22
26
18
22
22
22
18
22
GUARANTEED MINIMUM SETUP
AND HOLD TIMES WITH RESPECT TO CLOCK RISING EDGE Notes 9, 10 (ns)
1234567890123456789012345678901212345678901234567890
Input
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
L4C383-26
L4C383-55*
L4C383-40*
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
FTAB = 0
FTAB = 1
FTAB = 0
FTAB = 1
FTAB = 0
FTAB = 1
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
Setup Hold Setup Hold Setup Hold Setup Hold Setup Hold Setup Hold
1234567890123456789012345678901212345678901234567890
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1234567890123456789012345678901212345678901234567890
8
2
35
2
8
2
28
2
8
2
16
2
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1234567890123456789012345678901212345678901234567890
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1234567890123456789012345678901212345678901234567890
21
0
21
0
16
0
16
0
8
0
8
0
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
44
0
44
0
32
0
32
0
18
0
18
0
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
10
2
10
2
10
2
10
2
8
2
8
2
1234567890123456789012345678901212345678901234567890
A15-A0, B15-B0
C0
S4-S0
ENA, ENB, ENF
12345678901234567890123456
TRI-STATE
ENABLE/DISABLE TIMES Notes 9, 10, 11 (ns)
12345678901234567890123456
tENA
tDIS
12345678901234567890123456
12345678901234567890123456
L4C383-55* L4C383-40* L4C383-26
12345678901234567890123456
12345678901234567890123456
12345678901234567890123456
12345678901234567890123456
20
18
16
12345678901234567890123456
12345678901234567890123456
12345678901234567890123456
12345678901234567890123456
20
18
16
12345678901234567890123456
123456789012345678901234
123456789012345678901234
123456789012345678901234
*DISCONTINUED SPEED GRADE
123456789012345678901234
CLOCK CYCLE TIME
AND PULSE WIDTH Notes 9, 10 (ns)
12345678901234567890123456
12345678901234567890123456
12345678901234567890123456
L4C383-55* L4C383-40* L4C383-26
12345678901234567890123456
12345678901234567890123456
12345678901234567890123456
Minimum Cycle Time12345678901234567890123456
43
34
20
12345678901234567890123456
12345678901234567890123456
12345678901234567890123456
Highgoing Pulse 12345678901234567890123456
15
10
10
12345678901234567890123456
12345678901234567890123456
12345678901234567890123456
12345678901234567890123456
Lowgoing Pulse
15
10
10
12345678901234567890123456
12345678901234567890123456
Arithmetic Logic Units
6
08/16/2000–LDS.383-E
L4C383
DEVICES INCORPORATED
16-bit Cascadable ALU (Extended Set)
SWITCHING CHARACTERISTICS — COMMERCIAL OPERATING RANGE (0°C to +70°C)
GUARANTEED MAXIMUM COMBINATIONAL DELAYS Notes12345678901234567890123456
9, 10 (ns)
12345678901234567890123456
To Output
From Input
L4C383-20
F15-F0
N
OVF, Z
C16
FTAB = 0, FTF = 0
Clock
C0
S4-S0
11
—
—
20
—
18
20
14
20
20
14
18
FTAB = 0, FTF = 1
Clock
C0
S4-S0
20
18
20
20
—
18
20
14
20
20
14
18
FTAB = 1, FTF = 0
A15-A0, B15-B0
Clock
C0
S4-S0
—
11
—
—
16
—
—
18
20
—
14
20
17
—
14
18
FTAB = 1, FTF = 1
A15-A0, B15-B0
Clock
C0
S4-S0
20
20
18
20
16
20
—
18
20
20
14
20
17
20
14
18
12345678901234567890123456
12345678901234567890123456
L4C383-15*
12345678901234567890123456
12345678901234567890123456
12345678901234567890123456
12345678901234567890123456
F15-F0
N
OVF, Z C16
12345678901234567890123456
12345678901234567890123456
12345678901234567890123456
12345678901234567890123456
12345678901234567890123456
12345678901234567890123456
11
15
15
15
12345678901234567890123456
12345678901234567890123456
12345678901234567890123456
—
—
13
13
12345678901234567890123456
12345678901234567890123456
12345678901234567890123456
—
14
15
14
12345678901234567890123456
12345678901234567890123456
12345678901234567890123456
12345678901234567890123456
12345678901234567890123456
12345678901234567890123456
12345678901234567890123456
15
15
15
15
12345678901234567890123456
12345678901234567890123456
12345678901234567890123456
14
—
13
13
12345678901234567890123456
12345678901234567890123456
12345678901234567890123456
15
14
15
14
12345678901234567890123456
12345678901234567890123456
12345678901234567890123456
12345678901234567890123456
12345678901234567890123456
12345678901234567890123456
12345678901234567890123456
—
14
15
14
12345678901234567890123456
12345678901234567890123456
12345678901234567890123456
11
—
—
—
12345678901234567890123456
12345678901234567890123456
—
—
13
13
12345678901234567890123456
12345678901234567890123456
12345678901234567890123456
—
14
15
14
12345678901234567890123456
12345678901234567890123456
12345678901234567890123456
12345678901234567890123456
12345678901234567890123456
12345678901234567890123456
12345678901234567890123456
15
14
15
14
12345678901234567890123456
12345678901234567890123456
12345678901234567890123456
15
15
15
15
12345678901234567890123456
12345678901234567890123456
12345678901234567890123456
14
—
13
13
12345678901234567890123456
12345678901234567890123456
12345678901234567890123456
15
14
15
14
12345678901234567890123456
GUARANTEED MINIMUM SETUP AND HOLD TIMES WITH R
ESPECT TO CLOCK RISING EDGE Notes 9, 10 (ns)
12345678901234567890123456
12345678901234567890123456
12345678901234567890123456
12345678901234567890123456
L4C383-15*
12345678901234567890123456
12345678901234567890123456
12345678901234567890123456
FTAB = 0
FTAB = 1 12345678901234567890123456
FTAB = 0
FTAB = 1
12345678901234567890123456
12345678901234567890123456
Setup Hold Setup Hold 12345678901234567890123456
Setup Hold Setup Hold
12345678901234567890123456
12345678901234567890123456
12345678901234567890123456
5
0
14
0 12345678901234567890123456
5
0
12
0
12345678901234567890123456
12345678901234567890123456
12345678901234567890123456
12
0
12
0 12345678901234567890123456
10
0
10
0
12345678901234567890123456
12345678901234567890123456
12345678901234567890123456
15
0
15
0 12345678901234567890123456
12
0
12
0
12345678901234567890123456
12345678901234567890123456
12345678901234567890123456
5
0
5
0 12345678901234567890123456
5
0
5
0
12345678901234567890123456
12345678901234567890123456
L4C383-20
Input
A15-A0, B15-B0
C0
S4-S0
ENA, ENB, ENF
TRI-STATE ENABLE/DISABLE
TIMES Notes 9, 10, 11 (ns)
1234567890123
tENA
tDIS
1234567890123
L4C383-20 1234567890123
L4C383-15*
1234567890123
1234567890123
1234567890123
1234567890123
8
6
1234567890123
1234567890123
1234567890123
1234567890123
8
6
1234567890123
123456789012345678901234
123456789012345678901234
123456789012345678901234
*DISCONTINUED SPEED GRADE
123456789012345678901234
CLOCK CYCLE TIME AND PULSE 1234567890123
WIDTH Notes 9, 10 (ns)
1234567890123
1234567890123
1234567890123
1234567890123
14
1234567890123
1234567890123
1234567890123
1234567890123
4
1234567890123
1234567890123
1234567890123
1234567890123
4
1234567890123
1234567890123
L4C383-20 1234567890123
L4C383-15*
1234567890123
Minimum Cycle Time
18
Highgoing Pulse
5
Lowgoing Pulse
5
Arithmetic Logic Units
7
08/16/2000–LDS.383-E
L4C383
DEVICES INCORPORATED
16-bit Cascadable ALU (Extended Set)
SWITCHING CHARACTERISTICS — MILITARY OPERATING RANGE (–55°C to +125°C)
GUARANTEED MAXIMUM C123456789012345678901234567890121234567890123456789012345678901212345678901234
OMBINATIONAL DELAYS Notes 9, 10 (ns)
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
L4C383-65*
L4C383-45*
To Output 123456789012345678901234567890121234567890123456789012345678901212345678901234
L4C383-30*
123456789012345678901234567890121234567890123456789012345678901212345678901234
From Input
FTAB = 0, FTF = 0
Clock
C0
S4-S0
FTAB = 0, FTF = 1
Clock
C0
S4-S0
FTAB = 1, FTF = 0
A15-A0, B15-B0
Clock
C0
S4-S0
FTAB = 1, FTF = 1
A15-A0, B15-B0
Clock
C0
S4-S0
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
F15-F0
N
OVF, Z C16 F15-F0
N
OVF, Z C16 F15-F0
N
OVF, Z C16
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
37
44
63
45
28
34
50
34
26
28
34
28
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
—
—
42
25
—
—
32
23
—
—
22
22
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
—
48
48
48
—
38
38
38
—
28
28
28
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
68
44
63
45
56
34
50
34
34
28
34
28
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
42
—
42
25
32
—
32
23
26
—
22
22
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
66
48
48
48
46
38
38
38
30
28
28
28
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
—
44
56
44
—
32
46
36
—
28
28
28
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
37
—
—
—
28
—
—
—
26
—
—
—
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
—
—
42
25
—
—
32
23
—
—
22
22
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
—
48
48
48
—
38
38
38
—
28
28
28
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
65
44
56
44
45
32
46
36
30
28
28
28
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
68
44
63
45
56
34
50
34
34
28
34
28
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
42
—
42
25
32
—
32
23
26
—
22
22
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
66
48
48
48
46
38
38
38
30
28
28
28
123456789012345678901234567890121234567890123456789012345678901212345678901234
GUARANTEED MINIMUM SETUP
AND HOLD TIMES WITH RESPECT TO CLOCK RISING EDGE Notes 9, 10 (ns)
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
Input
A15-A0, B15-B0
C0
S4-S0
ENA, ENB, ENF
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
L4C383-65*
L4C383-45*
L4C383-30*
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
FTAB = 0
FTAB = 1
FTAB = 0
FTAB = 1
FTAB = 0
FTAB = 1
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
Setup Hold Setup Hold Setup Hold Setup Hold Setup Hold Setup Hold
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
10
3
43
3
8
3
33
3
8
3
20
3
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
25
0
25
0
20
0
20
0
12
0
12
0
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
50
0
50
0
36
0
36
0
20
0
20
0
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
12
2
12
2
10
2
10
2
10
2
10
2
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
TRI-STATE1234567890123456789012345678901212345
ENABLE/DISABLE TIMES Notes 9, 10, 11 (ns)
1234567890123456789012345678901212345
1234567890123456789012345678901212345
1234567890123456789012345678901212345
L4C383-65* L4C383-45* L4C383-30*
1234567890123456789012345678901212345
1234567890123456789012345678901212345
1234567890123456789012345678901212345
1234567890123456789012345678901212345
tENA
22
20
18
1234567890123456789012345678901212345
1234567890123456789012345678901212345
1234567890123456789012345678901212345
1234567890123456789012345678901212345
tDIS
22
20
18
1234567890123456789012345678901212345
1234567890123456789012345678901212345
123456789012345678901234
123456789012345678901234
123456789012345678901234
*DISCONTINUED SPEED GRADE
123456789012345678901234
CLOCK CYCLE TIME
AND PULSE WIDTH Notes 9, 10 (ns)
12345678901234567890123456789012123456
12345678901234567890123456789012123456
12345678901234567890123456789012123456
L4C383-65* L4C383-45* L4C383-30*
12345678901234567890123456789012123456
12345678901234567890123456789012123456
12345678901234567890123456789012123456
Minimum Cycle Time12345678901234567890123456789012123456
52
38
26
12345678901234567890123456789012123456
12345678901234567890123456789012123456
12345678901234567890123456789012123456
Highgoing Pulse 12345678901234567890123456789012123456
20
15
12
12345678901234567890123456789012123456
12345678901234567890123456789012123456
12345678901234567890123456789012123456
12345678901234567890123456789012123456
Lowgoing Pulse
20
15
12
12345678901234567890123456789012123456
12345678901234567890123456789012123456
Arithmetic Logic Units
8
08/16/2000–LDS.383-E
L4C383
DEVICES INCORPORATED
16-bit Cascadable ALU (Extended Set)
SWITCHING CHARACTERISTICS — MILITARY OPERATING RANGE (–55°C to +125°C)
GUARANTEED MAXIMUM C1234567890123456789012345678901212345678901234567890
OMBINATIONAL DELAYS Notes 9, 10 (ns)
1234567890123456789012345678901212345678901234567890
To Output 1234567890123456789012345678901212345678901234567890
L4C383-25*
L4C383-20*
1234567890123456789012345678901212345678901234567890
From Input
FTAB = 0, FTF = 0
Clock
C0
S4-S0
FTAB = 0, FTF = 1
Clock
C0
S4-S0
FTAB = 1, FTF = 0
A15-A0, B15-B0
Clock
C0
S4-S0
FTAB = 1, FTF = 1
A15-A0, B15-B0
Clock
C0
S4-S0
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
F15-F0
N
OVF, Z C16 F15-F0
N
OVF, Z C16
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
14
24
24
24
14
20
20
20
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
—
—
18
18
—
—
16
16
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
—
22
24
22
—
18
20
18
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
25
24
24
24
20
20
20
20
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
21
—
18
18
17
—
16
16
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
25
22
24
22
20
18
20
18
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
—
20
25
22
—
17
20
17
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
14
—
—
—
14
—
—
—
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
—
—
18
18
—
—
16
16
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
—
22
24
22
—
18
20
18
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
25
20
25
22
20
17
20
17
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
25
24
24
24
20
20
20
20
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
21
—
18
18
17
—
16
16
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
25
22
24
22
20
18
20
18
1234567890123456789012345678901212345678901234567890
GUARANTEED MINIMUM SETUP
AND HOLD TIMES WITH RESPECT TO CLOCK RISING EDGE Notes 9, 10 (ns)
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
Input
A15-A0, B15-B0
C0
S4-S0
ENA, ENB, ENF
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
L4C383-25*
L4C383-20*
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
FTAB = 0
FTAB = 1
FTAB = 0
FTAB = 1
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
Setup Hold Setup Hold Setup Hold Setup Hold
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
7
2
14
2
6
2
12
2
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
14
0
14
0
12
0
12
0
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
19
0
19
0
16
0
16
0
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
7
0
7
0
6
0
6
0
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
TRI-STATE1234567890123456789012345
ENABLE/DISABLE TIMES Notes 9, 10, 11 (ns)
1234567890123456789012345
1234567890123456789012345
L4C383-25* L4C383-20*
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tENA
14
10
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tDIS
14
10
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*DISCONTINUED SPEED GRADE
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CLOCK CYCLE TIME
AND PULSE WIDTH Notes 9, 10 (ns)
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L4C383-25* L4C383-20*
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Minimum Cycle Time12345678901234567890123456
20
18
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Highgoing Pulse 12345678901234567890123456
8
6
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Lowgoing Pulse
8
6
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Arithmetic Logic Units
9
08/16/2000–LDS.383-E
L4C383
DEVICES INCORPORATED
16-bit Cascadable ALU (Extended Set)
NOTES
1. Maximum Ratings indicate stress
specifications only. Functional operation of these products at values beyond
those indicated in the Operating Conditions table is not implied. Exposure to
maximum rating conditions for extended periods may affect reliability.
9. AC specifications are tested with
input transition times less than 3 ns,
output reference levels of 1.5 V (except
tDIS test), and input levels of nominally
0 to 3.0 V. Output loading may be a
resistive divider which provides for
specified IOH and IOL at an output
voltage of VOH min and VOL max
2. The products described by this spec- respectively. Alternatively, a diode
ification include internal circuitry de- bridge with upper and lower current
signed to protect the chip from damagsources of IOH and I OL respectively,
ing substrate injection currents and ac- and a balancing voltage of 1.5 V may be
cumulations of static charge. Neverthe- used. Parasitic capacitance is 30 pF
less, conventional precautions should minimum, and may be distributed.
be observed during storage, handling,
and use of these circuits in order to This device has high-speed outputs caavoid exposure to excessive electrical pable of large instantaneous current
stress values.
pulses and fast turn-on/turn-off times.
As a result, care must be exercised in the
3. This device provides hard clamping of testing of this device. The following
transient undershoot and overshoot. In- measures are recommended:
put levels below ground or above VCC
will be clamped beginning at –0.6 V and a. A 0.1 µF ceramic capacitor should be
VCC + 0.6 V. The device can withstand installed between VCC and Ground
indefinite operation with inputs in the leads as close to the Device Under Test
range of –0.5 V to +7.0 V. Device opera- (DUT) as possible. Similar capacitors
tion will not be adversely affected, how- should be installed between device VCC
ever, input current levels will be well in and the tester common, and device
ground and tester common.
excess of 100 mA.
4. Actual test conditions may vary from b. Ground and VCC supply planes
those designated but operation is guar- must be brought directly to the DUT
anteed as specified.
socket or contactor fingers.
5. Supply current for a given applica- c. Input voltages should be adjusted to
tion can be accurately approximated by: compensate for inductive ground and VCC
noise to maintain required DUT input
NCV2 F
levels relative to the DUT ground pin.
4
where
10. Each parameter is shown as a minN = total number of device outputs
C = capacitive load per output
V = supply voltage
F = clock frequency
6. Tested with all outputs changing every cycle and no load, at a 5 MHz clock
rate.
7. Tested with all inputs within 0.1 V of
VCC or Ground, no load.
8. These parameters are guaranteed
but not 100% tested.
11. For the tENA test, the transition is
measured to the 1.5 V crossing point
with datasheet loads. For the tDIS test,
the transition is measured to the
±200mV level from the measured
steady-state output voltage with
±10mA loads. The balancing voltage, V TH , is set at 3.5 V for Z-to-0
and 0-to-Z tests, and set at 0 V for Zto-1 and 1-to-Z tests.
12. These parameters are only tested at
the high temperature extreme, which is
the worst case for leakage current.
FIGURE A. OUTPUT LOADING CIRCUIT
S1
DUT
IOL
VTH
CL
IOH
FIGURE B. THRESHOLD LEVELS
tENA
OE
Z
tDIS
1.5 V
1.5 V
3.5V Vth
0
1.5 V
1.5 V
Z
1
VOL*
0.2 V
VOH*
0.2 V
0
Z
1
Z
0V Vth
VOL* Measured VOL with IOH = –10mA and IOL = 10mA
VOH* Measured VOH with IOH = –10mA and IOL = 10mA
imum or maximum value. Input requirements are specified from the point
of view of the external system driving
the chip. Setup time, for example, is
specified as a minimum since the external system must supply at least that
much time to meet the worst-case requirements of all parts. Responses from
the internal circuitry are specified from
the point of view of the device. Output
delay, for example, is specified as a
maximum since worst-case operation of
any device always provides data within
that time.
Arithmetic Logic Units
10
08/16/2000–LDS.383-E
L4C383
DEVICES INCORPORATED
16-bit Cascadable ALU (Extended Set)
ORDERING INFORMATION
A8
A7
A6
A5
A4
A3
A2
A1
A0
B15
B14
B13
B12
B11
B10
B9
B8
68-pin
10
9
8
7
6
5
4
3
2
1 68 67 66 65 64 63 62 61
60
11
59
12
58
13
57
14
56
15
55
16
54
17
Top
View
18
19
53
52
51
20
50
21
49
22
48
23
47
24
46
25
45
26
44
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
B7
B6
B5
B4
B3
B2
B1
B0
ENA
ENB
FTAB
S4
S3
S2
S1
S0
C0
OE
F15
F14
F13
F12
F11
F10
F9
F8
F7
F6
F5
F4
F3
F2
F1
F0
A9
A10
A11
A12
A13
A14
A15
CLK
VCC
GND
C16
GND
N
ZERO
OVF
ENF
FTF
Speed
Plastic J-Lead Chip Carrier
(J2)
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68-pin
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1
2
3
4
5
6
7
8
9
10
11
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A
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A8
A7
B9
A5
A3
A1
B15 B13 B11
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B
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B7
A10
A9
A6
B8
A4
A2
A0
B14 B12 B10
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C
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B5
B6
A12 A11
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D
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A14 A13
B3
B4
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E
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Top View
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CLK A15
B1
B2
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Through Package
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F
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ENA B0
GND VCC
(i.e., Component Side Pinout)
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G
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FTAB ENB
GND C16
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H
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S4
S3
ZERO N
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J
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S1
S2
ENF OVF
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K
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C0
S0
FTF OE F14 F12 F10
F8
F6
F4
F2
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L
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F0
F15 F13 F11
F9
F7
F5
F3
F1
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Discontinued Package
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Ceramic Pin Grid Array
(G1)
0°C to +70°C — COMMERCIAL SCREENING
26 ns
20 ns
L4C383JC26
L4C383JC20
–55°C to +125°C — COMMERCIAL SCREENING
–55°C to +125°C — MIL-STD-883 COMPLIANT
Arithmetic Logic Units
11
08/16/2000–LDS.383-E