L10C11 L10C11 DEVICES INCORPORATED 4/8-bit Variable Length Shift Register 4/8-bit Variable Length Shift Register DEVICES INCORPORATED FEATURES DESCRIPTION ❑ Variable Length 4 or 8-bit Wide Shift Register ❑ Selectable Delay Length from 3 to 18 Stages ❑ ❑ ❑ ❑ ❑ Low Power CMOS Technology Replaces Fairchild TMC2011 Load, Shift, and Hold Instructions Separate Data In and Data Out Pins Package Styles Available: • 24-pin Plastic DIP • 28-pin Plastic LCC, J-Lead The L10C11 is a high-speed, low power CMOS variable length shift register. The L10C11 consists of two 4-bit wide, adjustable length shift registers. These registers share control signals and a common clock. Both shift registers can be programmed together to any length from 3 to 18 stages inclusive, or one register can be fixed at 18 stages of delay while the other is variable. The configuration implemented is determined by the Length Code (L 3-0) and the MODE control line as shown in Table 1. Each input is applied to a chain of registers which are clocked on the rising edge of the common CLK input. These registers are numbered R1 through R17 and R1’ through R17’, corresponding to the D 3-0 and D 7-4 data fields respectively. A multiplexer serves to route the contents of any of registers R2 through R17 to the output register, denoted R18. A similar multiplexer operates on the contents of R2’ through R17’ to load R18’. Note that the minimum-length path from data inputs to outputs is R1 to R2 to R18, consisting of three stages of delay. The MODE input determines whether one or both of the internal shift registers have variable length. When MODE = 0, both D 3-0 and D 7-4 are delayed by an amount which is controlled by L3-0. When MODE = 1, the D 7-4 field is delayed by 18 stages independent of L3-0. The Length Code (L3-0) controls the number of stages of delay applied to the D inputs as shown in Table 1. When the Length Code is 0, the inputs are delayed by 3 clock periods. When the Length Code is 1, the delay is 4 clock periods, and so forth. The Length Code and MODE inputs are latched on the rising edge of CLK. Both the Length Code and MODE values may be changed at any time without affecting the contents of registers R1 through R17 or R1’ through R17’. MUX REGISTER R18 MUX REGISTER R18’ REGISTER R17 REGISTER R16 REGISTER R3 REGISTER R2 REGISTER R15 REGISTER R17’ REGISTER R16’ REGISTER R15’ 4 D7-4 REGISTER R3’ MODE REGISTER R2’ 4 L3-0 R17 R16 R15 R4 R3 R2 4 Y3-0 L REGISTER CLK REGISTER R1’ 4 D3-0 REGISTER R1 L10C11 BLOCK DIAGRAM R17’ R16’ R15’ R4’ R3’ R2’ 4 Y7-4 Pipeline Registers 1 03/27/2000–LDS.11-L L10C11 DEVICES INCORPORATED TABLE 1. 4/8-bit Variable Length Shift Register CONTROL ENCODING Length Code Mode = 0 Mode = 1 Delay Delay Y3-0 Y7-4 Y3-0 Y7-4 MAXIMUM RATINGS Above which useful life may be impaired (Notes 1, 2, 3, 8) Storage temperature ..................................................... –65°C to +150°C L3 L2 L1 L0 0 0 0 0 3 3 3 18 0 0 0 1 4 4 4 18 VCC supply voltage with respect to ground ...................... –0.5 V to +7.0 V 0 0 1 0 5 5 5 18 Input signal with respect to ground .................................. –3.0 V to +7.0 V 0 0 1 1 6 6 6 18 Signal applied to high impedance output ......................... –3.0 V to +7.0 V 0 1 0 0 7 7 7 18 Output current into low outputs ....................................................... 25 mA 0 1 0 1 8 8 8 18 Latchup current ......................................................................... > 400 mA 0 1 1 0 9 9 9 18 0 1 1 1 10 10 10 18 1 0 0 0 11 11 11 18 1 0 0 1 12 12 12 18 1 0 1 0 13 13 13 18 1 0 1 1 14 14 14 18 1 1 0 0 15 15 15 18 Mode Temperature Range Supply Voltage 1 1 0 1 16 16 16 18 Active Operation, Com. 0°C to +70°C 4.75 V £ VCC £ 5.25 V 1 1 1 0 17 17 17 18 1 1 1 1 18 18 18 18 Active Operation, Mil. –55°C to +125°C 4.50 V £ VCC £ 5.50 V Operating ambient temperature ..................................... –55°C to +125°C OPERATING CONDITIONS To meet specified electrical and switching characteristics ELECTRICAL CHARACTERISTICS Over Operating Conditions (Note 4) Symbol Parameter Test Condition Min VOH Output High Voltage VCC = Min., IOH = –12 mA 2.4 VOL Output Low Voltage VCC = Min., IOL = 24 mA VIH Input High Voltage VIL Input Low Voltage (Note 3) IIX Input Current Ground ≤ VIN ≤ VCC (Note 12) ICC1 VCC Current, Dynamic (Notes 5, 6) ICC2 VCC Current, Quiescent (Note 7) Typ Max Unit V 0.5 V 2.0 VCC V 0.0 0.8 V ±20 µA 20 mA 1.0 mA 10 Pipeline Registers 2 03/27/2000–LDS.11-L L10C11 DEVICES INCORPORATED 4/8-bit Variable Length Shift Register SWITCHING CHARACTERISTICS COMMERCIAL OPERATING RANGE (0°C to +70°C) Notes 9, 10 (ns) Symbol L10C11– 1234567890123456 1234567890123456 1234567890123456 25* 20 1234567890123456 1234567890123456 1234567890123456 Min Max Min Max 1234567890123456 1234567890123456 25 20 1234567890123456 1234567890123456 1234567890123456 1234567890123456 15 12 1234567890123456 1234567890123456 1234567890123456 20 10 1234567890123456 1234567890123456 1234567890123456 2 0 1234567890123456 1234567890123456 1234567890123456 20 10 1234567890123456 1234567890123456 1234567890123456 2 0 1234567890123456 1234567890123456 Parameter tPD Output Delay tPW Clock Pulse Width tSD Data Setup Time tHD Data Hold Time tSL L3-0, MODE Setup Time tHL L3-0, MODE Hold Time 15 Min Max 15 10 8 0 8 0 MILITARY OPERATING RANGE (–55°C to +125°C) Notes 9, 10 (ns) Symbol L10C11– 1234567890123456789012345678901212345678901234 1234567890123456789012345678901212345678901234 1234567890123456789012345678901212345678901234 * 30 25* 20* 1234567890123456789012345678901212345678901234 1234567890123456789012345678901212345678901234 1234567890123456789012345678901212345678901234 Min Max Min Max Min Max 1234567890123456789012345678901212345678901234 1234567890123456789012345678901212345678901234 30 25 20 1234567890123456789012345678901212345678901234 1234567890123456789012345678901212345678901234 1234567890123456789012345678901212345678901234 1234567890123456789012345678901212345678901234 15 12 12 1234567890123456789012345678901212345678901234 1234567890123456789012345678901212345678901234 1234567890123456789012345678901212345678901234 25 10 10 1234567890123456789012345678901212345678901234 1234567890123456789012345678901212345678901234 1234567890123456789012345678901212345678901234 2 2 0 1234567890123456789012345678901212345678901234 1234567890123456789012345678901212345678901234 1234567890123456789012345678901212345678901234 25 10 10 1234567890123456789012345678901212345678901234 1234567890123456789012345678901212345678901234 1234567890123456789012345678901212345678901234 1234567890123456789012345678901212345678901234 2 2 0 1234567890123456789012345678901212345678901234 Parameter tPD Output Delay tPW Clock Pulse Width tSD Data Setup Time tHD Data Hold Time tSL L3-0, MODE Setup Time tHL L3-0, MODE Hold Time SWITCHING WAVEFORMS tSD tHD tSL tHL D7-0 L3-0 MODE tPW tPW CLK tPD Y7-0 123456789012345678901234 123456789012345678901234 123456789012345678901234 *DISCONTINUED SPEED GRADE 123456789012345678901234 Pipeline Registers 3 03/27/2000–LDS.11-L L10C11 DEVICES INCORPORATED 4/8-bit Variable Length Shift Register NOTES 1. Maximum Ratings indicate stress specifications only. Functional operation of these products at values beyond those indicated in the Operating Conditions table is not implied. Exposure to maximum rating conditions for extended periods may affect reliability. 9. AC specifications are tested with input transition times less than 3 ns, output reference levels of 1.5 V (except tDIS test), and input levels of nominally 0 to 3.0 V. Output loading may be a resistive divider which provides for specified IOH and IOL at an output voltage of VOH min and VOL max respectively. Alternatively, a diode bridge with upper and lower current sources of IOH and I OL respectively, and a balancing voltage of 1.5 V may be used. Parasitic capacitance is 30 pF minimum, and may be distributed. 11. For the tENA test, the transition is measured to the 1.5 V crossing point with datasheet loads. For the tDIS test, the transition is measured to the ±200mV level from the measured steady-state output voltage with ±10mA loads. The balancing voltage, V TH , is set at 3.5 V for Z-to-0 and 0-to-Z tests, and set at 0 V for Zto-1 and 1-to-Z tests. 2. The products described by this specification include internal circuitry designedto protect the chipfrom damaging substrate injection currents and accumu12. These parameters are only tested at lations of static charge. Nevertheless, the high temperature extreme, which is conventional precautions should be obthe worst case for leakage current. served during storage, handling, and use FIGURE A. OUTPUT LOADING CIRCUIT of these circuits in order to avoid expo- This device has high-speed outputs casure to excessive electrical stress values. pable of large instantaneous current pulses and fast turn-on/turn-off times. 3. This device provides hard clamping of As a result, care must be exercised in the S1 transient undershoot and overshoot. In- testing of this device. The following DUT IOL put levels below ground or above VCC measures are recommended: VTH CL will be clamped beginning at –0.6 V and IOH VCC + 0.6 V. The device can withstand a. A 0.1 µF ceramic capacitor should be indefinite operation with inputs in the installed between VCC and Ground range of –0.5 V to +7.0 V. Device opera- leads as close to the Device Under Test FIGURE B. THRESHOLD LEVELS tion will not be adversely affected, how- (DUT) as possible. Similar capacitors tENA tDIS ever, input current levels will be well in should be installed between device VCC OE 1.5 V 1.5 V and the tester common, and device excess of 100 mA. ground and tester common. 3.5V Vth 0 Z 4. Actual test conditions may vary from 1.5 V VOL* 0.2 V Z 0 those designated but operation is guar- b. Ground and VCC supply planes 1 Z anteed as specified. must be brought directly to the DUT 0.2 V VOH* 1.5 V 0V Vth Z 1 socket or contactor fingers. 5. Supply current for a given application VOL* Measured VOL with IOH = –10mA and IOL = 10mA VOH* Measured VOH with IOH = –10mA and IOL = 10mA can be accurately approximated by: c. Input voltages should be adjusted to compensate for inductive ground and VCC NCV2 F noise to maintain required DUT input levels relative to the DUT ground pin. 4 where 10. Each parameter is shown as a minimum or maximum value. Input requirements are specified from the point of view of the external system driving the chip. Setup time, for example, is 6. Tested with all outputs changing ev- specified as a minimum since the exterery cycle and no load, at a 5 MHz clock nal system must supply at least that much time to meet the worst-case rerate. quirements of all parts. Responses from 7. Tested with all inputs within 0.1 V of the internal circuitry are specified from VCC or Ground, no load. the point of view of the device. Output 8. These parameters are guaranteed delay, for example, is specified as a maximum since worst-case operation of but not 100% tested. any device always provides data within that time. N = total number of device outputs C = capacitive load per output V = supply voltage F = clock frequency Pipeline Registers 4 03/27/2000–LDS.11-L L10C11 DEVICES INCORPORATED 4/8-bit Variable Length Shift Register ORDERING INFORMATION 1234567890123456789012345678901212345678901234567 1234567890123456789012345678901212345678901234567 1234567890123456789012345678901212345678901234567 1234567890123456789012345678901212345678901234567 24-pin — 0.6" wide 1234567890123456789012345678901212345678901234567 1234567890123456789012345678901212345678901234567 1234567890123456789012345678901212345678901234567 1234567890123456789012345678901212345678901234567 1234567890123456789012345678901212345678901234567 1234567890123456789012345678901212345678901234567 1234567890123456789012345678901212345678901234567 1234567890123456789012345678901212345678901234567 1234567890123456789012345678901212345678901234567 1234567890123456789012345678901212345678901234567 1234567890123456789012345678901212345678901234567 1234567890123456789012345678901212345678901234567 1234567890123456789012345678901212345678901234567 1 Y0 24 D0 1234567890123456789012345678901212345678901234567 1234567890123456789012345678901212345678901234567 1234567890123456789012345678901212345678901234567 2 Y1 23 D1 1234567890123456789012345678901212345678901234567 1234567890123456789012345678901212345678901234567 3 Y2 22 D 2 1234567890123456789012345678901212345678901234567 1234567890123456789012345678901212345678901234567 4 Y3 21 D 3 1234567890123456789012345678901212345678901234567 1234567890123456789012345678901212345678901234567 5 L2 20 L0 1234567890123456789012345678901212345678901234567 1234567890123456789012345678901212345678901234567 6 L3 19 L1 1234567890123456789012345678901212345678901234567 1234567890123456789012345678901212345678901234567 7 GND 18 VCC 1234567890123456789012345678901212345678901234567 1234567890123456789012345678901212345678901234567 1234567890123456789012345678901212345678901234567 8 MODE 17 CLK 1234567890123456789012345678901212345678901234567 1234567890123456789012345678901212345678901234567 9 Y4 16 D 4 1234567890123456789012345678901212345678901234567 1234567890123456789012345678901212345678901234567 10 Y5 15 D 5 1234567890123456789012345678901212345678901234567 1234567890123456789012345678901212345678901234567 11 Y6 14 D6 1234567890123456789012345678901212345678901234567 1234567890123456789012345678901212345678901234567 12 Y7 13 D7 1234567890123456789012345678901212345678901234567 1234567890123456789012345678901212345678901234567 1234567890123456789012345678901212345678901234567 1234567890123456789012345678901212345678901234567 1234567890123456789012345678901212345678901234567 1234567890123456789012345678901212345678901234567 1234567890123456789012345678901212345678901234567 1234567890123456789012345678901212345678901234567 1234567890123456789012345678901212345678901234567 1234567890123456789012345678901212345678901234567 1234567890123456789012345678901212345678901234567 1234567890123456789012345678901212345678901234567 1234567890123456789012345678901212345678901234567 1234567890123456789012345678901212345678901234567 1234567890123456789012345678901212345678901234567 1234567890123456789012345678901212345678901234567 1234567890123456789012345678901212345678901234567 1234567890123456789012345678901212345678901234567 1234567890123456789012345678901212345678901234567 1234567890123456789012345678901212345678901234567 1234567890123456789012345678901212345678901234567 1234567890123456789012345678901212345678901234567 Discontinued Package 1234567890123456789012345678901212345678901234567 1234567890123456789012345678901212345678901234567 1234567890123456789012345678901212345678901234567 1234567890123456789012345678901212345678901234567 1234567890123456789012345678901212345678901234567 1234567890123456789012345678901212345678901234567 24-pin — 0.3" wide D0 D1 D2 D3 L0 L1 VCC CLK D4 D5 D6 D7 Speed 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 Y0 Y1 Y2 Y3 L2 L3 GND MODE Y4 Y5 Y6 Y7 Plastic DIP (P2) Plastic DIP (P1) 0°C to +70°C — COMMERCIAL SCREENING 20 ns 15 ns L10C11PC20 L10C11PC15 –55°C to +125°C — COMMERCIAL SCREENING –55°C to +125°C — MIL-STD-883 COMPLIANT Pipeline Registers 5 03/27/2000–LDS.11-L L10C11 DEVICES INCORPORATED 4/8-bit Variable Length Shift Register ORDERING INFORMATION D2 D1 D0 Y0 Y1 Y2 Y3 28-pin 4 5 3 2 1 28 27 26 25 6 24 7 Top View 8 9 23 22 21 10 20 11 19 12 13 14 15 16 17 18 NC L2 L3 GND GND MODE NC D5 D6 D7 Y7 Y6 Y5 Y4 D3 L0 L1 VCC CLK D4 NC Speed Plastic J-Lead Chip Carrier (J4) 0°C to +70°C — COMMERCIAL SCREENING 20 ns 15 ns L10C11JC20 L10C11JC15 –55°C to +125°C — COMMERCIAL SCREENING –55°C to +125°C — MIL-STD-883 COMPLIANT Pipeline Registers 6 03/27/2000–LDS.11-L