LOGIC L4C381JC20

L4C381
L4C381
DEVICES INCORPORATED
16-bit Cascadable ALU
16-bit Cascadable ALU
DEVICES INCORPORATED
FEATURES
DESCRIPTION
❑ High-Speed (15ns), Low Power
16-bit Cascadable ALU
❑ Implements Add, Subtract, Accumulate, Two’s Complement, Pass, and
Logic Operations
❑ All Registers Have a Bypass Path
for Complete Flexibility
❑ 68-pin PLCC, J-Lead
The L4C381 is a flexible, high speed,
cascadable 16-bit Arithmetic and
Logic Unit. It combines four 381-type
4-bit ALUs, a look-ahead carry
generator, and miscellaneous interface
logic — all in a single 68-pin package.
While containing new features to
support high speed pipelined architectures and single 16-bit bus configurations, the L4C381 retains full performance and functional compatibility with
the bipolar ’381 designs.
The L4C381 can be cascaded to
perform 32-bit or greater operations.
See “Cascading the L4C381” toward
L4C381 BLOCK DIAGRAM
A15-A0
B15-B0
16
16
B REGISTER
A REGISTER
ENA
the end of this data sheet for more
information.
ARCHITECTURE
The L4C381 operates on two 16-bit
operands (A and B) and produces a
16-bit result (F). Three select lines
control the ALU and provide 3
arithmetic, 3 logical, and 2 initialization functions. Full ALU status is
provided to support cascading to
longer word lengths. Registers are
provided on both the ALU inputs and
the output, but these may be bypassed
under user control. An internal
feedback path allows the registered
ALU output to be routed to one of the
ALU inputs, accommodating chain
operations and accumulation. Furthermore, the A or B input can be
forced to Zero allowing unary functions on either operand.
ENB
ALU OPERATIONS
FTAB
0
0
2
P, G, C16
OVF, Z
5
4
ALU
OSA
OSB
S2-S0, C0
16
The S2–S0 lines specify the operation
to be performed. The ALU functions
and their select codes are shown in
Table 1.
The two functions, B minus A and
A minus B, can be achieved by setting
the carry input of the least significant
slice and selecting codes 001 and 010
respectively.
TABLE 1.
ENF
RESULT REGISTER
FTF
16
OE
16
CLK
TO ALL REGISTERS
F15-F0
ALU FUNCTIONS
S2-S0
FUNCTION
000
CLEAR (F = 00 • • • 00)
001
NOT(A) + B
010
A + NOT(B)
011
A+B
100
A XOR B
101
A OR B
110
A AND B
111
PRESET (F = 11 • • • 11)
Arithmetic Logic Units
1
08/16/2000–LDS.381-P
L4C381
DEVICES INCORPORATED
ALU STATUS
The ALU provides Overflow and Zero
status bits. Carry, Propagate, and
Generate outputs are also provided
for cascading. These outputs are
defined for the three arithmetic
functions only. The ALU sets the Zero
output when all 16 output bits are
zero. The Generate, Propagate, C16,
and OVF flags for the A + B operation
are defined in Table 2. The status
flags produced for NOT(A) + B and
A + NOT(B) can be found by complementing Ai and Bi respectively in
Table 2.
OPERAND REGISTERS
The L4C381 has two 16-bit wide input registers for operands A and B.
These registers are rising edge triggered by a common clock. The A
register is enabled for input by setting
the ENA control LOW, and the B
register is enabled for input by setting
the ENB control LOW. When either
the ENA control or ENB control is
HIGH, the data in the corresponding
input register will not change.
This architecture allows the L4C381 to
accept arguments from a single 16-bit
data bus. For those applications that
do not require registered inputs, both
the A and B operand registers can be
bypassed with the FTAB control line.
When the FTAB control is asserted
(FTAB = HIGH), data is routed
around the A and B input registers;
however, they continue to function
normally via the ENA and ENB
controls. The contents of the input
registers will again be available to the
ALU if the FTAB control is released.
OUTPUT REGISTER
The output of the ALU drives the
input of a 16-bit register. This risingedge-triggered register is clocked by
the same clock as the input registers.
When the ENF control is LOW, data
from the ALU will be clocked into the
16-bit Cascadable ALU
TABLE 2.
ALU STATUS FLAGS
Bit Carry Generate = gi = A iB i
Bit Carry Propagate = pi = A i + Bi
for i = 0 ... 15
for i = 0 ... 15
P 0 = p0
P i = pi(Pi–1)
for i = 1 ... 15
and
G 0 = g0
G i = gi + pi(Gi–1)
C i = G i–1 + Pi–1 (C0)
for i = 1 ... 15
for i = 1 ... 15
then
G
P
C 16
OVF
=
=
=
=
NOT(G15)
NOT(P15)
G 15 + P15C 0
C 15 XOR C16
output register. By disabling the
output register, intermediate results
can be held while loading new input
operands. Three-state drivers controlled by the OE input allow the
L4C381 to be configured in a single
bidirectional bus system.
The output register can be bypassed
by asserting the FTF control signal
(FTF = HIGH). When the FTF control
is asserted, output data is routed
around the output register, however,
it continues to function normally via
the ENF control. The contents of the
output register will again be available
on the output pins if FTF is released.
With both FTAB and FTF true (HIGH)
the L4C381 is functionally identical to
four cascaded 54S381-type devices.
OPERAND SELECTION
The two operand select lines, OSA and
OSB, control multiplexers that precede
the ALU inputs. These multiplexers
provide an operand force-to-zero
function as well as F register feedback
to the B input. Table 3 shows the
inputs to the ALU as a function of the
operand select inputs. Either the A or
B operands may be forced to zero.
TABLE 3. OPERAND SELECTION
OSB
OSA
OPERAND B
OPERAND A
0
0
F
A
0
1
0
A
1
0
B
0
1
1
B
A
When both operand select lines are
low, the L4C381 is configured as a
chain calculation ALU. The registered
ALU output is passed back to the B
input to the ALU. This allows accumulation operations to be performed
by providing new operands via the A
input port. The accumulator can be
preloaded from the A input by setting
OSA true. By forcing the function
select lines to the CLEAR state (000),
the accumulator may be cleared. Note
that this feedback operation is not
affected by the state of the FTF
control. That is, the F outputs of the
L4C381 may be driven directly by the
ALU. The output register continues to
function, however, and provides the
ALU B operand source.
Arithmetic Logic Units
2
08/16/2000–LDS.381-P
L4C381
DEVICES INCORPORATED
16-bit Cascadable ALU
MAXIMUM RATINGS Above which useful life may be impaired (Notes 1, 2, 3, 8)
Storage temperature ........................................................................................................... –65°C to +150°C
Operating ambient temperature ........................................................................................... –55°C to +125°C
VCC supply voltage with respect to ground ............................................................................ –0.5 V to +7.0 V
Input signal with respect to ground ........................................................................................ –3.0 V to +7.0 V
Signal applied to high impedance output ............................................................................... –3.0 V to +7.0 V
Output current into low outputs ............................................................................................................. 25 mA
Latchup current ............................................................................................................................... > 400 mA
OPERATING CONDITIONS To meet specified electrical and switching characteristics
Mode
Temperature Range (Ambient)
Active Operation, Commercial
Active Operation, Military
Supply Voltage
0°C to +70°C
4.75 V ≤ VCC ≤ 5.25 V
–55°C to +125°C
4.50 V ≤ VCC ≤ 5.50 V
ELECTRICAL CHARACTERISTICS Over Operating Conditions (Note 4)
Symbol
Parameter
Test Condition
Min
VOH
Output High Voltage
VCC = Min., IOH = –2.0 mA
VOL
Output Low Voltage
VCC = Min., IOL = 8.0 mA
VIH
Input High Voltage
VIL
Input Low Voltage
(Note 3)
IIX
Input Current
IOZ
Typ
Max
2.4
Unit
V
0.5
V
2.0
VCC
V
0.0
0.8
V
Ground ≤ VIN ≤ VCC (Note 12)
±20
µA
Output Leakage Current
Ground ≤ VOUT ≤ VCC (Note 12)
±20
µA
ICC1
VCC Current, Dynamic
(Notes 5, 6)
30
mA
ICC2
VCC Current, Quiescent
(Note 7)
1.5
mA
15
Arithmetic Logic Units
3
08/16/2000–LDS.381-P
L4C381
DEVICES INCORPORATED
16-bit Cascadable ALU
SWITCHING CHARACTERISTICS — COMMERCIAL OPERATING RANGE (0°C to +70°C)
GUARANTEED MAXIMUM C123456789012345678901234567890121234567890123456789012345678901212345678901234
OMBINATIONAL DELAYS Notes 9, 10 (ns)
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To Output 123456789012345678901234567890121234567890123456789012345678901212345678901234
L4C381-55*
L4C381-40*
L4C381-26*
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F15-F0 P, G OVF, Z C16 F15-F0 P, G OVF, Z C16 F15-F0 P, G OVF, Z C16
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FTAB = 0, FTF = 0
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Clock
32
38
53
36
26
30
44
32
22
22
26
22
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C0
—
—
34
22
—
—
28
20
—
—
18
18
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S2-S0, OSA, OSB
—
42
42
42
—
32
34
35
—
22
22
22
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FTAB = 0, FTF = 1
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Clock
56
38
53
36
46
30
44
32
28
22
26
22
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C0
37
—
34
22
30
—
28
20
22
—
18
18
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123456789012345678901234567890121234567890123456789012345678901212345678901234
S2-S0, OSA, OSB
55
42
42
42
40
32
34
35
26
22
22
22
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FTAB = 1, FTF = 0
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A15-A0, B15-B0
—
36
46
37
—
30
40
32
—
22
22
22
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Clock
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32
—
—
—
26
—
—
—
22
—
—
—
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123456789012345678901234567890121234567890123456789012345678901212345678901234
C0
—
—
34
22
—
—
28
20
—
—
18
18
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123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
S2-S0, OSA, OSB
—
42
42
42
—
32
34
35
—
22
22
22
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123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
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FTAB = 1, FTF = 1
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A15-A0, B15-B0
55
36
46
37
40
30
40
32
26
22
22
22
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123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
Clock (OSA, OSB = 0) 123456789012345678901234567890121234567890123456789012345678901212345678901234
56
38
53
36
46
30
44
32
28
22
26
22
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
C0
37
—
34
22
30
—
28
20
22
—
18
18
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123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
S2-S0, OSA, OSB
55
42
42
42
40
32
34
35
26
22
22
22
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From Input
GUARANTEED MINIMUM SETUP
AND HOLD TIMES WITH RESPECT TO CLOCK RISING EDGE Notes 9, 10 (ns)
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Input
A15-A0, B15-B0
C0
S2-S0, OSA, OSB
ENA, ENB, ENF
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123456789012345678901234567890121234567890123456789012345678901212345678901234
L4C381-26*
L4C381-55*
L4C381-40*
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
FTAB = 0
FTAB = 1
FTAB = 0
FTAB = 1
FTAB = 0
FTAB = 1
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Setup Hold Setup Hold Setup Hold Setup Hold Setup Hold Setup Hold
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8
2
35
2
8
2
28
2
8
2
16
2
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21
0
21
0
16
0
16
0
8
0
8
0
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44
0
44
0
32
0
32
0
18
0
18
0
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10
2
10
2
10
2
10
2
8
2
8
2
123456789012345678901234567890121234567890123456789012345678901212345678901234
TRI-STATE12345678901234567890123456789012123456
ENABLE/DISABLE TIMES Notes 9, 10, 11 (ns)
12345678901234567890123456789012123456
CLOCK CYCLE TIME
AND PULSE WIDTH Notes 9, 10 (ns)
12345678901234567890123456789012123456
12345678901234567890123456789012123456
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12345678901234567890123456789012123456
L4C381-55* L4C381-40* L4C381-26*
L4C381-55* L4C381-40* L4C381-26*
12345678901234567890123456789012123456
12345678901234567890123456789012123456
12345678901234567890123456789012123456
12345678901234567890123456789012123456
12345678901234567890123456789012123456
12345678901234567890123456789012123456
12345678901234567890123456789012123456
Minimum Cycle Time12345678901234567890123456789012123456
tENA
20
18
16
43
34
20
12345678901234567890123456789012123456
12345678901234567890123456789012123456
12345678901234567890123456789012123456
12345678901234567890123456789012123456
12345678901234567890123456789012123456
12345678901234567890123456789012123456
12345678901234567890123456789012123456
Highgoing Pulse 12345678901234567890123456789012123456
tDIS
20
18
16
15
10
10
12345678901234567890123456789012123456
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12345678901234567890123456789012123456
12345678901234567890123456789012123456
12345678901234567890123456789012123456
Lowgoing Pulse
15
10
10
12345678901234567890123456789012123456
123456789012345678901234
12345678901234567890123456789012123456
123456789012345678901234
123456789012345678901234
*DISCONTINUED SPEED GRADE
Arithmetic Logic Units
4
08/16/2000–LDS.381-P
L4C381
DEVICES INCORPORATED
16-bit Cascadable ALU
SWITCHING CHARACTERISTICS — COMMERCIAL OPERATING RANGE (0°C to +70°C)
GUARANTEED MAXIMUM COMBINATIONAL DELAYS Notes 9, 10 (ns)
L4C381-20
To Output
From Input
F15-F0
P, G OVF, Z
L4C381-15
C16 F15-F0
P, G OVF, Z
C16
FTAB = 0, FTF = 0
Clock
C0
S2-S0, OSA, OSB
11
—
—
20
—
18
20
14
20
20
14
18
11
—
—
15
—
14
15
13
15
15
13
14
FTAB = 0, FTF = 1
Clock
C0
S2-S0, OSA, OSB
20
18
20
20
—
18
20
14
20
20
14
18
15
14
15
15
—
14
15
13
15
15
13
14
FTAB = 1, FTF = 0
A15-A0, B15-B0
Clock
C0
S2-S0, OSA, OSB
—
11
—
—
16
—
—
18
20
—
14
20
17
—
14
18
—
11
—
—
14
—
—
14
15
—
13
15
14
—
13
14
FTAB = 1, FTF = 1
A15-A0, B15-B0
Clock (OSA, OSB = 0)
C0
S2-S0, OSA, OSB
20
20
18
20
16
20
—
18
20
20
14
20
17
20
14
18
15
15
14
15
14
15
—
14
15
15
13
15
14
15
13
14
GUARANTEED MINIMUM SETUP AND HOLD TIMES WITH RESPECT TO CLOCK RISING EDGE Notes 9, 10 (ns)
L4C381-20
Input
L4C381-15
FTAB = 0
FTAB = 1
FTAB = 0
FTAB = 1
Setup Hold
Setup Hold
Setup Hold
Setup Hold
A15-A0, B15-B0
5
0
14
0
5
0
12
0
C0
12
0
12
0
10
0
10
0
S2-S0, OSA, OSB
15
0
15
0
12
0
12
0
ENA, ENB, ENF
5
0
5
0
5
0
5
0
TRI-STATE ENABLE/DISABLE TIMES Notes 9, 10, 11 (ns)
CLOCK CYCLE TIME AND PULSE WIDTH Notes 9, 10 (ns)
L4C381-20
L4C381-15
L4C381-20
L4C381-15
tENA
8
6
Minimum Cycle Time
18
14
tDIS
8
6
Highgoing Pulse
5
4
Lowgoing Pulse
5
4
Arithmetic Logic Units
5
08/16/2000–LDS.381-P
L4C381
DEVICES INCORPORATED
16-bit Cascadable ALU
SWITCHING CHARACTERISTICS — MILITARY OPERATING RANGE (–55°C to +125°C)
GUARANTEED MAXIMUM C123456789012345678901234567890121234567890123456789012345678901212345678901234
OMBINATIONAL DELAYS Notes 9, 10 (ns)
123456789012345678901234567890121234567890123456789012345678901212345678901234
L4C381-65*
To Output 123456789012345678901234567890121234567890123456789012345678901212345678901234
L4C381-45*
L4C381-30*
123456789012345678901234567890121234567890123456789012345678901212345678901234
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F15-F0 P, G OVF, Z C16 F15-F0 P, G OVF, Z C16 F15-F0 P, G OVF, Z C16
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FTAB = 0, FTF = 0
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
37
44
63
45
28
34
50
34
26
28
34
28
Clock
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
—
—
42
25
—
—
32
23
—
—
22
22
C0
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
S2-S0, OSA, OSB
—
48
48
48
—
38
38
38
—
28
28
28
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
FTAB = 0, FTF = 1
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
Clock
68
44
63
45
56
34
50
34
34
28
34
28
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
C0
42
—
42
25
32
—
32
23
26
—
22
22
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
S2-S0, OSA, OSB
66
48
48
48
46
38
38
38
30
28
28
28
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
FTAB = 1, FTF = 0
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
—
44
56
44
—
32
46
36
—
28
28
28
A15-A0, B15-B0
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
Clock
37
—
—
—
28
—
—
—
26
—
—
—
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
C0
—
—
42
25
—
—
32
23
—
—
22
22
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
S2-S0, OSA, OSB
—
48
48
48
—
38
38
38
—
28
28
28
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
FTAB = 1, FTF = 1
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
A15-A0, B15-B0
65
44
56
44
45
32
46
36
30
28
28
28
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
Clock (OSA, OSB = 0) 123456789012345678901234567890121234567890123456789012345678901212345678901234
68
44
63
45
56
34
50
34
34
28
34
28
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
C0
42
—
42
25
32
—
32
23
26
—
22
22
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
S2-S0, OSA, OSB
66
48
48
48
46
38
38
38
30
28
28
28
123456789012345678901234567890121234567890123456789012345678901212345678901234
From Input
GUARANTEED MINIMUM SETUP
AND HOLD TIMES WITH RESPECT TO CLOCK RISING EDGE Notes 9, 10 (ns)
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
Input
A15-A0, B15-B0
C0
S2-S0, OSA, OSB
ENA, ENB, ENF
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
L4C381-65*
L4C381-45*
L4C381-30*
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
FTAB = 0
FTAB = 1
FTAB = 0
FTAB = 1
FTAB = 0
FTAB = 1
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
Setup Hold Setup Hold Setup Hold Setup Hold Setup Hold Setup Hold
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
10
3
43
3
8
3
33
3
8
3
20
3
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
25
0
25
0
20
0
20
0
12
0
12
0
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
50
0
50
0
36
0
36
0
20
0
20
0
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234
12
2
12
2
10
2
10
2
10
2
10
2
123456789012345678901234567890121234567890123456789012345678901212345678901234
TRI-STATE1234567890123456789012345678901212345
ENABLE/DISABLE TIMES Notes 9, 10, 11 (ns)
1234567890123456789012345678901212345
1234567890123456789012345678901212345
L4C381-65* L4C381-45* L4C381-30*
1234567890123456789012345678901212345
1234567890123456789012345678901212345
1234567890123456789012345678901212345
1234567890123456789012345678901212345
tENA
22
20
18
1234567890123456789012345678901212345
1234567890123456789012345678901212345
1234567890123456789012345678901212345
1234567890123456789012345678901212345
tDIS
22
20
18
1234567890123456789012345678901212345
1234567890123456789012345678901212345
123456789012345678901234
123456789012345678901234
123456789012345678901234
*DISCONTINUED SPEED GRADE
123456789012345678901234
CLOCK CYCLE TIME
AND PULSE WIDTH Notes 9, 10 (ns)
12345678901234567890123456789012123456
12345678901234567890123456789012123456
12345678901234567890123456789012123456
L4C381-65* L4C381-45* L4C381-30*
12345678901234567890123456789012123456
12345678901234567890123456789012123456
12345678901234567890123456789012123456
Minimum Cycle Time12345678901234567890123456789012123456
52
38
26
12345678901234567890123456789012123456
12345678901234567890123456789012123456
12345678901234567890123456789012123456
Highgoing Pulse 12345678901234567890123456789012123456
20
15
12
12345678901234567890123456789012123456
12345678901234567890123456789012123456
12345678901234567890123456789012123456
12345678901234567890123456789012123456
Lowgoing Pulse
20
15
12
12345678901234567890123456789012123456
12345678901234567890123456789012123456
Arithmetic Logic Units
6
08/16/2000–LDS.381-P
L4C381
DEVICES INCORPORATED
16-bit Cascadable ALU
SWITCHING CHARACTERISTICS — MILITARY OPERATING RANGE (–55°C to +125°C)
GUARANTEED MAXIMUM C1234567890123456789012345678901212345678901234567890
OMBINATIONAL DELAYS Notes 9, 10 (ns)
1234567890123456789012345678901212345678901234567890
To Output 1234567890123456789012345678901212345678901234567890
L4C381-25*
L4C381-20*
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
F15-F0 P, G OVF, Z C16 F15-F0 P, G OVF, Z C16
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
FTAB = 0, FTF = 0
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
14
24
24
24
14
20
20
20
Clock
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
—
—
18
18
—
—
16
16
C0
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
S2-S0, OSA, OSB
—
22
24
22
—
18
20
18
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
FTAB = 0, FTF = 1
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
Clock
25
24
24
24
20
20
20
20
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
C0
21
—
18
18
17
—
16
16
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
S2-S0, OSA, OSB
25
22
24
22
20
18
20
18
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
FTAB = 1, FTF = 0
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
—
20
25
22
—
17
20
17
A15-A0, B15-B0
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
Clock
14
—
—
—
14
—
—
—
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
C0
—
—
18
18
—
—
16
16
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
S2-S0, OSA, OSB
—
22
24
22
—
18
20
18
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
FTAB = 1, FTF = 1
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
A15-A0, B15-B0
25
20
25
22
20
17
20
17
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
Clock (OSA, OSB = 0) 1234567890123456789012345678901212345678901234567890
25
24
24
24
20
20
20
20
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
C0
21
—
18
18
17
—
16
16
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
S2-S0, OSA, OSB
25
22
24
22
20
18
20
18
1234567890123456789012345678901212345678901234567890
From Input
GUARANTEED MINIMUM SETUP
AND HOLD TIMES WITH RESPECT TO CLOCK RISING EDGE Notes 9, 10 (ns)
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
Input
A15-A0, B15-B0
C0
S2-S0, OSA, OSB
ENA, ENB, ENF
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
L4C381-25*
L4C381-20*
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
FTAB = 0
FTAB = 1
FTAB = 0
FTAB = 1
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
Setup Hold Setup Hold Setup Hold Setup Hold
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
7
2
14
2
6
2
12
2
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
14
0
14
0
12
0
12
0
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
19
0
19
0
16
0
16
0
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
7
0
7
0
6
0
6
0
1234567890123456789012345678901212345678901234567890
1234567890123456789012345678901212345678901234567890
TRI-STATE1234567890123456789012345
ENABLE/DISABLE TIMES Notes 9, 10, 11 (ns)
1234567890123456789012345
1234567890123456789012345
L4C381-25* L4C381-20*
1234567890123456789012345
1234567890123456789012345
1234567890123456789012345
1234567890123456789012345
tENA
14
10
1234567890123456789012345
1234567890123456789012345
1234567890123456789012345
1234567890123456789012345
tDIS
14
10
1234567890123456789012345
1234567890123456789012345
123456789012345678901234
123456789012345678901234
123456789012345678901234
*DISCONTINUED SPEED GRADE
123456789012345678901234
CLOCK CYCLE TIME
AND PULSE WIDTH Notes 9, 10 (ns)
12345678901234567890123456
12345678901234567890123456
12345678901234567890123456
L4C381-25* L4C381-20*
12345678901234567890123456
12345678901234567890123456
12345678901234567890123456
Minimum Cycle Time12345678901234567890123456
20
18
12345678901234567890123456
12345678901234567890123456
12345678901234567890123456
Highgoing Pulse 12345678901234567890123456
8
6
12345678901234567890123456
12345678901234567890123456
12345678901234567890123456
12345678901234567890123456
Lowgoing Pulse
8
6
12345678901234567890123456
12345678901234567890123456
Arithmetic Logic Units
7
08/16/2000–LDS.381-P
L4C381
DEVICES INCORPORATED
16-bit Cascadable ALU
NOTES
1. Maximum Ratings indicate stress
specifications only. Functional operation of these products at values beyond
those indicated in the Operating Conditions table is not implied. Exposure to
maximum rating conditions for extended periods may affect reliability.
9. AC specifications are tested with
input transition times less than 3 ns,
output reference levels of 1.5 V (except
tDIS test), and input levels of nominally
0 to 3.0 V. Output loading may be a
resistive divider which provides for
specified IOH and IOL at an output
voltage of VOH min and VOL max
2. The products described by this spec- respectively. Alternatively, a diode
ification include internal circuitry de- bridge with upper and lower current
signed to protect the chip from damagsources of IOH and I OL respectively,
ing substrate injection currents and ac- and a balancing voltage of 1.5 V may be
cumulations of static charge. Neverthe- used. Parasitic capacitance is 30 pF
less, conventional precautions should minimum, and may be distributed.
be observed during storage, handling,
and use of these circuits in order to This device has high-speed outputs caavoid exposure to excessive electrical pable of large instantaneous current
stress values.
pulses and fast turn-on/turn-off times.
As a result, care must be exercised in the
3. This device provides hard clamping of testing of this device. The following
transient undershoot and overshoot. In- measures are recommended:
put levels below ground or above VCC
will be clamped beginning at –0.6 V and a. A 0.1 µF ceramic capacitor should be
VCC + 0.6 V. The device can withstand installed between VCC and Ground
indefinite operation with inputs in the leads as close to the Device Under Test
range of –0.5 V to +7.0 V. Device opera- (DUT) as possible. Similar capacitors
tion will not be adversely affected, how- should be installed between device VCC
ever, input current levels will be well in and the tester common, and device
ground and tester common.
excess of 100 mA.
4. Actual test conditions may vary from b. Ground and VCC supply planes
those designated but operation is guar- must be brought directly to the DUT
anteed as specified.
socket or contactor fingers.
5. Supply current for a given applica- c. Input voltages should be adjusted to
tion can be accurately approximated by: compensate for inductive ground and VCC
noise to maintain required DUT input
NCV2 F
levels relative to the DUT ground pin.
4
where
10. Each parameter is shown as a minN = total number of device outputs
C = capacitive load per output
V = supply voltage
F = clock frequency
6. Tested with all outputs changing every cycle and no load, at a 5 MHz clock
rate.
7. Tested with all inputs within 0.1 V of
VCC or Ground, no load.
8. These parameters are guaranteed
but not 100% tested.
11. For the tENA test, the transition is
measured to the 1.5 V crossing point
with datasheet loads. For the tDIS test,
the transition is measured to the
±200mV level from the measured
steady-state output voltage with
±10mA loads. The balancing voltage, V TH , is set at 3.5 V for Z-to-0
and 0-to-Z tests, and set at 0 V for Zto-1 and 1-to-Z tests.
12. These parameters are only tested at
the high temperature extreme, which is
the worst case for leakage current.
FIGURE A. OUTPUT LOADING CIRCUIT
S1
DUT
IOL
VTH
CL
IOH
FIGURE B. THRESHOLD LEVELS
tENA
OE
Z
tDIS
1.5 V
1.5 V
3.5V Vth
0
1.5 V
1.5 V
Z
1
VOL*
0.2 V
VOH*
0.2 V
0
Z
1
Z
0V Vth
VOL* Measured VOL with IOH = –10mA and IOL = 10mA
VOH* Measured VOH with IOH = –10mA and IOL = 10mA
imum or maximum value. Input requirements are specified from the point
of view of the external system driving
the chip. Setup time, for example, is
specified as a minimum since the external system must supply at least that
much time to meet the worst-case requirements of all parts. Responses from
the internal circuitry are specified from
the point of view of the device. Output
delay, for example, is specified as a
maximum since worst-case operation of
any device always provides data within
that time.
Arithmetic Logic Units
8
08/16/2000–LDS.381-P
L4C381
DEVICES INCORPORATED
CASCADING
THE
16-bit Cascadable ALU
L4C381
Cascading the L4C381 to 32 bits is
accomplished simply by connecting
the C16 output of the least significant
slice to the C0 input of the most significant slice. The S2-S0, OSA, OSB,
ENA, ENB, and ENF lines are
common to both devices. The Zero
output flags should be logically
ANDed to produce the Zero flag for
the 32-bit result. The OVF and C16
outputs of the most significant slice
are valid for the 32-bit result.
Propagation delay calculations for this
configuration require two steps: First
determine the propagation delay from
the input of interest to the C16 output
of the lower slice. Add this number
to the delay from the C0 input of the
upper slice to the output of interest
(of the C0 setup time, if the F register
is used). The sum gives the overall
input-to-output delay (or setup time)
for the 32-bit configuration. This
method gives a conservative result,
since the C16 output is very lightly
loaded. Formulas for calculation of
all critical delays for a 32-bit system
are shown in Figures 4A through 4D.
Cascading to greater than 32 bits can
be accomplished in two ways: The
simplest (but slowest) method is to
simply connect the C16 output of each
slice to the C0 input of the next more
significant slice. Propagation delays
are calculated as for the 32-bit case,
except that the C0 to C16 delays for all
intermediate slices must be added to
the overall delay for each path. A
faster method is to use an external
carry-lookahead generator. The P and
G outputs of each slice are connected
as inputs to the CLA generator, which
in turn produces the C0 inputs for
each slice except the least significant.
The C16 outputs are not used in this
case, except for the most significant
one, which is the carry out of the
overall system. The carry in to the
system is connected to the C0 input of
the least significant slice, and also to
the carry lookahead generator.
Propagation delays for this configuration are the sum of the time to P, G,
for the least significant slice, the
propagation delay of the carry lookahead generator, and the C0 to output
time of the most significant slice.
Arithmetic Logic Units
9
08/16/2000–LDS.381-P
L4C381
DEVICES INCORPORATED
FIGURE 4A.
16-bit Cascadable ALU
FTAB = 0, FTF = 0
From
Clock
Clock
C0
S2-S0, OSA, OSB
A, B
C0
S2-S0, OSA, OSB
ENA, ENB, ENF
Minimum cycle time
To
➞ F
➞ Other
➞ Other
➞ Other
Setup time
Setup time
Setup time
Setup time
Calculated Specification Limit
Same as 16-bit case
(Clock ➞ C16) + (C0 ➞ Out)
(C0 ➞ C16) + (C0 ➞ Out)
(S2-S0, OSA, OSB ➞ C16) + (C0 ➞ Out)
Same as 16-bit case
(C0 ➞ C16) + (C0 Setup time)
(S2-S0, OSA, OSB ➞ C16) + (C0 Setup time)
Same as 16-bit case
(Clock ➞ C16) + (C0 Setup time)
A 31 -A 16
B 31 -B 16
A 15 -A 0
D
Q
D
D
Q
Q
A
B
C0
F
D
MOST
SIGNIFICANT
SLICE
B 15 -B 0
D
Q
A
C 16
F
B
C0
D
CLOCK
Q
FIGURE 4B.
=
=
=
=
=
=
=
=
=
C0, S 0 –S 2
OSA, OSB
CLOCK
Q
16
CLOCK
LEAST
SIGNIFICANT
SLICE
16
F 15 -F 0
F 31 -F 16
FTAB = 0, FTF = 1
From
Clock
Clock
C0
C0
S2-S0, OSA, OSB
S2-S0, OSA, OSB
A, B
C0
S2-S0, OSA, OSB
ENA, ENB, ENF
Minimum cycle time
To
➞ F
➞ Other
➞ F
➞ Other
➞ F
➞ Other
Setup time
Setup time
Setup time
Setup time
A 31 -A 16
B 31 -B 16
A 15 -A 0
D
Q
D
D
Q
Q
A
F
MOST
SIGNIFICANT
SLICE
Calculated Specification Limit
(Clock ➞ C16) + (C0 ➞ F)
(Clock ➞ C16) + (C0 ➞ Out)
(C0 ➞ C16) + (C0 ➞ F)
(C0 ➞ C16) + (C0 ➞ Out)
(S2-S0, OSA, OSB ➞ C16) + (C0 ➞ F)
(S2-S0, OSA, OSB ➞ C16) + (C0 ➞ Out)
Same as 16-bit case
(C0 ➞ C16) + (C0 Setup time)
(S2-S0, OSA, OSB ➞ C16) + (C0 Setup time)
Same as 16-bit case
(Clock ➞ C16) + (C0 Setup time)
=
=
=
=
=
=
=
=
=
=
=
B
C0
B 15 -B 0
D
Q
A
C 16
16
F
16
F 15 -F 0
F 31 -F 16
B
C0
CLOCK
C0, S 0 –S 2
OSA, OSB
LEAST
SIGNIFICANT
SLICE
Arithmetic Logic Units
10
08/16/2000–LDS.381-P
L4C381
DEVICES INCORPORATED
FIGURE 4C.
16-bit Cascadable ALU
FTAB = 1, FTF = 0
From
To
Clock
➞ F
A, B
➞ Other
C0
➞ Other
S2-S0, OSA, OSB
➞ Other
A, B
Setup time
C0
Setup time
S2-S0, OSA, OSB
Setup time
ENA, ENB, ENF
Setup time
Minimum cycle time
(F register accumulate loop)
A 31 -A 16
B 31 -B 16
A
D
FIGURE 4D.
B 15 -B 0
A
C 16
D
Q
16
C0, S 0 –S 2
OSA, OSB
B
C0
F
CLOCK
Q
MOST
SIGNIFICANT
SLICE
A 15 -A 0
B
C0
F
Calculated Specification Limit
Same as 16-bit case
(A, B ➞ C16) + (C0 ➞ Out)
(C0 ➞ C16) + (C0 ➞ Out)
(S2-S0, OSA, OSB ➞ C16) + (C0 ➞ Out)
(A, B ➞ C16) + (C0 Setup time)
(C0 ➞ C16) + (C0 Setup time)
(S2-S0, OSA, OSB ➞ C16) + (C0 Setup time)
Same as 16-bit case
(Clock ➞ C16) + (C0 Setup time)
=
=
=
=
=
=
=
=
=
CLOCK
LEAST
SIGNIFICANT
SLICE
16
F 15 -F 0
F 31 -F 16
FTAB = 1, FTF = 1
From
To
A, B
➞ F
A, B
➞ Other
C0
➞ F
C0
➞ Other
S2-S0, OSA, OSB
➞ F
➞ Other
S2-S0, OSA, OSB
A, B
Setup time
C0
Setup time
S2-S0, OSA, OSB
Setup time
ENA, ENB, ENF
Setup time
Minimum cycle time
(F register accumulate loop)
A 31 -A 16
B 31 -B 16
A
F
MOST
SIGNIFICANT
SLICE
=
=
=
=
=
=
=
=
=
=
=
Calculated Specification Limit
(A, B ➞ C16) + (C0 ➞ F)
(A, B ➞ C16) + (C0 ➞ Out)
(C0 ➞ C16) + (C0 ➞ F)
(C0 ➞ C16) + (C0 ➞ Out)
(S2-S0, OSA, OSB ➞ C16) + (C0 ➞ F)
(S2-S0, OSA, OSB ➞ C16) + (C0 ➞ Out)
(A, B ➞ C16) + (C0 Setup time)
(C0 ➞ C16) + (C0 Setup time)
(S2-S0, OSA, OSB ➞ C16) + (C0 Setup time)
Same as 16-bit case
(Clock ➞ C16) + (C0 Setup time)
A 15 -A 0
B
C0
B 15 -B 0
A
C 16
16
F
16
F 15 -F 0
F 31 -F 16
B
C0
C0, S 0 –S 2
OSA, OSB
LEAST
SIGNIFICANT
SLICE
Arithmetic Logic Units
11
08/16/2000–LDS.381-P
L4C381
DEVICES INCORPORATED
16-bit Cascadable ALU
ORDERING INFORMATION
A8
A7
A6
A5
A4
A3
A2
A1
A0
B15
B14
B13
B12
B11
B10
B9
B8
68-pin
10
9
8
7
6
5
4
3
2
1 68 67 66 65 64 63 62 61
60
11
59
12
58
13
57
14
56
15
55
16
54
17
Top
View
18
19
53
52
51
20
50
21
49
22
48
23
47
24
46
25
45
26
44
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
B7
B6
B5
B4
B3
B2
B1
B0
ENA
ENB
FTAB
OSB
OSA
S2
S1
S0
C0
OE
F15
F14
F13
F12
F11
F10
F9
F8
F7
F6
F5
F4
F3
F2
F1
F0
A9
A10
A11
A12
A13
A14
A15
CLK
VCC
GND
C16
P
G
ZERO
OVF
ENF
FTF
Speed
Plastic J-Lead Chip Carrier
(J2)
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68-pin
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1
2
3
4
5
6
7
8
9
10
11
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A
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A8
A7
B9
A5
A3
A1
B15 B13 B11
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B
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B7
A10
A9
A6
B8
A4
A2
A0
B14 B12 B10
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C
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B5
B6
A12 A11
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D
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A14 A13
B3
B4
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E
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Top View
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CLK A15
B1
B2
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Through Package
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F
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ENA B0
GND VCC
(i.e., Component Side Pinout)
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G
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C16
FTAB ENB
P
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H
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OSA OSB
ZERO G
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J
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S2
S1
ENF OVF
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K
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C0
S0
FTF OE F14 F12 F10
F8
F6
F4
F2
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L
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F0
F15 F13 F11
F9
F7
F5
F3
F1
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Discontinued Package
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Ceramic Pin Grid Array
(G1)
0°C to +70°C — COMMERCIAL SCREENING
20 ns
15 ns
L4C381JC20
L4C381JC15
–55°C to +125°C — COMMERCIAL SCREENING
–55°C to +125°C — MIL-STD-883 COMPLIANT
Arithmetic Logic Units
12
08/16/2000–LDS.381-P