TI TAS5186DDVG4

TM
TAS5186
www.ti.com
SLES136 – MAY 2005
6-Channel, 210-W, Digital-Amplifier Power Stage
•
•
•
•
•
•
•
•
Total Output Power @ 10% THD+N
– 5×30 W @ 6Ω + 1×60 W @ 3Ω
105-dB SNR (A-Weighted)
< 0.05% THD+N @ 1 W
Power Stage Efficiency > 90% Into
Recommended Loads (SE)
Integrated Self-Protection Circuits
– Undervoltage
– Overtemperature
– Overload
– Short Circuit
Integrated Active-Bias Control to Avoid DC
Pop
Thermally Enhanced 44-pin HTSSOP Package
EMI-Compliant When Used With
Recommended System Design
APPLICATIONS
•
•
DVD Receiver
Home Theater in a Box
DESCRIPTION
The TAS5186 is a high-performance, six-channel,
digital-amplifier power stage with an improved protection system. The TAS5186 is capable of driving a
6-Ω, single-ended load up to 30 W per each
front/satellite channel and a 3-Ω, single-ended
subwoofer greater than 60 W at 10% THD+N performance.
A low-cost, high-fidelity audio system can be built
using a TI chipset comprising a modulator (e.g.,
TAS5086) and the TAS5186. This device does not
require power-up sequencing because of the internal
power-on reset.
The TAS5186 requires only simple passive demodulation filters on its outputs to deliver high-quality,
high-efficiency audio amplification. The efficiency of
the TAS5186 is greater than 90% when driving 6-Ω
satellites and a 3-Ω subwoofer speaker.
The TAS5186 has an innovative protection system
integrated on-chip, safeguarding the device against a
wide range of fault conditions that could damage the
system. These safeguards are short-circuit protection,
overload protection, undervoltage protection, and
overtemperature protection. The TAS5186 has a new
proprietary current-limiting circuit that reduces the
possibility of device shutdown during high-level music
transients. A new programmable overcurrent detector
allows the use of lower-cost inductors in the demodulation output filter.
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
20
THD+N – Total Harmonic Distortion + Noise – %
FEATURES
PVDD = 40 V
TC = 75°C
10
1
6 Ω Satellite
0.1
3 Ω Subwoofer
0.01
1
10
PO – Output Power – W
70
G012
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD, PurePath Digital are trademarks of Texas Instruments.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005, Texas Instruments Incorporated
TAS5186
www.ti.com
SLES136 – MAY 2005
These devices have limited built-in ESD protection. The leads should be shorted together or the device
placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
GENERAL INFORMATION
TERMINAL ASSIGNMENT
The TAS5186 is available in a thermally enhanced 44-pin HTSSOP PowerPAD™ package. The heat slug is
located on the top side of the device for convenient thermal coupling to a heatsink.
DDV PACKAGE
(TOP VIEW)
PGND_EF
PWM_F
GVDD_DEF
VDD
PWM_E
PWM_D
RESET
M3
M2
M1
GND
AGND
VREG
OC_ADJ
SD
OTW
PWM_C
PWM_B
PWM_A
GVDD_ABC
BST_BIAS
OUT_BIAS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
BST_F
PVDD_F
OUT_F
PGND_EF
OUT_E
PVDD_E
BST_E
BST_D
PVDD_D
OUT_D
PGND_D
PGND_C
OUT_C
PVDD_C
BST_C
BST_B
PVDD_B
OUT_B
PGND_AB
OUT_A
PVDD_A
BST_A
P0016-01
2
TAS5186
www.ti.com
SLES136 – MAY 2005
GENERAL INFORMATION (continued)
TERMINAL FUNCTIONS
TERMINAL
NAME
NO.
TYPE (1)
DESCRIPTION
AGND
12
P
Analog ground
BST_A
23
P
HS bootstrap supply (BST), capacitor to OUT_A required
BST_B
29
P
HS bootstrap supply (BST), external capacitor to OUT_B required
BST_BIAS
21
P
BIAS bootstrap supply, external capacitor to OUT_BIAS required
BST_C
30
P
HS bootstrap supply (BST), external capacitor to OUT_C required
BST_D
37
P
HS bootstrap supply (BST), external capacitor to OUT_D required
BST_E
38
P
HS bootstrap supply (BST), external capacitor to OUT_E required
BST_F
44
P
HS bootstrap supply (BST), external capacitor to OUT_F required
GND
11
P
Chip ground
GVDD_ABC
20
P
Gate drive voltage supply
GVDD_DEF
3
P
Gate drive voltage supply
M1
10
I
Mode selection pin
M2
9
I
Mode selection pin
M3
8
I
Mode selection pin
OC_ADJ
14
O
Overcurrent threshold programming pin, resistor to ground required
OTW
16
O
Overtemperature warning open-drain output signal, active-low
OUT_A
25
O
Output, half-bridge A, satellite
OUT_B
27
O
Output, half-bridge B, satellite
OUT_BIAS
22
O
BIAS half-bridge output pin
OUT_C
32
O
Output, half-bridge C, subwoofer
OUT_D
35
O
Output, half-bridge D, satellite
OUT_E
40
O
Output, half-bridge E, satellite
OUT_F
42
O
Output, half-bridge F, satellite
PGND_AB
26
P
Power ground
PGND_C
33
P
Power ground
PGND_D
34
P
Power ground
PGND_EF
1, 41
P
Power ground
PVDD_A
24
P
Power-supply input for half-bridge A
PVDD_B
28
P
Power-supply input for half-bridge B
PVDD_C
31
P
Power-supply input for half-bridge C
PVDD_D
36
P
Power-supply input for half-bridge D
PVDD_E
39
P
Power-supply input for half-bridge E
PVDD_F
43
P
Power-supply input for half-bridge F
PWM_A
19
I
PWM input signal for half-bridge A
PWM_B
18
I
PWM input signal for half-bridge B
PWM_C
17
I
PWM input signal for half-bridge C
PWM_D
6
I
PWM input signal for half-bridge D
PWM_E
5
I
PWM input signal for half-bridge E
PWM_F
2
I
PWM input signal for half-bridge F
RESET
7
I
Reset signal (active-low logic)
SD
15
O
Shutdown open-drain output signal, active-low
VDD
4
P
Power supply for digital voltage regulator
VREG
13
O
Digital regulator supply filter pin, output
(1)
I = input; O = output; P = power
3
TAS5186
www.ti.com
SLES136 – MAY 2005
Table 1. MODE Selection Pins
MODE PINS (1)
MODE
M2
M3
0
0
2.1 mode
Channels A, B, and C enabled; channels D, E, and F disabled
0
1
5.1 mode
All channels enabled
1
0/1
Reserved
(1)
NAME
DESCRIPTION
M1 must always be connected to ground. 0 indicates a pin connected to GND; 1 indicates a pin connected to VREG.
PACKAGE HEAT DISSIPATION RATINGS (1)
(1)
(2)
PARAMETER
TAS5186DDV
RθJC (°C/W)—1 satellite (sat.) FET only
10.3
RθJC (°C/W)—1 subwoofer (sub.) FET only
5.2
RθJC (°C/W)—1 sat. half-bridge
5.2
RθJC (°C/W)—1 sub. half-bridge
2.6
RθJC (°C/W)—5 sat. half-bridges + 1 sub.
1.74
Typical pad area (2)
34.9 mm2
JC is junction-to-case, CH is case-to-heatsink.
RθCH is an important consideration. Assume a 2-mil thickness of typical thermal grease between the pad area and the heatsink. The
RθCH with this condition is typically 2°C/W for this package.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1)
TAS5186
VDD to AGND
–0.3 V to 13.2 V
GVDD_X to AGND
–0.3 V to 13.2 V
PVDD_X to PGND_X
(2)
–0.3 V to 50 V
OUT_X to PGND_X
(2)
–0.3 V to 50 V
BST_X to PGND_X
(2)
–0.3 V to 63.2 V
VREG to AGND
–0.3 V to 4.2 V
PGND_X to GND
–0.3 V to 0.3 V
PGND_X to AGND
–0.3 V to 0.3 V
GND to AGND
–0.3 V to 0.3 V
PWM_X, OC_ADJ, M1, M2, M3 to AGND
–0.3 V to 4.2 V
RESET, SD, OTW to AGND
Maximum operating junction temperature range (TJ )
Storage temperature
–0.3 V to 7 V
0 to 125°C
–40°C to 125°C
Lead temperature – 1,6 mm (1/16 inch) from case for 10 seconds
260°C
Minimum PWM pulse duration, low
30 ns
(1)
(2)
4
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
These voltages represent the dc voltage + peak ac waveform measured at the terminal of the device in all conditions.
TAS5186
www.ti.com
SLES136 – MAY 2005
TYPICAL SYSTEM DIAGRAM
BST_BIAS
OUT_BIAS
3
12 V
1 µF
20
1 µF
10 µF
+
0.1 µF
0.1 µF
14
PVDD_F
GVDD_ABC
OUT_F
9
11
PGND_EF
VREG
PVDD_E
OC_ADJ
OUT_E
PVDD_D
TAS5186
BST_D
PGND_D
PWM2
PWM3
PurePath
Digital
Modulator
TAS5086
PWM4
PWM5
PWM6
2
5
6
17
18
19
PWM_F
PVDD_C
PWM_E
BST_C
PWM_D
OUT_C
PWM_C
PGND_C
PVDD_B
VALID2
VALID1
7
8
16
RESET
M3
BST_B
OUT_B
SD
PGND_AB
OTW
PVDD_A
To µP
39
BST_A
OUT_A
270 µF
+
0.47 µF
40
0.47 µF
35
31
0.47 µF
32
33
28
0.47 µF
27
24
330 Ω
1000 µF
330 Ω
SAT
1000 µF
270 µF
270 µF
330 Ω
1 µF
+
0.47 µF
25
33 nF
SUB
22 µH
0.1 µF
23
270 µF
270 µF
1 µF
+
26
SAT
22 µH
0.1 µF
29
330 Ω
1 µF
+
33 nF
270 µF
22 µH
0.1 µF
30
270 µF
1 µF
+
33 nF
SAT
22 µH
0.1 µF
37
34
330 Ω
0.1 µF
38
36
270 µF
1 µF
1
33 nF
15
22 µH
PWM_B
PWM_A
SAT
41
33 nF
M2
0.47 µF
42
M1
GND
+
44
AGND
OUT_D
PWM1
680 Ω
0.1 µF
33 nF
15 kΩ
10
43
VDD
BST_E
12
33 nF
PVDD
PGND_EF
13
22
GVDD_DEF
BST_F
4
21
SAT
22 µH
270 µF
270 µF
330 Ω
1 µF
S0061-01
PurePath Digital™
5
TAS5186
www.ti.com
SLES136 – MAY 2005
FUNCTIONAL BLOCK DIAGRAM
Undervoltage
Protection
OTW
VDD
Internal Pullup
Resistors to VREG
SD
Protection
and
I/O Logic
M1
M2
Power On
Reset
VREG
VREG
AGND
Temperature
Sense
GND
M3
Overload
Protection
RESET
ISense
OC_ADJ
GVDD_DEF
BST_F
PWM_F
PWM
Receiver
PVDD_F
Control
Timing
Gate
Drive
OUT_F
PGND_EF
BST_E
PWM_E
PWM
Receiver
PVDD_E
Control
Timing
Gate
Drive
OUT_E
PGND_EF
BST_D
PWM_D
PWM
Receiver
PVDD_D
Control
Timing
Gate
Drive
OUT_D
PGND_D
GVDD_ABC
BST_C
PVDD_C
PWM_C
PWM
Receiver
Control
Timing
Gate
Drive
OUT_C
PGND_C
BST_B
PVDD_B
PWM_B
PWM
Receiver
Control
Timing
Gate
Drive
OUT_B
PGND_AB
BST_A
PVDD_A
PWM_A
PWM
Receiver
Control
Timing
Gate
Drive
OUT_A
BST_BIAS
Control
Timing
Gate
Drive
OUT_BIAS
B0034-01
6
TAS5186
www.ti.com
SLES136 – MAY 2005
RECOMMENDED OPERATING CONDITIONS
MIN
TYP
MAX
PVDD_X
Half-bridge supply, SE
DC supply voltage at pin(s)
40
V
GVDD
Gate drive and guard ring supply voltage
DC voltage at pin(s)
10.8
12
13.2
V
VDD
Digital regulator supply
DC supply voltage at pin
10.8
12
13.2
V
VPU
Pullup voltage supply
Any value of RPU,EXT within
recommended range
3
5
5.5
V
RL,SAT
Resistive load impedance, satellite
channels (1)
Recommended demodulation filter
4
6
Ω
RL,SUB
Resistive load impedance, subwoofer
channel
Recommended demodulation filter
2.25
3
Ω
Loutput
Demodulation filter inductance
5
22
µH
Coutput,sat
Demodulation filter capacitance
1
µF
Coutput,sub
Demodulation filter capacitance
0.47
FPWM
PWM frame rate
(1)
0
UNIT
Minimum output inductance under
short-circuit condition
192
384
µF
432
kHz
Load impedance outside range listed might cause shutdown due to OLP, OTE, or NLP.
AUDIO SPECIFICATION
PVDD_X = 40 V, GVDD = 12 V, audio frequency = 1 kHz, AES17 measurement filter, FPWM = 384 kHz, case temperature =
75°C. Audio performance is recorded as a chipset, using TAS5086 PWM processor with an effective modulation index limit of
97%. All performance is in accordance with the foregoing specifications and recommended operating conditions unless
otherwise specified.
PARAMETER
PO,sat
PO,sub
Power output per satellite channel
Power output, subwoofer
Total harmonic distortion + noise,
satellite
THD + N
Total harmonic distortion + noise,
subwoofer
CONDITIONS
MIN
TYP
RL = 6 Ω, 10% THD, clipped input signal
30
RL = 8 Ω, 10% THD, clipped input signal
25
RL = 6 Ω, 0 dBFS, unclipped input signal
25
RL = 8 Ω, 0 dBFS, unclipped input signal
20
RL = 3 Ω, 10% THD, clipped input signal
60
RL = 4 Ω, 10% THD, clipped input signal
52
RL = 3 Ω, 0 dBFS, unclipped input signal
50
RL = 4 Ω, 0 dBFS, unclipped input signal
40
RL = 6 Ω, PO = 25 W
RL = 6 Ω, 1 W
RL = 3 Ω, PO = 50 W
RL = 3 Ω, 1 W
MAX
UNIT
W
W
0.3%
0.03%
0.5%
0.03%
Output integrated noise, satellite
A-weighted
55
Output integrated noise, subwoofer
A-weighted
60
SNR
System signal-to-noise ratio
A-weighted
105
dB
DNR
Dynamic
range (1)
A-weighted, –60 dBFs input signal
Pidle
Power dissipation due to idle losses
(IPVDDX)
Vn
(1)
(2)
µV
105
dB
PO = 0 W, all channels running 5.1 mode (2)
8
W
PO = 0 W, 2.1 mode
4
W
SNR is calculated relative to 0-dBFS input level.
Actual system idle losses are affected by core losses of output inductors.
7
TAS5186
www.ti.com
SLES136 – MAY 2005
ELECTRICAL CHARACTERISTICS
FPWM = 384 kHz, GVDD = 12 V, VDD = 12 V, TC (case temperature) = 25°C, unless otherwise noted. All performance is in
accordance with recommended operating conditions, unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
3
UNIT
INTERNAL VOLTAGE REGULATOR AND CURRENT CONSUMPTION
VREG
Voltage regulator, only used as reference node
IVDD
VDD supply current
IGVDD_X
Gate supply current per half-bridge
IPVDD_X
Half-bridge idle current
VDD = 12 V
3.3
3.6
Operating, 50% duty cycle
7
20
Idle, reset mode
6
16
50% duty cycle
5
22
Idle, reset mode
1
3
50% duty cycle, without output filter or load, 5.1
mode
180
50% duty cycle, without output filter or load, 2.1
mode
100
V
mA
mA
mA
OUTPUT STAGE MOSFETs
RDSon, LS Sat
Drain-to-source resistance, low side, satellite
TJ = 25°C, includes metallization resistance
210
mΩ
RDSon, HS Sat
Drain-to-source resistance, high side, satellite
TJ = 25°C, includes metallization resistance
210
mΩ
RDson, LS Sub
Drain-to-source resistance, low side, subwoofer
TJ = 25°C, includes metallization resistance
110
mΩ
RDson, HS Sub
Drain-to-source resistance, high side, subwoofer
TJ = 25°C, includes metallization resistance
110
mΩ
I/O PROTECTION
VUVP,
G
VUVP,
hyst
Undervoltage protection limit GVDD_X
10
V
Undervoltage protection hysteresis
250
mV
OTW (1)
Overtemperature warning
125
°C
OTWhyst (1)
Temperature drop needed below OTW temp. for
OTW to be inactive after the OTW event
25
°C
OTE (1)
Overtemperature error
155
°C
OTEHYST (1)
Temperature drop needed below OTE temp. for SD
to be released after the OTE event
25
°C
OLCP
Overload protection counter
(1)
1.25
ms
Overcurrent limit protection, sat.
Resistor programmable, high end,
Rocp = 15 kΩ
5
A
Overcurrent limit protection, sub.
Resistor programmable, high end,
Rocp = 15 kΩ
8
A
IOC
IOCT
Overcurrent response time
Rocp
OC programming resistor range
210
Resistor tolerance = 5%
ns
15
kΩ
STATIC DIGITAL SPECIFICATION
VIH
High-level input voltage
VIL
Low-level input voltage
ILEAK
Input leakage current
PWM_X, M1, M2, M3, RESET
Static condition
2
0.8
–80
80
V
µA
OTW/SHUTDOWN (SD)
RINT_PU
Internal pullup resistor to DREG (3.3 V) for SD and
OTW
VOH
High-level output voltage
VOL
Low-level output voltage
FANOUT
Device fanout OTW, SD
(1)
8
Specified by design.
26
Internal pullup resistor only
3.3
3.6
IO = 4 mA
0.2
0.4
No external pullup
30
External pullup: 4.7-kΩ resistor to 5 V
3
kΩ
4.5
5
V
Devices
TAS5186
www.ti.com
SLES136 – MAY 2005
TYPICAL CHARACTERISTICS, 5.1 MODE
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
20
Satellite
PVDD = 40 V
TC = 75°C
10
THD+N – Total Harmonic Distortion + Noise – %
THD+N – Total Harmonic Distortion + Noise – %
20
1
6Ω
0.1
8Ω
0.01
1
3Ω
0.1
4Ω
0.01
1
10
40
PO – Output Power – W
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
0
1
10
70
PO – Output Power – W
G001
Figure 1.
Figure 2.
OUTPUT POWER
vs
SUPPLY VOLTAGE
OUTPUT POWER
vs
SUPPLY VOLTAGE
G002
70
Satellite
1 Channel
TC = 75°C
THD+N = 10%
Subwoofer
1 Channel
TC = 75°C
THD+N = 10%
65
60
55
PO – Output Power – W
PO – Output Power – W
Subwoofer
PVDD = 40 V
TC = 75°C
10
6Ω
8Ω
50
45
40
35
30
25
3Ω
20
4Ω
15
10
5
0
0
5
10
15
20
25
30
35
40
PVDD – Supply Voltage – V
0
5
10
15
20
30
35
40
G004
G003
Figure 3.
25
PVDD – Supply Voltage – V
Figure 4.
9
TAS5186
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SLES136 – MAY 2005
TYPICAL CHARACTERISTICS, 5.1 MODE (continued)
OUTPUT POWER
vs
SUPPLY VOLTAGE
OUTPUT POWER
vs
SUPPLY VOLTAGE
55
28
Satellite
1 Channel
TC = 75°C
Unclipped Input Signal
26
24
45
20
PO – Output Power – W
PO – Output Power – W
22
18
16
14
12
10
Subwoofer
1 Channel
TC = 75°C
Unclipped Input Signal
50
6Ω
8
8Ω
6
40
35
30
25
20
3Ω
15
4Ω
10
4
5
2
0
0
0
5
10
15
20
25
30
35
40
0
PVDD – Supply Voltage – V
5
10
15
20
25
30
G005
40
G006
Figure 5.
Figure 6.
SYSTEM EFFICIENCY
vs
TOTAL OUTPUT POWER
SYSTEM POWER LOSS
vs
TOTAL OUTPUT POWER
40
100
RL(SAT) = 8 Ω
RL(SUB) = 4 Ω
90
System Power Loss – W
70
5.1 Mode
PVDD = 40 V
TC = 25°C
35
RL(SAT) = 6 Ω
RL(SUB) = 3 Ω
80
System Efficiency – %
35
PVDD – Supply Voltage – V
60
50
40
30
30
RL(SAT) = 6 Ω
RL(SUB) = 3 Ω
25
20
RL(SAT) = 8 Ω
RL(SUB) = 4 Ω
15
10
20
5.1 Mode
PVDD = 40 V
TC = 25°C
10
0
0
0
20 40 60 80 100 120 140 160 180 200 220 240
PO – Total Output Power – W
Figure 7.
10
5
G007
0
20 40 60 80 100 120 140 160 180 200 220 240
PO – Total Output Power – W
Figure 8.
G008
TAS5186
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SLES136 – MAY 2005
TYPICAL CHARACTERISTICS, 5.1 MODE (continued)
OUTPUT POWER
vs
CASE TEMPERATURE
OUTPUT POWER
vs
CASE TEMPERATURE
40
80
6Ω
35
60
25
PO – Output Power – W
30
8Ω
20
15
10
Satellite
1 Channel
THD+N = 10%
5
50
4Ω
40
30
20
Subwoofer
1 Channel
THD+N = 10%
10
0
0
20
30
40
50
60
70
80
90
100 110
TC – Case Temperature – °C
20
30
40
50
60
70
80
90
TC – Case Temperature – °C
G009
Figure 9.
100 110
G010
Figure 10.
AMPLITUDE
vs
FREQUENCY
0
Satellite
1 Channel
PVDD = 40 V
TC = 75°C
−10
−20
−30
−40
Amplitude – dB
PO – Output Power – W
3Ω
70
−50
−60
−70
−80
−90
−100
−110
−120
−130
−140
−150
0
2
4
6
8
10
12
14
16
18
20
22
f – Frequency – kHz
G011
Figure 11.
11
TAS5186
www.ti.com
SLES136 – MAY 2005
THEORY OF OPERATION
POWER SUPPLIES
To facilitate system design, the TAS5186 needs only
a 12-V supply in addition to a typical 39-V
power-stage supply. An internal voltage regulator
provides suitable voltage levels for the digital and
low-voltage analog circuitry. Additionally, all circuitry
requiring a floating voltage supply, e.g., the high-side
gate drive, is accommodated by built-in bootstrap
circuitry requiring only a few external capacitors.
In order to provide outstanding electrical and acoustic
characteristics, the PWM signal path including gate
drive and output stage is designed as identical,
independent half-bridges. For this reason, each
half-bridge has separate bootstrap pins (BST_X) and
power-stage supply pins (PVDD_X). Furthermore, an
additional pin (VDD) is provided as power supply for
all common circuits. Although supplied from the same
12-V source, it is highly recommended to separate
GVDD_X and VDD on the printed-circuit board (PCB)
by RC filters (see application diagram for details).
These RC filters provide the recommended
high-frequency isolation. Special attention should be
paid to placing all decoupling capacitors as close to
their associated pins as possible. In general, inductance between the power-supply pins and decoupling
capacitors must be avoided. (See reference board
documentation for additional information.)
For a properly functioning bootstrap circuit, a small
ceramic capacitor must be connected from each
bootstrap pin (BST_X) to the power-stage output pin
(OUT_X). When the power-stage output is low, the
bootstrap capacitor is charged through an internal
diode
connected
between
the
gate-drive
power-supply pin (GVDD_X) and the bootstrap pin.
When the power-stage output voltage is high, the
bootstrap capacitor voltage is shifted above the
output voltage potential and thus provides a suitable
voltage supply for the high-side gate driver. In an
application with PWM switching frequencies in the
range 352 kHz to 384 kHz, it is recommended to use
33-nF ceramic capacitors, size 0603 or 0805, for the
bootstrap capacitor. These 33-nF capacitors ensure
sufficient energy storage, even during minimal PWM
duty cycles, to keep the high-side power stage FET
(LDMOS) fully started during all of the remaining part
of the PWM cycle. In an application running at a
reduced switching frequency, generally 250 kHz to
192 kHz, the bootstrap capacitor might need to be
increased in value. Special attention should be paid
to the power-stage power supply; this includes
component selection, PCB placement and routing. As
indicated, each half-bridge has independent
power-stage supply pins (PVDD_X). For optimal electrical performance, EMI compliance, and system reliability it is important that each PVDD_X pin is
12
decoupled with a 100-nF ceramic capacitor placed as
close as possible to each supply pin on the same
side of the PCB as the TAS5186. It is recommended
to follow the PCB layout of the TAS5186 reference
design. For additional information on the recommended power supply and required components,
see the application diagrams given in this data sheet.
The 12-V supply should be powered from a
low-noise, low-output-impedance voltage regulator.
Likewise, the 39-V power-stage supply is assumed to
have low output impedance and low noise. The
power-supply sequence is not critical due to the
internal power-on-reset circuit. Moreover, the
TAS5186 is fully protected against erroneous
power-stage turnon due to parasitic gate charging.
Thus, voltage-supply ramp rates (dv/dt) are typically
noncritical.
SYSTEM POWER-UP/DOWN SEQUENCE
The TAS5186 does not require a power-up sequence.
The outputs of the H-bridge remain in a
high-impedance state until the gate-drive supply voltage (GVDD_X) and VDD voltage are above the
undervoltage protection (UVP) voltage threshold (see
the Electrical Characteristics section of this data
sheet). Although not specifically required, it is recommended to hold RESET in a low state while
powering up the device.
When the TAS5186 is being used with TI PWM
modulators such as the TAS5086, no special attention to the state of RESET is required, provided that
the chipset is configured as recommended.
Powering Down
The TAS5186 does not require a power-down sequence. The device remains fully operational as long
as the gate-drive supply (GVDD_X) voltage and VDD
voltage are above the undervoltage protection (UVP)
threshold level (see the Electrical Characteristics
section of this data sheet). Although not specifically
required, it is a good practice to hold RESET low
during power down, thus preventing audible artifacts
including pops and clicks
When the TAS5186 is being used with TI PWM
modulators such as the TAS5086, no special attention to the state of RESET is required, provided that
the chipset is configured as recommended.
Error Reporting
The SD and OTW pins are both active-low,
open-drain outputs. Their function is for protection-mode signaling to a PWM controller or other
system-control device.
TAS5186
www.ti.com
SLES136 – MAY 2005
Any fault resulting in device shutdown is signaled by
the SD pin going low. Likewise, OTW goes low when
the device junction temperature exceeds 125°C (see
the following table).
SD
OTW
0
0
Overtemperature (OTE) or overload (OLP) or
undervoltage (UVP)
DESCRIPTION
0
1
Overload (OLP) or undervoltage (UVP)
1
0
Overtemperature warning. Junction temperature
higher than 125°C, typical
1
1
Normal operation. Junction temperature lower than
125°C, typical
It should be noted that asserting RESET low forces
the SD and OTW signals high independently of faults
being present. It is recommended to monitor the
OTW signal using the system microcontroller and to
respond to an overtemperature warning signal by,
e.g., turning down the volume to prevent further
heating of the device that would result in device
shutdown (OTE). To reduce external component
count, an internal pullup resistor to 3.3 V is provided
on both the SD and OTW outputs. Level compliance
for 5-V logic can be obtained by adding external
pullup resistors to 5 V (see the Electrical Characteristics section of this data sheet for further specifications).
Device Protection System
The TAS5186 contains advanced protection circuitry
carefully designed to facilitate system integration and
ease of use, as well as safeguarding the device from
permanent failure due to a wide range of fault
conditions such as short circuit, overload, and
undervoltage. The TAS5186 responds to a fault by
immediately setting the power stage in a
high-impedance state (Hi-Z) and asserting the SD pin
low. In situations other than overload, the device
automatically recovers when the fault condition has
been removed, e.g., the supply voltage has
increasedor the temperature has dropped. For
highest possible reliability, recovering from an overload fault requires external reset of the device no
sooner than 1 second after the shutdown (see the
Device Reset section of this data sheet).
two protection systems. The first protection system
controls the power stage in order to prevent the
output current from further increasing. I.e., it performs
a current-limiting function rather than prematurely
shutting down during combinations of high-level music transients and extreme speaker load-impedance
drops. If the high-current situation persists, i.e., the
power stage is being overloaded, a second protection
system triggers a latching shutdown, resulting in the
power stage being set in the high-impedance (Hi-Z)
state.
For added flexibility, the OC threshold is
programmable within a limited range using a single
external resistor connected between the OC_ADJ pin
and AGND.
OC-Adjust Resistor Values
(kΩ)
Maximum Current Before OC
Occurs (A)
15
5 (sat.), 8 (sub.)
18
4.5 (sat.), 7.5 (sub.)
It should be noted that a properly functioning
overcurrent detector assumes the presence of a
properly designed demodulation filter at the
power-stage output. Short-circuit protection is not
provided directly at the output pins of the power stage
but only on the speaker terminals (after the demodulation filter). It is required to follow certain guidelines
when selecting the OC threshold and an appropriate
demodulation inductor.
• For the lowest-cost bill of materials in terms of
component selection, the OC threshold current
should be limited, considering the power output
requirement and minimum load impedance.
Higher-impedance loads require a lower OC
threshold.
• The demodulation filter inductor must retain at
least 5 µH of inductance at twice the OC
threshold setting.
Most inductors have decreasing inductance with increasing temperature and increasing current
(saturation). To some degree, an increase in temperature naturally occurs when operating at high
output currents, due to inductor core losses and the
dc resistance of the inductor copper winding. A
thorough analysis of inductor saturation and thermal
properties is strongly recommended.
OVERCURRENT (OC) PROTECTION WITH
CURRENT LIMITING AND OVERLOAD DETECTION
Setting the OC threshold too low might cause issues
such as lack of output power and/or unexpected
shutdowns due to sensitive overload detection.
The device has independent, fast-reacting current
detectors with programmable trip threshold (OC
threshold) on all high-side and low-side power-stage
FETs. See the following table for OC-adjust resistor
values. The detector outputs are closely monitored by
In general, it is recommended to follow closely the
external component selection and PCB layout as
given in the application section.
13
TAS5186
www.ti.com
SLES136 – MAY 2005
Overtemperature Protection
The TAS5186 has a two-level temperature-protection
system that asserts an active-low warning signal
(OTW) when the device junction temperature exceeds 125°C (typical), and If the device junction
temperature exceeds 155°C (typical), the device is
put into thermal shutdown, resulting in all half-bridge
outputs being set in the high-impedance state (Hi-Z)
and SD being asserted low.
UNDERVOLTAGE PROTECTION (UVP) AND
POWER-ON RESET (POR)
The UVP and POR circuits of the TAS5186 fully
protect the device in any power-up/down and
brownout situation. While powering up, the POR
circuit resets the overload circuit (OLP) and ensures
that all circuits are fully operational when the
GVDD_X and VDD supply voltages reach 10 V
(typical). Although GVDD_X and VDD are independently monitored, a supply voltage drop below the
UVP threshold on any VDD or GVDD_X pin results in
all half-bridge outputs immediately being set in the
high-impedance (Hi-Z) state and SD being asserted
low. The device automatically resumes operation
when all supply voltages have increased above the
UVP threshold.
DEVICE RESET
When RESET is asserted low, the output FETs in all
half-bridges are forced into a high-impedance (Hi-Z)
state.
Asserting the RESET input low removes any fault
information to be signaled on the SD output, i.e., SD
is forced high.
A rising-edge transition on the RESET input allows
the device to resume operation after an overload
fault.
ACTIVE-BIAS CONTROL (ABC)
Audible pop noises are often associated with
single-rail, single-ended power stages at power-up or
at the start of switching. This commonly known
problem has been virtually eliminated by incorporating a proprietary active-bias control circuitry as part
of the TAS5186 feature set. By the use of only a few
passive external components (typically resistors), the
14
ABC can pre-charge the dc-blocking element in the
audio path, i.e., split-cap capacitors or series capacitor, to the desired potential before switching is started
on the PWM outputs. (For recommended configuration, see the typical application schematic included
in this data sheet).
The start-up sequence can be controlled through
sequencing the M3 and RESET pins according to
Table 2 and Table 3.
Table 2. 5.1 Mode—All Output Channels Active
M3 RESET OUT_BIAS OUT_A, OUT_D,
_B, _C _E, _F
COMMENT
0
0
Hi-Z
Hi-Z
Hi-Z
All outputs disabled, nothing is
switching.
1
0
Active
Hi-Z
Hi-Z
OUT_BIAS enabled, all other
outputs disabled
1
1
Hi-Z
Active
Active
OUT_BIAS disabled, all other
outputs
switching
Table 3. 2.1 Mode—Only Output Channels A, B,
and C Active
M3 RESET OUT_BIAS OUT_A, OUT_D,
_B, _C _E, _F
COMMENT
0
0
Hi-Z
Hi-Z
Hi-Z
All outputs disabled, nothing is
switching.
1
0
Active
Hi-Z
Hi-Z
OUT_BIAS enabled, all other
outputs disabled
0
1
Hi-Z
Active
Hi-Z
OUT_BIAS disabled, all other
outputs
switching
When the TAS5186 is used with the TAS5086 PWM
modulator, no special attention to start-up sequencing
is required, provided that the chipset is configured as
recommended.
PACKAGE OPTION ADDENDUM
www.ti.com
7-Nov-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
TAS5186DDV
ACTIVE
HTSSOP
DDV
44
35
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
TAS5186DDVG4
ACTIVE
HTSSOP
DDV
44
35
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
TAS5186DDVR
ACTIVE
HTSSOP
DDV
44
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
TAS5186DDVRG4
ACTIVE
HTSSOP
DDV
44
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
TAS5186DKD
PREVIEW
SSOP
DKD
44
TBD
Call TI
Call TI
TAS5186DKDR
PREVIEW
SSOP
DKD
44
TBD
Call TI
Call TI
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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