DRV8402 www.ti.com ........................................................................................................................................................................................... SLES222 – DECEMBER 2008 Dual Full Bridge PWM Motor Driver FEATURES 1 • • • • • • • • • • High-Efficiency Power Stage (up to 96%) with Low RDS(on) MOSFETs (80 mΩ at TJ = 25°C) Operating Supply Voltage up to 50 V (65 V Absolute Maximum) 10 A Continuous Output Current and 24 A Peak Current per Device PWM Operating Frequency up to 500 kHz Integrated Self-Protection Circuits Programmable Cycle-by-Cycle Current Limit Protection Independent Supply and Ground Pins for Each Half Bridge Intelligent Gate Drive and Cross Conduction Prevention No External Snubber or Schottky Diode is Required Thermally Enhanced DKD (36-pin PSOP3) Package The DRV8402 can operate at up to 500 kHz switching frequency while still maintains precise control and high efficiency. It also has an innovative protection system integrated on-chip, safeguarding the device against a wide range of fault conditions that could damage the system. These safeguards are short-circuit protection, overcurrent protection, undervoltage protection, and two-stage thermal protection. The DRV8402 has a current-limiting circuit that prevents device shutdown during load transients such as motor start-up. A programmable overcurrent detector allows adjustable current limit and protection level to meet different motor requirements. The DRV8402 has unique independent supply and ground pins for each half bridge, which makes it possible to provide current measurement through external shunt resistor and support multiple motors with different power supply voltage requirements. Simplified Application Diagram APPLICATIONS • • • • • • DC and Brushless DC Motors Three Phase Permanent Magnet Synchronous Motors Robotic and Haptic Control System Actuators and Pumps Precision Instruments TEC Drivers DESCRIPTION The DRV8402 is a high performance, integrated dual full bridge motor driver with an advanced protection system. Because of the low RDS(on) and intelligent gate drive design, the efficiency of this motor driver can be up to 96%, which enables the use of smaller power supplies and heatsinks, and is a good candidate for energy efficient applications. This device requires two power supplies, one at 12 V for GVDD and VDD, and one up to 50 V for PVDD. The DRV8402 is capable of driving 5 A continuous RMS current and 12 A peak current per full bridge with low idle power dissipation. It can also be used for up to 10 A continuous current and 24 A peak current in parallel full bridge operation. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2008, Texas Instruments Incorporated DRV8402 SLES222 – DECEMBER 2008 ........................................................................................................................................................................................... www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ABSOLUTE MAXIMUM RATINGS Over operating free-air temperature range unless otherwise noted (1) PARAMETER VALUE VDD to AGND –0.3 V to 13.2 V GVDD_X to AGND –0.3 V to 13.2 V PVDD_X to GND_X (2) –0.3 V to 65 V OUT_X to GND_X (2) –0.3 V to 65V BST_X to GND_X (2) –0.3 V to 75 V Transient peak output current (per pin), pulse width limited by internal over-current protection circuit. 15 A VREG to AGND –0.3 V to 4.2 V GND_X to GND –0.3 V to 0.3 V GND_X to AGND –0.3 V to 0.3 V GND to AGND –0.3 V to 0.3 V PWM_X, OC_ADJ, M1, M2, M3 to AGND –0.3 V to 4.2 V RESET_X, FAULT, OTW to AGND –0.3 V to 7 V Maximum continuous sink current (FAULT, OTW) 9 mA Maximum operating junction temperature range, TJ -40°C to 150°C Storage temperature, Tstg –55°C to 150°C (1) (2) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. These voltages represent the dc voltage + peak ac waveform measured at the terminal of the device in all conditions. RECOMMENDED OPERATING CONDITIONS PARAMETER DESCRIPTION MIN NOM MAX UNIT PVDD_X Half bridge X (A, B, C, or D) DC supply voltage 0 50 52.5 V GVDD_X Supply for logic regulators and gate-drive circuitry 11.4 12.3 13.2 V VDD Digital regulator input 11.4 12.3 13.2 V IO_pulse Pulsed peak current per output pin 12 A IO Continuous current per output pin 5 FSw PWM switching frequency LO Minimum output inductance under short-circuit condition and parallel mode ROCP_CBC OC programming resistor range in cycle by cycle current limit modes, Resistor tolerance = 5% 27 39 kΩ ROCP_OCL OC programming resistor range in OC latching shutdown modes, Resistor tolerance = 5% 22 39 kΩ TA Operating ambient temperature -40 85 °C 500 4 A kHz µH Package Heat Dissipation Ratings PARAMETER VALUE RθJC, junction-to-case (heat slug) thermal resistance (all bridges running) RθJA, junction-to-ambient thermal resistance 1°C/W This device is not intended to be used without a heatsink. Therefore, RθJA is not specified. See the Thermal Information section. 80 mm2 Exposed heat slug area 2 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): DRV8402 DRV8402 www.ti.com ........................................................................................................................................................................................... SLES222 – DECEMBER 2008 DEVICE INFORMATION Pin Assignment The DRV8402 is available in a thermally enhanced package: • 36-pin PSOP3 package (DKD) This package contains a heat slug that is located on the top side of the device for convenient thermal coupling to the heatsink. DKD PACKAGE (TOP VIEW) GVDD_B OTW FAULT PWM_A RESET_AB PWM_B OC_ADJ GND AGND VREG M3 M2 M1 PWM_C RESET_CD PWM_D VDD GVDD_C 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 GVDD_A BST_A PVDD_A OUT_A GND_A GND_B OUT_B PVDD_B BST_B BST_C PVDD_C OUT_C GND_C GND_D OUT_D PVDD_D BST_D GVDD_D MODE Selection Pins MODE PINS M3 M2 M1 OUTPUT CONFIGURATION 0 0 0 2 FB Dual full bridge with cycle-by-cycle current limit 0 0 1 2 FB Dual full bridge with OC latching shutdown (no cycle-by-cycle current limit) 0 1 0 1 PFB Parallel full bridge with cycle-by-cycle current limit 0 1 1 1 PFB Parallel full bridge with OC latching shutdown 4 HB Half bridge with cycle-by-cycle current limit. Protection works similarly to full bridge mode. Only difference in half bridge mode is that OUT_X is Hi-Z instead of a pulldown through internal pulldown resistor when RESET pin is low. 4 HB Half bridge with OC latching shutdown. Protection works similarly to full bridge mode. Only difference in half bridge mode is that OUT_X is Hi-Z instead of a pulldown through internal pulldown resistor when RESET pin is low. 1 0 0 1 0 1 1 1 0 1 1 1 DESCRIPTION Reserved Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): DRV8402 3 DRV8402 SLES222 – DECEMBER 2008 ........................................................................................................................................................................................... www.ti.com Pin Functions PIN NAME FUNCTION (1) DESCRIPTION AGND 9 P Analog ground BST_A 35 P High side bootstrap supply (BST), external capacitor to OUT_A required BST_B 28 P High side bootstrap supply (BST), external capacitor to OUT_B required BST_C 27 P High side bootstrap supply (BST), external capacitor to OUT_C required BST_D 20 P High side bootstrap supply (BST), external capacitor to OUT_D required GND 8 P Ground GND_A 32 P Power ground for half-bridge A GND_B 31 P Power ground for half-bridge B GND_C 24 P Power ground for half-bridge C GND_D 23 P Power ground for half-bridge D GVDD_A 36 P Gate-drive voltage supply requires 0.1-µF capacitor to AGND GVDD_B 1 P Gate-drive voltage supply requires 0.1-µF capacitor to AGND GVDD_C 18 P Gate-drive voltage supply requires 0.1-µF capacitor to AGND GVDD_D 19 P Gate-drive voltage supply requires 0.1-µF capacitor to AGND M1 13 I Mode selection pin M2 12 I Mode selection pin M3 11 I Mode selection pin OC_ADJ 7 O Analog overcurrent programming pin requires resistor to ground OTW 2 O Overtemperature warning signal, open-drain, active-low OUT_A 33 O Output, half-bridge A OUT_B 30 O Output, half-bridge B OUT_C 25 O Output, half-bridge C OUT_D 22 O Output, half-bridge D PVDD_A 34 P Power supply input for half-bridge A requires close decoupling of 0.01-µF capacitor in parallel with a 1.0-µF capacitor to GND_A. PVDD_B 29 P Power supply input for half-bridge B requires close decoupling of 0.01-µF capacitor in parallel with a 1.0-µF capacitor to GND_B. PVDD_C 26 P Power supply input for half-bridge C requires close decoupling of 0.01-µF capacitor in parallel with a 1.0-µF capacitor to GND_C. PVDD_D 21 P Power supply input for half-bridge D requires close decoupling of 0.01-µF capacitor in parallel with a 1.0-µF capacitor to GND_D. PWM_A 4 I Input signal for half-bridge A PWM_B 6 I Input signal for half-bridge B PWM_C 14 I Input signal for half-bridge C PWM_D 16 I Input signal for half-bridge D RESET_AB 5 I Reset signal for half-bridge A and half-bridge B, active-low RESET_CD 15 I Reset signal for half-bridge C and half-bridge D, active-low FAULT 3 O Fault signal, open-drain, active-low VDD 17 P Power supply for digital voltage regulator requires a 47-µF capacitor in parallel with a 0.1-µF capacitor to GND for decoupling. VREG 10 P Digital regulator supply filter pin requires 0.1-µF capacitor to AGND. (1) 4 DKD NO. I = input, O = output, P = power Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): DRV8402 DRV8402 www.ti.com ........................................................................................................................................................................................... SLES222 – DECEMBER 2008 SYSTEM BLOCK DIAGRAM VDD 4 Undervoltage Protection OTW Internal Pullup Resistors to VREG FAULT M1 Protection and I/O Logic M2 M3 4 VREG VREG Power On Reset AGND Temp. Sense GND RESET_AB Overload Protection RESET_CD Isense OC_ADJ GVDD_D BST_D PVDD_D PWM_D PWM Rcv. Ctrl. Timing Gate Drive OUT_D FB/PFB−Configuration Pulldown Resistor GND_D GVDD_C BST_C PVDD_C PWM_C PWM Rcv. Ctrl. Timing Gate Drive OUT_C FB/PFB−Configuration Pulldown Resistor GND_C GVDD_B BST_B PVDD_B PWM_B PWM Rcv. Ctrl. Timing Gate Drive OUT_B FB/PFB−Configuration Pulldown Resistor GND_B GVDD_A BST_A PVDD_A PWM_A PWM Rcv. Ctrl. Timing Gate Drive OUT_A FB/PFB−Configuration Pulldown Resistor GND_A Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): DRV8402 5 DRV8402 SLES222 – DECEMBER 2008 ........................................................................................................................................................................................... www.ti.com ELECTRICAL CHARACTERISTICS Ta = 25 °C, PVDD = 50 V, GVDD = VDD = 12 V, FSw = 400 kHz, unless otherwise noted. All performance is in accordance with recommended operating conditions unless otherwise specified. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Internal Voltage Regulator and Current Consumption VREG Voltage regulator, only used as a reference node VDD = 12 V IVDD VDD supply current Idle, reset mode IGVDD_X Gate supply current per half-bridge IPVDD_X Half-bridge X (A, B, C, or D) idle current MOSFET drain-to-source resistance, low side (LS) 2.95 3.3 3.65 V 9 12 mA Reset mode 1.7 2 mA Reset mode 0.5 1 mA TJ = 25°C, includes metallization resistance, GVDD = 12 V 90 mΩ MOSFET drain-to-source resistance, high TJ = 25°C, includes metallization resistance, side (HS) GVDD = 12 V 90 mΩ Output Stage RDS(on) VF Diode forward voltage drop TJ = 25°C - 125°C, IO = 5 A 1 V tR Output rise time Resistive load, IO = 5 A 9 nS tF Output fall time Resistive load, IO = 5 A 9 nS tPD_ON Propagation delay when FET is on Resistive load, IO = 5 A 42 nS tPD_OFF Propagation delay when FET is off Resistive load, IO = 5 A 40 nS tDT Dead time between HS and LS FETs Resistive load, IO = 5 A 5 nS I/O Protection Vuvp,G Gate supply voltage GVDD_X undervoltage protection 8.5 V Vuvp,hyst (1) Hysteresis for gate supply undervoltage event 0.8 V OTW (1) Overtemperature warning OTWhyst (1) Hysteresis temperature to reset OTW event OTSD (1) Overtemperature shut down OTE-OTWdifferential (1) OTE-OTW overtemperature detect temperature difference OTSDHYST (1) Hysteresis temperature for FAULT to be released following an OTSD event. IOC Overcurrent limit protection IOCT RPD 115 125 135 °C 25 °C 150 °C 25 °C 25 °C Resistor—programmable, nominal, ROCP = 27 kΩ 10.6 A Overcurrent response time Time from application of short condition to Hi-Z of affected FET(s) 250 ns Internal pulldown resistor at the output of each half-bridge Connected when RESET_AB or RESET_CD is active to provide bootstrap capacitor charge. Not used in SE mode 1 kΩ Static Digital Specifications VIH High-level input voltage VIL Low-level input voltage llkg Input leakage current PWM_A, PWM_B, PWM_C, PWM_D, M1, M2, M3, RESET_AB, RESET_CD 2 V -100 0.8 V 100 µA kΩ OTW / FAULT RINT_PU Internal pullup resistance, OTW to VREG, FAULT to VREG VOH High-level output voltage VOL Low-level output voltage (1) 6 Internal pullup resistor only External pullup of 4.7 kΩ to 5 V IO = 4 mA 20 26 35 2.95 3.3 3.65 4.5 5 0.2 0.4 V V Specified by design Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): DRV8402 DRV8402 www.ti.com ........................................................................................................................................................................................... SLES222 – DECEMBER 2008 TYPICAL CHARACTERISTICS EFFICIENCY vs SWITCHING FREQUENCY NORMALIZED RDS(on) vs GATE DRIVE, GVDD 1.10 100 90 1.08 RDS(on) / (RDS(on) at 12 V) 80 Efficiency = % 70 60 50 40 30 Full Bridge Load = 5 A PVDD = 50 V TC = 75°C 20 10 1.04 1.02 1.00 TJ = 25°C 0.98 0 0.96 0 50 100 150 200 250 300 350 400 450 500 f - Switching Frequency - kHz 8 8.5 9 9.5 10 10.5 11 GVDD - Gate Drive - V 11.5 Figure 1. Figure 2. NORMALIZED RDS(on) vs JUNCTION TEMPERATURE DRAIN TO SOURCE DIODE FORWARD ON CHARACTERISTICS 1.6 12 6 5 1.4 TJ = 25°C 4 1.2 Current - A RDS(on) / (RDS(on) at 25oC) 1.06 1.0 3 2 0.8 1 GVDD = 12V 0.6 0.4 -40 0 -1 -20 0 20 40 60 80 100 120 o TJ - Junction Temperature - C 140 0 Figure 3. 0.2 0.4 0.6 Voltage - V 0.8 1 1.2 Figure 4. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): DRV8402 7 DRV8402 SLES222 – DECEMBER 2008 ........................................................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS (continued) OUTPUT DUTY CYCLE vs INPUT DUTY CYCLE 100 90 FS = 500 kHz TC = 25°C Output Duty Cycle - % 80 70 60 50 40 30 20 10 0 0 10 20 30 40 50 60 70 Input Duty Cycle - % 80 90 100 Figure 5. 8 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): DRV8402 DRV8402 www.ti.com ........................................................................................................................................................................................... SLES222 – DECEMBER 2008 THEORY OF OPERATION POWER SUPPLIES To help with system design, the DRV8402 needs only a 12 V supply in addition to power-stage supply. An internal voltage regulator provides suitable voltage levels for the digital and low-voltage analog circuitry. Additionally, all circuitry requiring a floating voltage supply, for example, the high-side gate drive, is accommodated by built-in bootstrap circuitry requiring only a few external capacitors. To provide electrical characteristics, the PWM signal path including gate drive and output stage is designed as identical, independent half-bridges. For this reason, each half-bridge has separate gate drive supply (GVDD_X), bootstrap pins (BST_X), and power-stage supply pins (PVDD_X). Furthermore, an additional pin (VDD) is provided as supply for all common circuits. Although supplied from the same 12-V source, it is recommended that a 1 – 10 Ω resistor is used to separate the GVDD_X pins from VDD on the printed-circuit board (PCB). Special attention should be paid to placing all decoupling capacitors as close to their associated pins as possible. In general, inductance between the power supply pins and decoupling capacitors must be avoided. For a properly functioning bootstrap circuit, a small ceramic capacitor must be connected from each bootstrap pin (BST_X) to the power-stage output pin (OUT_X). When the power-stage output is low, the bootstrap capacitor is charged through an internal diode connected between the gate-drive power-supply pin (GVDD_X) and the bootstrap pin. When the power-stage output is high, the bootstrap capacitor potential is shifted above the output potential and thus provides a suitable voltage supply for the high-side gate driver. In an application with PWM switching frequencies in the range from 25 kHz to 500 kHz, the use of 47 nF ceramic capacitors, size 0603 or 0805, is recommended for the bootstrap supply. These 47 nF capacitors ensure sufficient energy storage, even during minimal PWM duty cycles, to keep the high-side power stage FET fully turned on during the remaining part of the PWM cycle. In an application running at a switching frequency lower than 25 kHz, the bootstrap capacitor might need to be increased in value. compliance, and system reliability, it is important that each PVDD_X pin is decoupled with a ceramic capacitor placed as close as possible to each supply pin. It is recommended to follow the PCB layout of the DRV8402 in EVM board. The 12 V supply should be from a low-noise, low-output-impedance voltage regulator. Likewise, the 50 V power-stage supply is assumed to have low output impedance and low noise. The power-supply sequence is not critical as facilitated by the internal power-on-reset circuit. Moreover, the DRV8402 is fully protected against erroneous power-stage turn-on due to parasitic gate charging. Thus, voltage-supply ramp rates (dv/dt) are non-critical within the specified range (see the Recommended Operating Conditions section of this data sheet). SYSTEM POWER-UP/POWER-DOWN SEQUENCE Powering Up The DRV8402 does not require a power-up sequence. The outputs of the H-bridges remain in a highimpedance state until the gate-drive supply voltage (GVDD_X) and VDD voltage are above the undervoltage protection (UVP) voltage threshold (see the Electrical Characteristics section of this data sheet). Although not specifically required, holding RESET_AB and RESET_CD in a low state while powering up the device is recommended. This allows an internal circuit to charge the external bootstrap capacitors by enabling a weak pulldown of the half-bridge output (except in half-bridge modes). Powering Down The DRV8402 does not require a power-down sequence. The device remains fully operational as long as the gate-drive supply (GVDD_X) voltage and VDD voltage are above the UVP voltage threshold (see the Electrical Characteristics section of this data sheet). Although not specifically required, it is a good practice to hold RESET_AB and RESET_CD low during power down to prevent any unknown state during this transition. Special attention should be paid to the power-stage power supply; this includes component selection, PCB placement, and routing. As indicated, each half-bridge has independent power-stage supply pins (PVDD_X). For optimal electrical performance, EMI Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): DRV8402 9 DRV8402 SLES222 – DECEMBER 2008 ........................................................................................................................................................................................... www.ti.com ERROR REPORTING Bootstrap Capacitor Under Voltage Protection The FAULT and OTW pins are both active-low, open-drain outputs. Their function is for protection-mode signaling to a PWM controller or other system-control device. When the device runs at a low switching frequency (e.g. less than 20 kHz with 47 nF bootstrap capacitor), the bootstrap capacitor voltage might not be able to maintain a proper voltage level for the high-side gate driver. A bootstrap capacitor undervoltage protection circuit (BST_UVP) will start under this circumstance to prevent the potential failure of the high-side MOSFET. When the voltage on the bootstrap capacitors is less than required for safe operation, the DRV8402 will initiate bootstrap capacitor recharge sequences (turn off high side FET for a short period) until the bootstrap capacitors are properly charged for safe operation. This function may also be activated when PWM duty cycle is too high (e.g. higher than 99.5%). Note that bootstrap capacitor might not be able to be charged up if no load is presented at output. Any fault resulting in device shutdown is signaled by the FAULT pin going low. Likewise, OTW goes low when the device junction temperature exceeds 125°C (see Table 1). Table 1. FAULT OTW 0 0 Overtemperature warning and (overtemperature shut down or overcurrent shut down or undervoltage protection) occurred DESCRIPTION 0 1 Overcurrent shut-down or undervoltage protection occurred 1 0 Overtemperature warning 1 1 Device under normal operation Note that asserting either RESET_AB or RESET_CD low forces the FAULT signal high, independent of faults being present. For proper error reporting, set both RESET_AB and RESET_CD high during normal operation. TI recommends monitoring the OTW signal using the system microcontroller and responding to an OTW signal by reducing the load current to prevent further heating of the device resulting in device overtemperature shutdown (OTSD). To reduce external component count, an internal pullup resistor to 3.3 V is provided on both FAULT and OTW outputs. Level compliance for 5-V logic can be obtained by adding external pull-up resistors to 5 V (see the Electrical Characteristics section of this data sheet for further specifications). DEVICE PROTECTION SYSTEM The DRV8402 contains advanced protection circuitry carefully designed to facilitate system integration and ease of use, as well as to safeguard the device from permanent failure due to a wide range of fault conditions such as short circuits, overcurrent, overtemperature, and undervoltage. The DRV8402 responds to a fault by immediately setting the power stage in a high-impedance (Hi-Z) state and asserting the FAULT pin low. In situations other than overcurrent or overtemperature, the device automatically recovers when the fault condition has been removed or the gate supply voltage has increased. For highest possible reliability, recovering from an overcurrent shut down (OCSD) or OTSD fault requires external reset of the device (see the Device Reset section of this data sheet) no sooner than 1 second after the shutdown. 10 Because the extra pulse width to charge bootstrap capacitor is so short, that the output current disruption due to the extra charge is negligible most of the time when output inductor is present. Overcurrent (OC) Protection The device has independent, fast-reacting current detectors with programmable trip threshold (OC threshold) on all high-side and low-side power-stage FETs. There are two settings for OC protection through Mode selection pins: cycle-by-cycle (CBC) current limiting mode and OC latching (OCL) shut down mode. In CBC current limiting mode, the detector outputs are monitored by two protection systems. The first protection system controls the power stage in order to prevent the output current from further increasing, i.e., it performs a CBC current-limiting function rather than prematurely shutting down the device. This feature could effectively limit the inrush current during motor start-up or transient without damaging the device. During short to power and short to ground condition, the current limit circuitry might not be able to control the current in a proper level, a second protection system triggers a latching shutdown, resulting in the power stage being set in the high-impedance (Hi-Z) state. Current limiting and overcurrent protection are independent for half-bridges A, B, C, and, D, respectively. In OCL shut down mode, the cycle-by-cycle current limit and error recovery circuitry is disabled and an overcurrent condition will cause the device to shutdown immediately. After shutdown, RESET_AB and/or RESET_CD must be asserted to restore normal operation after the overcurrent condition is removed. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): DRV8402 DRV8402 www.ti.com ........................................................................................................................................................................................... SLES222 – DECEMBER 2008 For added flexibility, the OC threshold is programmable within a limited range using a single external resistor connected between the OC_ADJ pin and AGND pin. See Table 2 for information on the correlation between programming-resistor value and the OC threshold. It should be noted that a properly functioning overcurrent detector assumes the presence of a proper inductor at the power-stage output (minimum 2 µH). Short-circuit protection is not provided directly at the output pins of the power stage, but only after the inductor. If a further smaller inductor is preferred for any reason, using OCL mode setting is recommended. Table 2. Undervoltage Protection (UVP) and Power-On Reset (POR) The UVP and POR circuits of the DRV8402 fully protect the device in any power-up/down and brownout situation. While powering up, the POR circuit resets the overcurrent circuit and ensures that all circuits are fully operational when the GVDD_X and VDD supply voltages reach 9.8 V (typical). Although GVDD_X and VDD are independently monitored, a supply voltage drop below the UVP threshold on any VDD or GVDD_X pin results in all half-bridge outputs immediately being set in the high-impedance (Hi-Z) state and FAULT being asserted low. The device automatically resumes operation when all supply voltage on the bootstrap capacitors have increased above the UVP threshold. OC-Adjust Resistor Values (kΩ) Max. Current Before OC Occurs (A) 22(1) 12.2 DEVICE RESET 24(1) 11.5 27 10.6 30 9.9 33 9.3 36 8.7 39 8.2 Two reset pins are provided for independent control of half-bridges A/B and C/D. When RESET_AB is asserted low, all four power-stage FETs in half-bridges A and B are forced into a high-impedance (Hi-Z) state. Likewise, asserting RESET_CD low forces all four power-stage FETs in half-bridges C and D into a high-impedance state. (1) Recommended to use in OCL Mode Only Overtemperature Protection The DRV8402 has a two-level temperature-protection system that asserts an active-low warning signal (OTW) when the device junction temperature exceeds 125°C (nominal) and, if the device junction temperature exceeds 150°C (nominal), the device is put into thermal shutdown, resulting in all half-bridge outputs being set in the high-impedance (Hi-Z) state and FAULT being asserted low. OTSD is latched in this case and RESET_AB and RESET_CD must be asserted low. In full bridge and parallel full bridge configurations, to accommodate bootstrap charging prior to switching start, asserting the reset inputs low enables weak pulldown of the half-bridge outputs. In half bridge configuration, the weak pulldowns are not enabled, and it is, therefore, recommended to precharge bootstrap capacitor by providing a low pulse on the PWM inputs first when reset is asserted high. Asserting either reset input low removes any fault information to be signaled on the FAULT output, i.e., FAULT is forced high. A rising-edge transition on either reset input allows the device to resume operation after an overcurrent fault. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): DRV8402 11 DRV8402 SLES222 – DECEMBER 2008 ........................................................................................................................................................................................... www.ti.com DIFFERENT MODE OPERATIONS The DRV8402 supports three operations: 1. Full bridge (FB) mode 2. Parallel full bridge (PFB) mode 3. Half bridge (HB) mode different mode In full bridge and half bridge modes, PWM_A controls half bridge A, PWM_B controls both half bridge B, etc. Figure 6 shows an application example for full bridge mode operation. In parallel full bridge mode, PWM_A controls both half bridge A and B, and PWM_B controls both half bridge C and D, while PWM_C and PWM_D pins are not used (recommended to connect to ground). Bridges A and B are synchronized internally (even during CBC), and so as bridges C and D. OUT_A and OUT_B should be connected together and OUT_C and OUT_D should be connected together after a small output inductor. Figure 7 shows an example of parallel full bridge mode connection. Figure 6. Application Diagram Example for Full Bridge Mode Operation Mode pins are configured as CBC current limit operation in Figure 6 and Figure 7. The DRV8402 can be also used in three phase permanent magnet synchronous motor (PMSM) applications. Because each half bridge has independent supply and ground pins, a shunt sensing resistor can be inserted between PVDD to PVDD_X or GND to GND_X. A high side shunt resistor between PVDD and PVDD_X is recommended for differential current sensing because a high bias voltage on the low side sensing could affect device operation. OCL mode is recommended for a three phase application. Figure 8 shows a three-phase application example. A decoupling capacitor close to each supply pin is recommended for each application (not shown in diagrams). PWM_A controls OUT_A and OUT_B; PWM_B controls OUT_C and OUT_D. Figure 7. Application Diagram Example for Parallel Full Bridge Mode Operation 12 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): DRV8402 DRV8402 www.ti.com ........................................................................................................................................................................................... SLES222 – DECEMBER 2008 RθJA is a system thermal resistance from junction to ambient air. As such, it is a system parameter with the following components: • RθJC (the thermal resistance from junction to case, or in this example the heat slug) • Thermal grease thermal resistance • Heat sink thermal resistance The thermal grease thermal resistance can be calculated from the exposed heat slug area and the thermal grease manufacturer's area thermal resistance (expressed in °C-in2/W or °C-mm2/W). The approximate exposed heat slug size is as follows: • DRV8402, 36-pin PSOP3 …… 0.124 in2 (80 mm2) Figure 8. Application Diagram Example for Three Phase PMSM Operation The thermal resistance of thermal pads is considered higher than a thin thermal grease layer. Thermal tape has an even higher thermal resistance and should not be used at all. Heat sink thermal resistance is predicted by the heat sink vendor, modeled using a continuous flow dynamics (CFD) model, or measured. Thus the system RθJA = RθJC + thermal grease resistance + heat sink resistance. THERMAL INFORMATION The thermally enhanced package provided with the DRV8402 is designed to interface directly to heat sink using a thermal interface compound, (e.g., Arctic Silver, TIMTronics 413, Ceramic thermal compound, etc.). The heat sink then absorbs heat from the ICs and couples it to the local air. See the TI application report, IC Package Thermal Metrics (SPRA953A), for more thermal information. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): DRV8402 13 PACKAGE OPTION ADDENDUM www.ti.com 2-Jan-2009 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty DRV8402DKD ACTIVE SSOP DKD 36 29 Green (RoHS & no Sb/Br) CU NIPDAU Level-4-260C-72 HR DRV8402DKDR ACTIVE SSOP DKD 36 500 Green (RoHS & no Sb/Br) CU NIPDAU Level-4-260C-72 HR Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 31-Dec-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device DRV8402DKDR Package Package Pins Type Drawing SSOP DKD 36 SPQ 500 Reel Reel Diameter Width (mm) W1 (mm) 330.0 24.4 Pack Materials-Page 1 A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 14.7 16.4 4.0 20.0 24.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 31-Dec-2008 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DRV8402DKDR SSOP DKD 36 500 346.0 346.0 41.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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