TM TAS5261 www.ti.com SLES188 – AUGUST 2006 315-W Mono BTL Digital Amplifier Power Stage FEATURES • • • • • • • • Total Output Power – 125 W Into 8 Ω at <0.09% THD+N – 220 W Into 6 Ω at 10% THD+N – 315 W Into 4 Ω at 10% THD+N 110-dB SNR (A-Weighted with TAS5518 modulator) Supports Pulse-Width Modulation (PWM) Frame Rates of 192 kHz to 384 kHz Resistor-Programmable Current Limit Integrated Self-Protection Circuit Including: – Under Voltage Protection – Over Temperature Warning and Error – Over Load Protection – Short Circuit (OC) Protection – PWM Activity Dectector Power-On Reset (POR) to Eliminate System Power-Supply Sequencing Thermally-Enhanced Package DKD (36-pin PSOP3) EMI Compliant When Used With Recommended System Design Error Reporting 3.3-V and 5-V Compliant APPLICATIONS • • • • AV Receivers DVD Receivers Mini/Micro Component Systems Home Theater Systems The TAS5261 has complete protection circuitry integrated on chip, safeguarding the device and speakers against fault conditions that could damage the system. These protection features are short-circuit protection, overcurrent protection, undervoltage protection, and a loss of pulse-width modulation (PWM) input signal (PWM Activity Detector). A power-on reset (POR) circuit is used to eliminate power-supply sequencing that is normally required for most H-bridge designs. OUTPUT POWER vs PVDD_x SUPPLY VOLTAGE 330 TC = 75°C THD+N at 10% 300 270 PO − Output Power − W • 240 210 6Ω 180 150 4Ω 120 90 60 8Ω 30 0 0 5 10 15 20 25 30 35 40 45 50 PVDD Supply Voltage − V G001 DESCRIPTION The TAS5261 is a high-performance, integrated mono digital amplifier power stage designed to drive 4-Ω to 8-Ω speakers with low harmonic distortion. This system requires only a simple, passive demodulation filter to deliver high-quality, high-efficiency audio amplification. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2006, Texas Instruments Incorporated TAS5261 www.ti.com SLES188 – AUGUST 2006 DEVICE INFORMATION The TAS5261 is available in a thermally-enhanced 36-pin PSOP3 PowerPAD™ package. The heat slug is located on the top side of the device for convenient thermal coupling to a heat sink. DKD PACKAGE (TOP VIEW) BST_A GVDD_A OTW SD RESET PWM_A OC_ADJ GND AGND VREG M3 M2 M1 PWM_B VDD GND GVDD_B BST_B 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 PVDD_A PVDD_A PVDD_A PGND PGND PGND OUT_A OUT_A OUT_A OUT_B OUT_B OUT_B PGND PGND PGND PVDD_B PVDD_B PVDD_B P0018-02 2 Submit Documentation Feedback TAS5261 www.ti.com SLES188 – AUGUST 2006 DISSIPATION RATINGS PARAMETER CONDITION TYPICAL (DKD) RθJC BTL channel (four transistors) 0.6°C/W RθJC One transistor 2.38°C/W 80 mm2 Pad area Protection Mode Protection modes are selected by shorting M1, M2, and M3 to VREG or GND. Table 1. Protection Modes MODE PINS PROTECTION MODE M3 (1) M2 M1 0 0 0 0 0 1 Reserved 0 1 0 OC latching mode 0 1 1 Reserved (1) Full protection (default) M3 is reserved and always should be connected to board GND. Submit Documentation Feedback 3 TAS5261 www.ti.com SLES188 – AUGUST 2006 TERMINAL FUNCTIONS TERMINAL DESCRIPTION PIN NO. AGND 9 I Analog ground BST_A 1 P Bootstrap, A side BST_B 18 I Bootstrap, B side GND 8, 16 I Power ground GVDD_A 2 P Gate-drive voltage supply, A side GVDD_B 17 I Gate-drive voltage supply, B side M1 13 I Mode-selection 1 (LSB) M2 12 I Mode-selection 2 (MSB) M3 11 I Reserved OC_ADJ 7 I Overcurrent threshold programming OTW 3 O Overtemperature warning. Open drain, active low. OUT_A 28, 29, 30 O Output, half-bridge A OUT_B 25, 26, 27 O Output, half-bridge B PGND 22, 23, 24, 31, 32, 33 P Power ground 6 I PWM for half-bridge A PWM_A PWM_B 14 I PWM Input for half-bridge B PVDD_A 34, 35, 36 P PVDD supply for half-bridge A PVDD_B 19, 20, 21 P PVDD supply for half-bridge B 5 I Reset. Active low. SD 4 O Shutdown. Open drain, active low. VDD 15 I Input power supply VREG 10 O Internal voltage regulator RESET 4 I/O NAME Submit Documentation Feedback TAS5261 www.ti.com SLES188 – AUGUST 2006 GVDD (12 V) and VDD (12 V) GND PWM_B RESET M2 Shutdown M1 Hardwire Mode Control H-Bridge OC_ADJ Output VDD VREG GND GVDD_A, B PVDD_A, B GND_A, B Mono BTL H-Bridge Overtemp_warning Right Output PWM_A R2 Left Output M3 OUT_A OUT_B 2nd-Order L-C Output Filter for Each H-Bridge 4–8 W (3 W Min) BST_A BST_B Bootstrap Capacitors RESET_H-Bridge RESET SD OTW SD PWM_B 6 50 V PVDD (0–50 V) System Power Supplies GND 12 V 6 PVDD Power-Supply Decoupling VDD VREG GND M3 OUT_A OUT_B 2nd-Order L-C Output Filter for Each H-Bridge 4–8 W (3 W Min) BST_A GND M2 GND_A, B PVDD_A, B M1 Hardwire Mode Control GVDD_A, B Mono BTL H-Bridge H-Bridge Output L2 PWM_A OC_ADJ L1 Shutdown System Microcontroller Overtemp_warning OTW RESET TAS55XX R1 2 6 GND 6 Hardwire Overcurrent Limit GVDD, VDD, and VREG Power-Supply Decoupling PVDD Power-Supply Decoupling PVDD (0–50 V) BST_B Bootstrap Capacitors 2 GVDD, VDD, and VREG Power-Supply Decoupling Hardwire Overcurrent Limit GND GVDD (12 V) and VDD (12 V) AC B0101-01 Figure 1. Typical System Block Diagram Submit Documentation Feedback 5 TAS5261 www.ti.com SLES188 – AUGUST 2006 OTW M1 M2 M3 PROTECTION & I/O LOGIC SD VDD POWER-UP RESET UVP VREG VREG AGND TEMP SENSE GVDD_A GVDD_B GND OVER-LOAD PROT . CURRENT SENSE CB3C OC_ADJ RESET GVDD _B PWM ACTIVITY DETECTOR BST_B PVDD_B (x3) PWM_B PWM RECEIVER CONTROL TIMING CONTROL GATE-DRIVE OUT_B (x3) PGND (x3) GVDD _A BST_A PVDD_A (x3) PWM_A PWM RECEIVER CONTROL TIMING CONTROL GATE-DRIVE OUT_A (x3) PGND (x3) Figure 2. Functional Block Diagram 6 Submit Documentation Feedback TAS5261 www.ti.com SLES188 – AUGUST 2006 ORDERING INFORMATION TA PACKAGE DESCRIPTION 0°C to 70°C TAS5261DKD 36-pin PSOP3 Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VDD to AGND –0.3 13.2 V GVDD_x to AGND –0.3 13.2 V PVDD_x to PGND_x (2) –0.3 71 V OUT_x to PGND_x (2) –0.3 71 V BST_x to PGND_x (2) –0.3 79.7 V GVDD_x (2) BST_x to –0.3 66.5 V VREG to AGND –0.3 4.2 V PGND_x to GND –0.3 0.3 V PGND_x to AGND –0.3 0.3 V GND to AGND –0.3 0.3 V PWM_x, OC_ADJ, M1, M2, M3 to AGND –0.3 4.2 V RESET, SD, OTW to AGND –0.3 7 V 9 mA 0 150 °C –65 150 °C 260 °C Maximum continuous sink current (SD, OTW) Maximum operating junction temperature range, TJ Storage temperature range, Tstg Lead temperature 1,6 mm (1/16 in) from case for 10 s Minimum pulse duration, low – minimum pulse width must be ensured by the PWM processor (1) (2) 50 ns Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are only stress ratings, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. These voltages represent the dc voltage + peak ac waveform measured at the terminal of the device in all conditions. Submit Documentation Feedback 7 TAS5261 www.ti.com SLES188 – AUGUST 2006 RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT 0 50 52.5 V Gate-drive power supply 10.8 (1) 12 13.2 V VDD Digital regulator supply voltage 10.8 (1) 12 13.2 RL Resistive load impedance, bridge-tied load (BTL) RL Resistive load impedance, BTL, ROC = 22kΩ, PVDD = 50V, (no current limiting) 3 LDEM Minimum output filter inductance under both operating and short-circuit conditions, with appropriate OC_ADJ resistor value 5 fS PWM frame rate t(low) Minimum low-state pulse duration per PWM frame, noise shaper enabled CBS Bootstrap capacitor, selected value supports fs = 192 kHz to 384 kHz 33 nF RBS Bootstrap series resistor - 1/4 W 1.5 Ω 4.7 Ω 470 pF 15 nS PVDD_x Half-bridge supply voltage GVDD_x Ω Bootstrap snubber - 1/4 W DCLMP Ultra-Fast Recovery Clamping Diode, Average forward current = 1A, Maximum repetitive reverse voltage = 200V (ES1D, mfg:Fairchild) DTVS Transient Voltage Suppressor, 600W @ 1mS (P6SMB62AT3, mfg: ON Semiconductor) CPVDD PVDD Close Decoupling Capacitor, two capacitors RAGND AGND resistor - 1/4 W R Optional external pullup resistor to +3.3V or +5 V for SD and OTW TJ Junction temperature µH 10 192 RCBS (1) V Ω 4-16 384 50 3.3 kHz ns 62 V 100 nF 3.3 Ω 4.7 kΩ 0 125 °C GVDD operation below 10.8 V significantly reduces efficiency of the output MOSFET stage and requires a larger heatsink. For the purpose of noise margin, the UVP level is set lower to provide an increased noise margin, however, TI recommends a nominal dc voltage of 12 V for GVDD. AUDIO CHARACTERISTICS Audio frequency = 1 kHz, PVDD_x = 50 V, GVDD_x = 12 V, VDD = 12 V, RL = 8 Ω , fs = 384 kHz, OC_ADJ = 22 kΩ, TC= 75°C, output filter is LDEM = 10 µH, CL = 1 µF (unless otherwise noted). Audio performance is recorded as a chipset, TAS5518 as front end with an effective modulation index of 96.1% and TAS5261 as the power stage. PCB and system configuration are in accordance with recommended design guidelines. PARAMETER PO MIN TYP 125 RL = 6 Ω, f = 1 kHz 165 RL = 4 Ω, f = 1 kHz 235 RL = 8 Ω, f = 1 kHz, THD = 10% 165 RL = 6 Ω, f = 1 kHz, THD = 10% 220 RL = 4 Ω, f = 1 kHz, THD = 10% 315 MAX UNIT W PO Maximum power output RL = 3 Ω, f = 1 kHz, CBC allowed 400 THD+N Total harmonic distortion + noise, AES 17 filter 1 W to 125 W, RL=8 Ω, AES17 filter, Unclipped 0.09 % SNR Signal-to-noise ratio (1) Ratio of 1-FFS to 0-FFS input, A-weighted filter 110 dB DNR Dynamic range –60-dBFS input, A-weighted filter 110 dB VOO Output offset voltage PWM switching frequency 384 kHz, Measured on speaker terminals Pidle Power dissipation due to idle losses (IPVDD_X) PO = 0 W, Output switching (2) (1) (2) 8 Unclipped power output TEST CONDITIONS RL = 8 Ω, f = 1 kHz SNR is calculated relative to the 0 dBFS input level. Actual system idle losses are also affected by core losses of output inductors. Submit Documentation Feedback –15 W 15 2 mV W TAS5261 www.ti.com SLES188 – AUGUST 2006 ELECTRICAL CHARACTERISTICS Audio frequency = 1 kHz, PVDD_x = 50 V, GVDDx = 12 V, VDD = 12 V, RL = 8 Ω , fs = 384 kHz, OC_ADJ = 22 kΩ, TC = 75°C, output filter is LDEM = 10 µH, CL = 1 µF (unless otherwise noted). AC performance is recorded as a chipset, TAS5518 as front end with an effective modulation index of 96.1% and TAS5261 as the power stage. PCB and system configuration are in accordance with recommended design guidelines. PARAMETER CONDITIONS MIN TYP MAX UNIT Internal Voltage Regulator and Current Consumption VREG Voltage regulator, only used as reference node IVDD VDD supply current IGVDD_x GVDD_x gate-supply current per half bridge IPVDD_x Half-bridge idle current 3.3 Operating, 50% duty cycle 7.7 Idle, reset mode 6.7 V mA 50% duty cycle 15 Idle, reset mode 1.5 50% duty cycle 23 mA 100 µA Reset mode (RESET = 1), No switching mA Output-Stage MOSFETs RDSON,LS Drain-to-source resistance, low side TJ = 25°C, LDMOS only 40 mΩ RDSON,HS Drain-to-source resistance, high side TJ = 25°C, LDMOS only 40 mΩ I/O Protection VUVP,POS Undervoltage protection limit, GVDD_x 8.5 V OTW Overtemperature warning 125 °C OTWhys OTW hysteresis 25 °C OTE Overtemperature error threshold 155 °C OTEhys OTE hysteresis 30 °C OTE-OTW differential Temperature delta between OTW and OTE 30 °C OLPC Overload protection time constant (1) fPWM = 384 kHz 20 Resistor programmable high end with OC_ADJ = 22 kΩ (1) 15 ms IOC Overcurrent limit response ROC Programming resistor RPD Pulldown resistor at the output of each half-bridge Connected when RESET is high to provide a charge path for the bootstrap capacitor 2.5 kΩ PWM PWM Activity Detector Lack of transition of any PWM input 13 µs (1) 16 22 17 A 100 kΩ DC measurement with 1-ms pulse Submit Documentation Feedback 9 TAS5261 www.ti.com SLES188 – AUGUST 2006 ELECTRICAL CHARACTERISTICS GVDD_x = 12 V ± 10%, VDD = 12 V ± 10%, TJ = 25°C (unless otherwise noted) PARAMETER CONDITIONS MIN TYP MAX UNIT Logic-Level and Open-Drain Outputs VIH High-level input voltage Static VIL Low-level input voltage Static Ilkg (1) Input leakage current 0.8 45 65 Static, Low PWM_A, Low PWM_B, Low M1, Low M2, Low M3 –10 10 Static, High RESET 20 40 Static, Low RESET –70 –50 Internal pulldown to AGND for PWM_A and PWM_B inputs RINT-PU Internal pullup resistance on OTW and SD VOH High-level output voltage VOL Low-level output voltage IO = 4 mA FANOUT Device fanout (OTW, SD) External pullup to 5 V 10 V Static, High PWM_A, High PWM_B, High M1, High M2, High M3 RINT-PD (1) 2 50 20 Internal pullup resistor 2.4 VREG External pullup of 3.3 kΩ to 5 V 2.5 4.9 Submit Documentation Feedback 33 0.4 10 µA kΩ Resistor to VREG Pullup and pulldown resistors affect the leakage current. 28 V kΩ V V Devices TAS5261 www.ti.com SLES188 – AUGUST 2006 TYPICAL CHARACTERISTICS blk TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER 10 5 2 1 0.5 T H D + N % 0.2 0.1 0.05 0.02 0.01 80m 200m 500m 1 2 5 10 20 50 100 200 300 Output Power W Red - 4 Ohm Blue - 6 Ohm Magenta - 8 Ohm Figure 3. OUTPUT POWER vs PVDD_x SUPPLY VOLTAGE UNCLIPPED OUTPUT POWER vs PVDD_x SUPPLY VOLTAGE 330 250 TC = 75°C THD+N at 10% 300 270 200 240 PO − Output Power − W PO − Output Power − W TC = 75°C 225 210 6Ω 180 150 4Ω 120 90 175 150 6Ω 125 4Ω 100 75 50 60 8Ω 30 8Ω 25 0 0 0 5 10 15 20 25 30 35 40 45 50 0 PVDD Supply Voltage − V 5 10 15 20 25 30 35 40 45 50 PVDD Supply Voltage − V G001 Figure 4. G003 Figure 5. Submit Documentation Feedback 11 TAS5261 www.ti.com SLES188 – AUGUST 2006 TYPICAL CHARACTERISTICS (continued) blk SYSTEM EFFICIENCY vs OUTPUT POWER SYSTEM POWER LOSS vs OUTPUT POWER 100 12 TC = 25°C 11 10 80 8 Power Loss − W Efficiency − % 9 60 40 7 6 5 4 3 20 2 TC = 25°C Two Channels 1 0 0 0 20 40 60 80 100 120 PO − Output Power − W 0 25 50 G004 Figure 6. Figure 7. SYSTEM OUTPUT POWER vs CASE TEMPERATURE 350 4Ω PO − Output Power − W 300 250 6Ω 200 8Ω 150 100 50 THD+N at 10% 0 0 25 50 75 100 TC − Case Temperature − °C Figure 8. 12 75 PO − Output Power − W Submit Documentation Feedback 125 G006 100 125 G005 TAS5261 www.ti.com SLES188 – AUGUST 2006 TYPICAL CHARACTERISTICS (continued) blk NOISE AMPLITUDE vs FREQUENCY +0 -5 -10 -15 -20 -25 -30 -35 -40 N o i s e -45 -50 -55 -60 A m p l i t u d e -65 -70 -75 -80 -85 -90 - -95 d B r -100 -105 -110 -115 -120 -125 -130 -135 -140 -145 -150 0 1k 2k 3k 4k 5k 6k 7k 8k 9k 10k 11k 12k 13k 14k 15k 16k 17k 18k 19k 20k 21k 22k f - Frequency - kHz Figure 9. Submit Documentation Feedback 13 TAS5261 www.ti.com SLES188 – AUGUST 2006 APPLICATION INFORMATION Typical Application Schematic 14 Submit Documentation Feedback TAS5261 www.ti.com SLES188 – AUGUST 2006 APPLICATION INFORMATION (continued) Recommended Printed Circuit Board (PCB) Layout PCB Requirements • • 2-oz copper (FR-4) recommended PVDD voltage and capacitor selection in accordance with the data sheet Figure 10. PCB (Top Layer) Figure 11. PCB (Bottom Layer) Submit Documentation Feedback 15 TAS5261 www.ti.com SLES188 – AUGUST 2006 THEORY OF OPERATION Power Supplies To facilitate system design, the TAS5261 needs only a 12-V supply in addition to a typical 50-V power-stage supply. An internal voltage regulator provides suitable voltage levels for the digital and low-voltage analog circuitry. Additionally, all circuitry requiring a floating voltage supply, e.g., the high-side gate drive, is accommodated by built-in bootstrap circuitry requiring only a few external capacitors. To provide outstanding electrical and acoustic characteristics, the PWM signal path, including gate drive and output stage, is designed as identical, independent half bridges. For this reason, each half bridge has separated gate-drive supply (GVDD_x), bootstrap pins (BST_x) and power-stage supply pins (PVDD_x). Furthermore, an additional pin (VDD) is provided as power supply for all common circuits. Although supplied from the same 12-V source, it is highly recommended to separate GVDD_x and VDD on the printed circuit board (PCB) by RC filters (see application diagram for details). These RC filters provide the recommended high-frequency isolation. Special attention should be paid to placing all decoupling capacitors as close to their associated pins as possible. In general, inductance between the power-supply pins and decoupling capacitors must be avoided. (See reference board documentation for additional information.) For a properly functioning bootstrap circuit, a small ceramic capacitor must be connected from each bootstrap pin (BST_x) to the power-stage output pin (OUT_x). When the power-stage output is low, the bootstrap capacitor is charged through an internal diode connected between the gate-drive power-supply pin (GVDD_x) and the bootstrap pin. When the power-stage output voltage is high, the bootstrap capacitor voltage is shifted above the output voltage potential and, thus, provides a suitable voltage supply for the high-side gate driver. In an application with PWM switching frequencies in the range of 352 kHz to 384 kHz, it is recommended to use 33-nF ceramic capacitors, size 0603 or 0805, for the bootstrap capacitor. These 33-nF capacitors ensure sufficient energy storage, even during minimal PWM duty cycles, to keep the high-side power-stage FET (LDMOS) fully started during all of the remaining part of the PWM cycle. In an application running at a reduced switching frequency, generally 250 kHz to 192 kHz, the bootstrap capacitor might need to be increased in value. Special attention should be paid to the power-stage power supply – this includes component selection, 16 PCB placement, and routing. As indicated, each half bridge has independent power-stage supply pins (PVDD_x). For optimal electrical performance, EMI compliance, and system reliability, it is important that each PVDD_x pin is decoupled with two 100-nF ceramic capacitors placed as close as possible to each supply pin on the same side of the PCB as the TAS5261 location. It is recommended to follow the PCB layout of the TAS5261 reference design. For additional information on the recommended power supply and required components, see the application diagrams given in this data sheet. The 12-V supply should be powered from a low-noise, low-output-impedance voltage regulator. Likewise, the 50-V power-stage supply is assumed to have low output impedance and low noise. The internal POR circuit eliminates the need for power-supply sequencing. Moreover, the TAS5261 is fully protected against erroneous power-stage turn on due to parasitic gate charging. Thus, voltage-supply ramp rates (dv/dt) are noncritical within the specified range (see the Recommended Operating Conditions section of this data sheet). System Power-Up/Power-Down Sequence Powering Up There is no power-up sequence is required for the TAS5261. The outputs of the H-bridge remain in a high-impedance state until the gate-drive supply voltage (GVDD_x) and VDD voltage are above the undervoltage protection (UVP) voltage threshold (see the Electrical Characteristics section of this data sheet). Although not specifically required, it is recommended to hold RESET in a low state while powering up the device. This allows an internal circuit to charge the external bootstrap capacitors by enabling a weak pulldown of the half-bridge output. While powering up the TAS5261, RESET should be held low. Powering Down There is no power-down sequence is required for the TAS5261. The device remains fully operational as long as the gate-drive supply (GVDD_x) voltage and VDD voltage are above the undervoltage protection (UVP) threshold level (see the Electrical Characteristics section of this data sheet). Although not specifically required, it is a good practice to hold RESET low during power down, thus, preventing audible artifacts including pops and clicks. Submit Documentation Feedback TAS5261 www.ti.com SLES188 – AUGUST 2006 Error Reporting The SD and OTW pins are both active-low, open-drain outputs. Their function is for protection-mode signaling to a PWM controller or other system-control device. Any fault resulting in device shutdown is signaled by the SD pin going low. Likewise, OTW goes low when the device junction temperature exceeds 115°C. (see Table 2). Table 2. Error Reporting SD OTW DESCRIPTION 0 0 Over Temperature (OTE) or Over Load (OLP) or Under Voltage (UVP) 0 1 Over Load (OLP), PWM Activity Dectector, or Under Voltage (UVP) 1 0 Over Temperature Warning. Junction temperature higher than 125°C. 1 1 Normal operation. Junction temperature lower than 125°C. It should be noted that asserting RESET low forces the SD and OTW signals high, independent of faults being present. It is recommended to monitor the OTW signal using the system microcontroller and respond to an overtemperature warning signal by, for example, turning down the volume to prevent further heating of the device resulting in device shutdown (OTW). To reduce external component count, an internal pullup resistor to 3.3 V is provided on both the SD and OTW outputs. Level compliance for 5-V logic can be obtained by adding external pullup resistors to 5 V (see the Electrical Characteristics section of this data sheet for further specifications). Device Protection System The TAS5261 contains advanced protection circuitry carefully designed to facilitate system integration and ease of use, as well as safeguarding the device from permanent failure due to a wide range of fault conditions, such as short circuit, overload, and undervoltage. The TAS5261 responds to a fault by immediately setting the power stage in a high-impedance state (Hi-Z) and asserting the SD pin low. In situations other than overload, the device automatically recovers when the fault condition has been removed (e.g., the voltage supply has increased). For highest possible reliability, recovering from an overload fault requires external reset of the device no sooner than 1 s after the shutdown (see the Device Reset section of this data sheet). Over Current (OC) Protection With Current Limiting and Overload Detection The device has independent, fast-reacting current detectors with programmable trip threshold (OC threshold) on all high-side and low-side power-stage FETs. See Table 3 for OC-adjust resistor values. The detector outputs are closely monitored by two protection systems. The first protection system controls the power stage in order to prevent the output current from further increasing. For instance, it performs a current-limiting function rather than prematurely shutting down during combinations of high-level music transients and extreme speaker load impedance drops. If the high-current situation persists, i.e., the power stage is being overloaded, a second protection system triggers a latching shutdown, resulting in the power stage being set in the high-impedance (Hi-Z) state. Table 3. OC-Adjust Resistor Values OC-ADJUST RESISTOR VALUES (kΩ) (1) (1) CURRENT BEFORE OC OCCURS (A) MIN TYP MAX 22 15 16 17 27 12 13 14 47 7 8 8 68 5 5 6 100 3 4 4 Resistor tolerance is ±5%. For lowest-cost bill of materials in terms of component selection, the OC threshold current should be limited, considering the power output requirement and minimum load impedance. Higher-impedance loads require a lower OC threshold. The demodulation filter inductor must retain a minimum of 5-H inductance at twice the selected OC threshold current. Most inductors have decreasing inductance with increasing temperature and increasing current (saturation). To some degree, an increase in temperature naturally occurs when operating at high output currents, due to inductor core losses and the dc resistance of the inductor copper winding. A thorough analysis of inductor saturation and thermal properties is strongly recommended. Setting the OC threshold too low might cause issues, such as lack of enough output power and/or unexpected shutdowns due to sensitive overload detection. In general, it is recommended to follow closely the external component selection and PCB layout as given in the Application Information section of this data sheet. Submit Documentation Feedback 17 TAS5261 www.ti.com SLES188 – AUGUST 2006 For added flexibility, the OC threshold is programmable within a limited range using a single external resistor connected between the OC_ADJ pin and AGND. It should be noted that a properly functioning overcurrent detector assumes the presence of a properly designed demodulation filter at the power-stage output. Short-circuit protection is not provided directly at the output pins of the power stage but only on the speaker terminals (after the demodulation filter). It is required to follow certain guidelines when selecting the OC threshold and an appropriate demodulation inductor. VDD or GVDD_x pin results in all half-bridge outputs immediately being set in the high-impedance state (Hi-Z) and SD being asserted low. The device automatically resumes operation when all supply voltages have increased above the UVP threshold. Over Temperature (OTE) Protection Asserting RESET input low removes fault information. A rising-edge transition on the reset input allows the device to resume operation after an overload fault. The TAS5261 has a two-level, temperature-protection system that asserts an active-low warning signal (OTW) when the device junction temperature exceeds the OTW level stated in the parametric table. If the device junction temperature exceeds the OTE level stated in the parametric table, the device is put into thermal shutdown, resulting in all half-bridge outputs being set in the high-impedance state (Hi-Z) and SD being asserted low. OTE is latched in this case. To clear the OTE latch, reset must be asserted. Thereafter, the device resumes normal operation. Under Voltage Protection (UVP) and Power-On Reset (POR) The UVP and POR circuits of the TAS5261 fully protect the device in any power-up/down and brownout situation. While powering up, the POR circuit resets the overload circuit (OLP) and ensures that all circuits are fully operational when the GVDD_x and VDD supply voltages reach the UVP level stated in the parametric table. Although GVDD_x and VDD are independently monitored, a supply-voltage drop below the UVP threshold on any Device Reset When RESET is asserted low, the output FETs in all half bridges are forced into a high-impedance state (Hi-Z). During this reset time, a resistor is connected between OUT_x and PGND pins, in order to charge the bootstrap capacitor. PWM Activity Detector The PWM Activity Detector logic monitors individual PWM inputs. If one or more inputs are stuck in either a high state or a low state for more than a defined length of time, the entire device is shut down. The PWM Activity Detector is not latched and normal operation resumes when PWM activity is present on the PWM inputs. When an invalid PWM frame is detected, the PWM Activity Detector responds immediately (no delay). The TAS5261 resumes operation as soon as valid PWM signals are present. The PWM Activity Detector is reported as a low on the SD pin. Modulation Index Setting 96.1% is the recommended setting for the modulation index limit of the PWM when driving the TAS5261. The following shows modulation index limit registers and setting value in hexadecimal for TI modulators. TAS5508/TAS5518: 0x16h at 04h TAS5086: 0x10h at 04h 18 Submit Documentation Feedback PACKAGE OPTION ADDENDUM www.ti.com 6-Dec-2006 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TAS5261DKD ACTIVE SSOP DKD 36 29 Green (RoHS & no Sb/Br) CU NIPDAU Level-4-260C-72 HR TAS5261DKDG4 ACTIVE SSOP DKD 36 29 Green (RoHS & no Sb/Br) CU NIPDAU Level-4-260C-72 HR TAS5261DKDR ACTIVE SSOP DKD 36 500 Green (RoHS & no Sb/Br) CU NIPDAU Level-4-260C-72 HR TAS5261DKDRG4 ACTIVE SSOP DKD 36 500 Green (RoHS & no Sb/Br) CU NIPDAU Level-4-260C-72 HR Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. 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