DATA SHEET MOS INTEGRATED CIRCUIT µ PD16347 192-BIT AC-PDP DRIVER DESCRIPTION The µ PD16347 is a high-withstanding-voltage CMOS driver designed for use with a flat display panel such as a PDP, VFD, or EL panel. It consists of a 192-bit bi-directional shift register, 192-bit latch and high-withstanding-voltage CMOS driver. The logic block operates with a 5.0 V power supply and 3.3 V interface so that it can be directly connected to a gate array and microcomputer. The driver block provides a high-withstanding-voltage output: 80 V. The logic and driver blocks are made of CMOS circuits, consuming lower power. FEATURES • 3-ch, 4-ch, 6-ch and 6-ch (3-ch + 3-ch) input port switching is possible using the IBS1 and IBS2 pins • Many outputs: 192-bit output • Clock transfer is switchable via the SDS pin between single edge and double edge • Data control with transfer clock (external) and latch • High-speed data transfer: fCLK = 60 MHz MAX. (at loading of data) • On-chip chip temperature detection circuit • High withstanding voltage and high drive output: 80 V MAX., +15/–30 mA MAX. • 3.3 V input interface (VDD1 = 5.0 V) • High-withstanding-voltage CMOS structure ORDERING INFORMATION Part Number Package µ PD16347N-xxx TCP (TAB package) Remark The TCP's external shape is customized. To order the required shape, please contact one of our sales representatives. The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. Document No. S16472EJ1V0DS00 (1st edition) Date Published June 2003 NS CP(K) Printed in Japan The mark ★ shows major revised points. 2002 µ PD16347 1. BLOCK DIAGRAM (1) IBS1 = L, IBS2 = H: 3-bit input HZ /LBLK /HBLK VDD2 /LE SR1 A1 A1 LE S1 S4 CLK CLK R,/L R,/L S190 CLR S1 S2 S3 /L1 O1 VSS2 /CLR SR2 A2 S2 S5 A2 CLK R,/L S191 CLR SR3 A3 A3 S3 S6 VDD2 CLK R,/L S192 CLR S190 S191 S192 /L192 O192 64-bit shift register VDD3 DET VSS2 Temperature detection VSS3 Remark /xxx indicates active low signal. 2 Data Sheet S16472EJ1V0DS µ PD16347 (2) IBS1 = L, IBS2 = L: 4-bit input HZ /LBLK /HBLK VDD2 /LE SR1 A1 S1 S5 CLK R,/L S189 CLR A1 CLK R,/L /CLR S1 LE S2 /L1 S3 S4 O1 SR2 A2 S2 S6 CLK R,/L S190 CLR A2 VSS2 SR3 A3 S3 S7 CLK R,/L S191 CLR A3 SR4 A4 S4 S8 CLK A4 R,/L S192 CLR 48-bit shift register VDD3 DET Temperature detection VDD2 S189 S190 S191 S192 /L192 O192 VSS3 VSS2 Data Sheet S16472EJ1V0DS 3 µ PD16347 (3) IBS1 = H, IBS2 = L: 6-bit input HZ /LBLK /HBLK VDD2 /LE SR1 A1 S1 S7 CLK R,/L S187 CLR A1 CLK R,/L SR2 A2 S2 S8 CLK R,/L S188 CLR A2 /CLR S1 LE S2 /L1 S3 S4 S5 S6 O1 VSS2 SR3 A3 S3 S9 CLK R,/L S189 CLR A3 SR4 A4 S4 S10 CLK R,/L S190 CLR A4 SR5 A5 S5 S11 CLK R,/L S191 CLR A5 SR6 A6 S6 S12 CLK R,/L S192 CLR A6 VDD2 S187 S188 S189 S190 S191 S192 /L192 O192 32-bit shift register VDD3 VSS2 DET Temperature detection VSS3 4 Data Sheet S16472EJ1V0DS µ PD16347 (4) IBS1 = H, IBS2 = H: 6-bit (3-bit + 3-bit) input HZ /LBLK /HBLK VDD2 /LE SR1 S1 A1 S4 CLK R,/L S94 CLR A1 CLK R,/L S1 LE S2 /L1 S3 S4 O1 SR2 S2 A2 S5 CLK R,/L S95 CLR A2 /CLR SR3 S3 A3 S6 CLK R,/L S96 CLR A3 SR4 S97 A4 CLK S187 R,/L S190 CLR A4 SR5 S98 A5 CLK S188 R,/L S191 CLR A5 SR6 S99 A6 CLK S189 R,/L S192 CLR A6 VSS2 S94 S95 S96 S97 S98 S99 VDD2 S187 S188 S189 S190 S191 S192 /L192 O192 32-bit shift register VDD3 VSS2 DET Temperature detection VSS3 Data Sheet S16472EJ1V0DS 5 µ PD16347 2. PIN CONFIGURATION (IC pad surface) µPD16347N-xxx: TCP (TAB package) O192 VSS2 O191 VDD2 O190 VSS2 O189 A6 A5 A4 A3 A2 A1 SDS /LE /CLR CLK /LBLK VDD3 IC pad surface DET VSS3 /HBLK VDD1 HZ IBS1 IBS2 VSS1 R,/L VSS2 O4 VDD2 O3 VSS2 O2 O1 Remark This figure does not specify the TCP package. 6 Data Sheet S16472EJ1V0DS µ PD16347 3. PIN FUNCTIONS Symbol Pin Name I/O Description /LBLK Low blanking Input /LBLK = L: All output = L /HBLK High blanking Input /HBLK = L: All output = H /LE Latch enable Input Latch operation performed at the falling edge. HZ Output high impedance Input HZ = H: All output set to the high-impedance state /CLR Register clear Input /CLR = L: All shift register data cleared to the low level A1 to A3 (6) Data Input The A1 to A3 (6) are Data input pins. The data shift direction is switched inside the R,/L pin. CLK Clock Input SDS = H: Shift operation is executed at the rising and falling edges SDS = L: Shift operation is executed at the rising edge R,/L Shift direction control Input The shift direction control pin of shift register. The shift directions of the shift register are as follows. R,/L = H (right shift): SR1: A1 → S1...S190 (SR2 to SR6 also shift in the same direction.) R,/L = L (left shift): SR1: A1 → S190...S1 (SR2 to SR6 also shift in the same direction.) Refer to 5. INTERNAL REGISTER. IBS1, Input mode switch Input IBS2 IBS1 = H, IBS2 = H: 6-bit (3-bit + 3-bit) input, Length of shift register: 32-bit IBS1 = H, IBS2 = L: 6-bit input, Length of shift register: 32-bit IBS1 = L, IBS2 = H: 3-bit input, Length of shift register: 64-bit IBS1 = L, IBS2 = L: 4-bit input, Length of shift register: 48-bit DET Temperature detection Output The DET is N-ch open-drain output. Low level is output (N-ch transistor: ON) via temperature detection. SDS Clock edge switch Input SDS = H: Shift operation is executed at the rising and falling edges of CLK (double edge) SDS = L: Shift operation is executed at the rising edge of CLK (single edge) O1 to O192 High withstanding voltage Output 70 V VDD1 Logic power supply − 5 V ± 5% VDD2 Driver power supply − 15 to 70 V VDD3 Temperature detection − 5 V ± 10% power supply VSS1 Logic ground − Connect to system ground VSS2 Driver ground − Connect to system ground VSS3 Temperature detection − Connect to system ground ground Caution In 3-bit and 4-bit input mode, unused input pins must be held at the low level or high level. Data Sheet S16472EJ1V0DS 7 µ PD16347 4. TRUTH TABLE Shift Register Block Input Shift Register R,/L SDS CLK H H ↑ or ↓ Right shift operation is executed. H H H or L Hold H L ↑ H L H or L Hold L H ↑ or ↓ Left shift operation is executed. L H H or L Hold L L ↑ L L H or L Right shift operation is executed. Left shift operation is executed. Hold Latch Block /LE ↓ H or L Output State of Latch Section (/Ln) Latch Sn data Hold latch (output) data Driver Block A /HBLK /LBLK HZ Output State of Driver Block O1 to O192 x L H L All driver output: H x x L L All driver output: L x x x H All driver output: High-impedance L H H L L H H H L H Remark x: H or L 8 Data Sheet S16472EJ1V0DS µ PD16347 5. INTERNAL REGISTER Shift Direction (R,/L = H, right shift) 3-bit input 4-bit input 6-bit input 6-bit (3-bit + 3-bit) input SR1 (A1 input register) A1 → S1, S4 … S190 A1 → S1, S5 … S189 A1 → S1, S7 … S187 A1 → S1, S4 … S94 SR2 (A2 input register) A2 → S2, S5 … S191 A2 → S2, S6 … S190 A2 → S2, S8 … S188 A2 → S2, S5 … S95 SR3 (A3 input register) A3 → S3, S6 … S192 A3 → S3, S7 … S191 A3 → S3, S9 … S189 A3 → S3, S6 … S96 A4 → S4, S10 … S190 A4 → S97, S100 … S190 SR5 (A5 input register) A4 → S4, S8 … S192 A5 → S5, S11 … S191 A5 → S98, S101 … S191 SR6 (A6 input register) A6 → S6, S12 … S192 A6 → S99, S102 … S192 SR4 (A4 input register) Shift Direction (R,/L = L, left shift) 3-bit input 4-bit input 6-bit input 6-bit (3-bit + 3-bit) input SR1 (A1 input register) A1 → S190, S187 … S1 A1 → S189, S185 … S1 A1 → S187, S181 … S1 A1 → S94, S91 … S1 SR2 (A2 input register) A2 → S191, S188 … S2 A2 → S190, S186 … S2 A2 → S188, S182 … S2 A2 → S95, S92 … S2 SR3 (A3 input register) A3 → S192, S189 … S3 A3 → S191, S187 … S3 A3 → S189, S183 … S3 A3 → S96, S93 … S3 A4 → S192, S188 … S4 A4 → S190, S184 … S4 A4 → S190, S187 … S97 SR5 (A5 input register) A5 → S191, S185 … S5 A5 → S191, S188 … S98 SR6 (A6 input register) A6 → S192, S186 … S6 A6 → S192, S189 … S99 SR4 (A4 input register) Data Sheet S16472EJ1V0DS 9 µ PD16347 6. TIMING CHART (1) IBS1 = L, IBS2 = H: 3-bit input, SDS = L: single edge CLK /CLR A1 (A3) A2 (A2) A3 (A1) S1 (S192) S2 (S191) S3 (S190) S4 (S189) /LE (Latch at the falling edge) /LBLK /HBLK HZ High-impedance O1 (O192) O2 (O191) O3 (O190) O4 (O189) Remark Values in parentheses are when R,/L = L. 10 Data Sheet S16472EJ1V0DS µ PD16347 (2) IBS1 = L, IBS2 = H: 3-bit input, SDS = H: double edge Loading of data starts at first falling edge or at first rising edge CLK /CLR A1 (A3) A2 (A2) A3 (A1) S1 (S192) S2 (S191) S3 (S190) S4 (S189) /LE (Latch at the falling edge) /LBLK /HBLK HZ High-impedance O1 (O192) O2 (O191) O3 (O190) O4 (O189) Remark Values in parentheses are when R,/L = L. Data Sheet S16472EJ1V0DS 11 µ PD16347 (3) IBS1 = L, IBS2 = L: 4-bit input, SDS = L: single edge CLK /CLR A1 (A4) A2 (A3) A3 (A2) A4 (A1) S1 (S192) S2 (S191) S3 (S190) S4 (S189) /LE (Latch at the falling edge) /LBLK /HBLK HZ High-impedance O1 (O192) O2 (O191) O3 (O190) O4 (O189) Remark Values in parentheses are when R,/L = L. 12 Data Sheet S16472EJ1V0DS µ PD16347 (4) IBS1 = L, IBS2 = L: 4-bit input, SDS = H: double edge Loading of data starts at first falling edge or at first rising edge CLK /CLR A1 (A4) A2 (A3) A3 (A2) A4 (A1) S1 (S192) S2 (S191) S3 (S190) S4 (S189) /LE (Latch at the falling edge) /LBLK /HBLK HZ High-impedance O1 (O192) O2 (O191) O3 (O190) O4 (O189) Remark Values in parentheses are when R,/L = L. Data Sheet S16472EJ1V0DS 13 µ PD16347 (5) IBS1 = H, IBS2 = L: 6-bit input, SDS = L: single edge CLK /CLR A1 (A6) A2 (A5) A3 (A4) A4 (A3) A5 (A2) A6 (A1) S1 (S192) S2 (S191) S3 (S190) S4 (S189) S5 (S188) S6 (S187) /LE (Latch at the falling edge) /LBLK /HBLK HZ High-impedance O1 (O192) O2 (O191) O3 (O190) O4 (O189) O5 (O188) O6 (O187) Remark Values in parentheses are when R,/L = L. 14 Data Sheet S16472EJ1V0DS µ PD16347 (6) IBS1 = H, IBS2 = L: 6-bit input, SDS = H: double edge Loading of data starts at first falling edge or at first rising edge CLK /CLR A1 (A6) A2 (A5) A3 (A4) A4 (A3) A5 (A2) A6 (A1) S1 (S192) S2 (S191) S3 (S190) S4 (S189) S5 (S188) S6 (S187) /LE (Latch at the falling edge) /LBLK /HBLK HZ High-impedance O1 (O192) O2 (O191) O3 (O190) O4 (O189) O5 (O188) O6 (O187) Remark Values in parentheses are when R,/L = L. Data Sheet S16472EJ1V0DS 15 µ PD16347 (7) IBS1 = H, IBS2 = H: 6-bit (3-bit + 3-bit) input, SDS = L: single edge CLK /CLR A1 (A3) A2 (A2) A3 (A1) A4 (A6) A5 (A5) A6 (A4) S1 (S96) S2 (S95) S3 (S94) S97 (S192) S98 (S191) S99 (S190) /LE (Latch at the falling edge) /LBLK /HBLK HZ High-impedance O1 (O96) O2 (O95) O3 (O94) O97 (O192) O98 (O191) O99 (O190) Remark Values in parentheses are when R,/L = L. 16 Data Sheet S16472EJ1V0DS µ PD16347 (8) IBS1 = H, IBS2 = H: 6-bit (3-bit + 3-bit) input, SDS = H: double edge Loading of data starts at first falling edge or at first rising edge CLK /CLR A1 (A3) A2 (A2) A3 (A1) A4 (A6) A5 (A5) A6 (A4) S1 (S96) S2 (S95) S3 (S94) S97 (S192) S98 (S191) S99 (S190) /LE (Latch at the falling edge) /LBLK /HBLK HZ High-impedance O1 (O96) O2 (O95) O3 (O94) O97 (O192) O98 (O191) O99 (O190) Remark Values in parentheses are when R,/L = L. Data Sheet S16472EJ1V0DS 17 µ PD16347 7. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (TA = 25°°C, VSS1 = VSS2 = VSS3 = 0 V) Parameter Symbol Ratings Unit Logic and temperature detection supply voltage VDD1, VDD3 −0.5 to +6.0 V Driver supply voltage VDD2 −0.5 to +80 V Logic input voltage VI1 −0.5 to VDD1 + 0.5 V Temperature detection input voltage VI3 −0.5 to VDD3 + 0.5 V Operating junction temperature Tj +125 °C Storage temperature Tstg −65 to +125 °C Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Recommended Operating Range (TA = −40 to +85°°C, VSS1 = VSS2 = VSS3 = 0 V) Parameter Symbol MIN. TYP. MAX. Unit 5.0 5.25 V 70 V 5.5 V Logic supply voltage VDD1 4.75 Driver supply voltage VDD2 15 Temperature detection supply voltage VDD3 4.5 Logic high level input voltage VIH11 2.7 VDD1 V Logic low level input voltage VIL11 0 0.6 V IBS and R,/L high level input voltage VIH12 0.7 VDD1 VDD1 V IBS and R,/L low level input voltage VIL12 0 0.2 VDD1 V Driver output current IOH2 −24 mA IOL2 +13 mA 18 Data Sheet S16472EJ1V0DS 5.0 µ PD16347 ★ Electrical Characteristics (TA = 25°°C, VDD1 = VDD3 = 5.0 V, VDD2 = 70 V, VSS1 = VSS2 = VSS3 = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit VOH21 IOH2 = −0.52 mA 69 V VOH22 IOH2 = −5.2 mA 65 V Low level output voltage VOL21 IOL2 = 1.6 mA VOL22 IOL2 = 13 mA Input leakage current II VI1 = VDD1 or VSS1, High level output voltage 1.0 V 10 V ±1.0 µA VI3 = VDD3 or VSS3 Logic high level input voltage VIH11 VDD1 = 4.75 to 5.25 V 2.7 VDD1 V Logic low level input voltage VIL11 VDD1 = 4.75 to 5.25 V 0 0.6 V IBS and R,/L high level input voltage VIH12 0.7 VDD1 VDD1 V IBS and R,/L low level input voltage VIL12 0 0.2 VDD1 V Detection temperature TDET 110 135 °C Detection temperature hysteresis width Thys 10 15 °C Temperature detection output (N-ch) RDET 0.1 VDD3 V Logic, TA = −40 to +85°C 1000 µA Logic, TA = 25°C 600 µA Static current dissipation VSS3 to DET voltage, IO = 1 mA characteristic IDD11 IDD12 Logic, TA = −40 to +85°C Logic, TA = 25°C IDD3 10 10 Note Note mA mA 1000 µA 800 µA Driver, TA = −40 to +85°C 1000 µA Driver, TA = 25°C 100 µA Temperature detection, TA = −40 to +85°C Temperature detection, TA = 25°C IDD2 Note When input all input high level (VIH = 2.7 V to VDD1, but both the R,/L and IBS pins are fixed to VI = VSS1 or VDD1) Data Sheet S16472EJ1V0DS 19 µ PD16347 Switching Characteristics (TA = 25°°C, VDD1 = VDD3 = 5.0 V, VDD2 = 70 V, VSS1 = VSS2 = VSS3 = 0 V, Logic CL = 15 pF, Driver CL = 50 pF, tr = tf = 3.0 ns) Parameter Propagation delay time Symbol tPHL2 Conditions MIN. /LE ↓ → O1 to O192 tPLH2 tPHL3 /HBLK → O1 to O192 tPLH3 tPHL4 /LBLK → O1 to O192 tPLH4 Rise time TYP. MAX. Unit 220 ns 220 ns 205 ns 205 ns 200 ns 200 ns tPHZ HZ → O1 to O192, 340 ns tPZH RL = 10 kΩ 220 ns tPLZ 340 ns tPZL 220 ns tTLH O1 to O192 220 ns tTLZ O1 to O192, 3 µs tTZH RL = 10 kΩ 220 ns tTHL O1 to O192 350 ns tTHZ O1 to O192, 3 µs tTZL RL = 10 kΩ 350 ns Maximum clock frequency fMAX. Loading of data, duty = 50% Input capacitance CI Fall time 20 60 MHz 15 Data Sheet S16472EJ1V0DS pF µ PD16347 Timing Requirement (TA = 25°°C, VDD1 = 4.75 to 5.25 V, VSS1 = VSS2 = VSS3 = 0 V, tr = tf = 3.0 ns) Parameter Symbol Conditions MIN. TYP. MAX. Unit Clock pulse width PW CLK 8 ns Latch enable pulse width PW /LE 8 ns Blank pulse width PW /BLK /HBLK, /LBLK 600 ns HZ pulse width PW HZ RL = 10 kΩ 3.3 µs /CLR pulse width PW /CLR 12 ns /CLR timing t/CLR 6 ns Data setup time tSETUP 3 ns Data hold time tHOLD 3 ns Latch enable Time t/LE11, t/LE21 8 ns t/LE12, t/LE22 8 ns ★ Detection Temperature Hysteresis Width and Detection Output <Detection output circuit> VDD (Microcomputer side) 10 kΩ "H" To a microcomputer DET output DET to Thys MIN. Note Thys MAX.Note "L" Tj (˚C) TDET MIN. VSS3 TDET MAX. Note Change of Thys linked with TDET's. Data Sheet S16472EJ1V0DS 21 µ PD16347 Switching Characteristics Waveform (1/3) 1/fMAX. PWCLK PWCLK 3.3 V 50% CLK 50% 50% 0V tHOLD tSETUP 3.3 V An (Input) 50% 50% 0V Remark The falling timing of CLK is at SDS = H (double edge). 3.3 V /LE 50% 50% 0V PW/LE PW/LE t/LE11 t/LE21 3.3 V CLK (SDS = L) 50% 0V t/LE12 CLK (SDS = H) 50% t/LE22 3.3 V 50% 50% 0V tPHL2 tTHL VOH2 90% On 10% tPLH2 VOL2 tTLH VOH2 90% On 10% 22 Data Sheet S16472EJ1V0DS VOL2 µ PD16347 Switching Characteristics Waveform (2/3) PW/BLK 3.3 V /LBLK 50% 50% 0V tPLH4 tPHL4 VOH2 90% On 10% VOL2 PW/BLK 3.3 V /HBLK 50% 50% 0V tPLH3 tPHL3 VOH2 90% On 10% VOL2 PW/CLR 3.3 V /CLR 50% 50% 0V t/CLR 3.3 V CLK (SDS = L) 50% 0V The rising (falling) edge of CLK for valid data 3.3 V CLK (SDS = H) 50% 0V Data Sheet S16472EJ1V0DS 23 µ PD16347 Switching Characteristics Waveform (3/3) PWHZ 3.3 V HZ 50% 50% 0V tPLZ tPZL tTLZ tTZL VO (H) 90% 90% On 10% 10% VOL2 VOH2 90% 90% On 10% tPHZ 24 tTHZ Data Sheet S16472EJ1V0DS 10% tPZH tTZH VO (L) µ PD16347 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. Data Sheet S16472EJ1V0DS 25 µ PD16347 Reference Documents NEC Semiconductor Device Reliability/Quality Control System (C10983E) Quality Grades On NEC Semiconductor Devices (C11531E) • The information in this document is current as of June, 2003. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. • No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics. 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