NEC UPD16310

MOS INTEGRATED CIRCUIT
µPD16310
HIGH VOLTAGE CMOS DRIVER FOR PDP, EL, VFD
DESCRIPTION
µPD16310 is high voltage driver for PDP, EL or VFD graphic panel structured by CMOS process. Logic power
supply is 5.0 V connecting direct to control logic. Maximum output voltage is 80 V and maximum current is 50 mA.
FEATURES
• 80 V Output Voltage Swing Capability
• 50 mA Output Sink and Source Current Capability
• 40 bit Shift-register and Latch
• High Speed Serial DATA Transferring (fmax. = 20 MHz
MIN.)
• Low Standby Current 100 µA
ORDERING INFORMATION
Part Number
Package
µPD16310GF-3L9
80-pin plastic QFP (3 direction lead)
Document No. IC-2859 (1st edition)
Date Published March 1997 P
Printed in Japan
©
1993
µPD16310
PIN CONNECTION DIAGRAM (Top View)
59
O35
7
58
O34
O8
8
57
O33
O9
9
56
O32
O10
10
55
O31
O11
11
54
O30
O12
12
53
O29
O13
13
52
O28
O14
14
51
O27
O15
15
50
O26
O16
16
49
O25
O17
17
48
O24
O18
18
47
O23
O19
19
46
O22
O20
20
45
O21
VDD2
21
44
VDD2
VSS2
22
43
VSS2
VSS2
23
42
VSS2
VSS1
24
25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
41
VSS1
NC
6
O7
NC
O6
VDD1
O36
BLK
O37
60
B
61
5
STB
4
O5
NC
O4
NC
O38
NC
62
CLK
3
A
O3
NC
O39
NC
O40
63
PC
64
2
R/L
1
VDD1
O1
O2
Note The 33 pin (NC) should be open.
All the power supply terminals should be used.
VSS1 and VSS2 should be respectively connected with themselves outside.
To prevent latch up breakdown, the power should be turned ON in order VDD1, logic input, VDD2.
It should be turned OFF in the opposite order.
This relationship should be followed during transition period as well.
2
µPD16310
BLOCK DIAGRAM
PC
BLK
STB
S1
A
O1
L1
A
CLK
CLK
R/L
R/L
B
STB
*
B
S40
40 bit
Shift Register
O40
L40
40 bit Latch
* High Voltage CMOS Driver
80 V ± 50 mAMAX.
3
µPD16310
PN CONFIGURATION
PIN No.
SYMBOL
PIN NAME
FUNCTION
27
PC
Polarity Change Input
All driver outputs’ level are inverted while PC is L.
37
BLK
Blank Input
All driver outputs are H or L while BLK is H.
36
STB
Latch Strobe Input
Latch’s status is data through while STB is L.
30
A
Right Data Input/Output
R/L = H : A = IN, B = OUT
R/L = L : A = OUT, B = IN
35
B
Left Data Input/Output
31
CLK
Clock Input
Data of shift-register is shifted while CLK is going
H to L. (Negative edge is active.)
25
R/L
Shift Direction Control Input
H: Right Shift Mode
A → O1 ··· O40 → B
L: left Shift Mode
B → O40 ··· O1 → A
1 - 20
45 - 64
O1 - O40
Driver Outputs
High voltage output 80 V, 50 mA
26, 39
VDD1
Logic Power Supply
5.0 V ± 10 %
21, 44
VDD2
Driver Power Supply
10 to 70 V
24, 41
VSS1
Ground (for Logic)
Connect to the system ground.
22, 23, 42, 43
VSS2
Ground (for Driver)
Connect to the system ground.
28, 29, 32 - 34
38, 40
NC
No Connect
No. 33 pin should be open.
TRUTH TABLE 1 (Shift-Register part)
INPUT
IN/OUT
SHIFT-REGISTER
R/L
CLK
A
B
H
↓
IN
OUT
DATA is shifted.
H
H or L
IN
OUT
No Change.
L
↓
OUT
IN
DATA is shifted.
L
H or L
OUT
IN
No Change.
TRUTH TABLE 2 (Latch, Driver part)
INPUT
DRIVER OUTPUT
A (B)
STB
BLK
PC
X
X
H
H
ALL H
X
X
H
L
ALL L
H
L
L
H
H
H
L
L
L
L
L
L
L
H
L
L
L
L
L
H
X
H
L
H
Latch’s data output
X
H
L
L
Latch’s data output (inverting)
X = H or L, H = High Level, L = Low Level
4
µPD16310
TIMING CHART
(
) : R/L = L
A (B)
(INPUT)
CLK
S1
(S40)
S2
(S39)
S3
(S38)
STB
BLK
PC
O1
(O40)
O2
(O39)
O3
(O38)
5
µPD16310
ABSOLUTE MAXIMUM RATINGS (Ta = 25 °C, VSS1 = VSS2 = 0 V)
PARAMETER
SYMBOL
RATINGS
UNIT
VDD1
–0.5 to +7.0
V
VI
–0.5 to VDD1 + 0.5
V
Logic Output Voltage
VO1
–0.5 to VDD1 + 0.5
V
Driver Power Supply
VDD2
–0.5 to 80
V
Driver Output Voltage
VO2
–0.5 to VDD2 + 0.5
V
Drive Maximum Current
IO2
±50
mA
Power Dissipation
PD
1 000
mW
Operating Temperature
Topt
–40 to +85
°C
Storage Temperature
Tstg
–65 to +150
°C
Logic Power Supply
Input Voltage
RECOMMENDED OPERATING CONDITIONS (Ta = 25 °C, VSS1 = VSS2 = 0 V)
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
VDD1
4.5
5.0
5.5
V
High Level Input Voltage
VIH
0.7 · VDD1
VDD1
V
Low Level Input Voltage
VIL
0
0.2 · VDD1
V
Driver Power Supply
VDD2
10
70
V
Driver Output Current
IOL2
+40
mA
IOH2
–40
mA
Logic Power Supply
DC CHARACTERISTICS (Ta = 25 °C, VDD1 = 5.0 V, VDD2 = 70 V, VSS1 = VSS2 = 0 V)
PARAMETER
SYMBOL
MIN.
Hight Level Output Voltage
VOH1
0.9 · VDD1
Low Level Output Voltage
VOL1
High Level Output Voltage
VOH21
VOH22
Low Level Output Voltage
6
TYP.
MAX.
UNIT
TEST CONDITIONS
V
Logic, IOH1 = –1.0 mA
V
Logic, IOL1 = 1.0 mA
69
V
O1 - O40, IOH2 = –1.0 mA
65
V
O1 - O40, IOH2 = –10 mA
0.1 · VDD1
VOL21
1.0
V
O1 - O40, IOL2 = 5.0 mA
VOL22
10
V
O1 - O40, IOL2 = 40 mA
High Level Input Current
IIH
1.0
µA
VI = VDD1
Low Level Input Current
IIL
–1.0
µA
VI = 0 V
High Level Input Voltage
VIH
Low Level Input Voltage
VIL
0.2 · VDD1
V
Standby Current
IDD1
10
µA
for VDD1, Ta = 25 °C
IDD1
100
µA
for VDD1, Ta = –40 to +85 °C
IDD2
100
µA
for VDD2, Ta = 25 °C
IDD2
1 000
µA
for VDD2, Ta = –40 to +85 °C
0.7 · VDD1
V
µPD16310
AC CHARACTERISTICS (Ta = 25 °C, VDD1 = 5.0 V, VDD2 = 70 V, VSS1 = VSS2 = 0 V, Logic CL = 15 pF,
Driver CL = 50 pF)
PARAMETER
MAX.
UNIT
tPHL1
50
ns
tPLH1
50
ns
tPHL2
160
ns
tPLH2
160
ns
tPHL3
150
ns
tPLH3
150
ns
tPHL4
145
ns
tPLH4
145
ns
tPHL5
140
ns
tPLH5
140
ns
Rise Time
tTLH
70
ns
O1 - O40
Fall Time
tTHL
70
ns
O1 - O40
Maximum Frequency
fmax.
Delay Time
Input Capacitance
SYMBOL
MIN.
20
CI
TYP.
30
10
MHz
20
TEST CONDITIONS
CLK → A/B
CLK → O1 - O40
STB → O1 - O40
BLK → O1 - O40
PC → O1 - O40
Duty = 50 %, for CLK
pF
AC TIMING REQUIREMENT (Ta = –40 to +85 °C, VDD1 = 4.5 to 5.5 V, VDD2 = 10 to 70 V
VSS1 = VSS2 = 0 V)
PARAMETER
SYMBOL
MIN.
Clock Pulse Width
PWCLK
20
ns
Strobe Pulse Width
PWSTB
20
ns
Blank Pulse Width
PWBLK
200
ns
Polarity Change Pulse Width
PWPC
200
ns
Data Setup Time
tSETUP
10
ns
Data Hold Time
tHOLD
10
ns
tCLK-STB
50
ns
Setup Time
TYP.
MAX.
UNIT
TEST CONDITIONS
for CLK ↓ to STB ↑
7
µPD16310
AC CHARACTERISTICS WAVEFORM
1/fCLK
PWCLK(L)
PWCLK(H)
VDD1
50 %
CLK
50 %
50 %
VSS1
tSETUP
tHOLD
VDD1
A/B
(INPUT)
50 %
50 %
50 %
VSS1
tPHL1
tPLH1
VOH1
B/A
(OUTPUT)
50 %
50 %
VOL1
tPHL2
tTHL
VOH2
90 %
90 %
On
10 %
10 %
tPLH2
VOL2
tTLH
VDD1
CLK
50 %
VSS1
tCLK-STB
PWSTB
VDD1
STB
50 %
50 %
VSS1
tPHL3
VOH2
90 %
On
VOL2
tPLH3
VOH2
On
10 %
8
VOL2
µPD16310
PWBLK
VDD1
BLK
50 %
50 %
tPHL4
tPLH4
VSS1
VOH1
90 %
On
10 %
VOL2
PWPC
VDD1
PC
50 %
50 %
tPHL5
tPLH5
VSS1
VOH2
90 %
On
10 %
VOL2
9
µPD16310
PACKAGE DIMENSIONS
80 PIN PLASTIC QFP (THREE DIRECTIONS) (14×20)
A
B
41
40
64
65
detail of lead end
S
C D
R
Q
F
25
24
80
1
G
J
H
I
P
M
K
M
N
L
NOTE
Each lead centerline is located within 0.15 mm (0.006 inch) of
its true position (T.P.) at maximum material condition.
ITEM
MILLIMETERS
INCHES
A
22.3±0.4
0.878±0.016
B
20.0±0.2
0.795 +0.009
–0.008
C
14.0±0.2
0.551 +0.009
–0.008
D
17.6±0.4
0.693±0.016
F
1.0
0.039
G
0.8
0.031
H
0.35±0.10
0.014 +0.004
–0.005
I
0.15
0.006
J
0.8 (T.P.)
0.031 (T.P.)
K
1.8±0.2
0.071 +0.008
–0.009
L
0.8±0.2
0.031 +0.009
–0.008
M
0.15 +0.10
–0.05
0.006 +0.004
–0.003
N
0.10
0.004
P
2.7
0.106
Q
0.1±0.1
0.004±0.004
R
5°±5°
5°±5°
S
3.0 MAX.
0.119 MAX.
P80GF-80-3L9-2
10
µPD16310
RECOMMENDED SOLDERING CONDITIONS
The following conditions (see table below) must be met when soldering this product. Please consult with our sales
offices in case other soldering process is used, or in case soldering is done under different conditions.
µPD16310GF-3L9
Soldering process
Soldering conditions
Symbol
Infrared ray reflow
Peak package’s surface temperature: 230 °C or below,
Reflow time: 30 seconds or below (210 °C or higher),
Number of reflow process: 1, Exposure limit*: None
IR30-00-1
VPS
Peak package’s surface temperature: 215 °C or below,
Reflow time: 40 seconds or below (200 °C or higher),
Number of reflow process: 1, Exposure limit*: None
VP15-00-1
Partial heating method
Terminal temperature: 300 °C or below,
Flow time: 10 seconds or below,
Exposure limit*: None
* Exposure limit before soldering after dry-pack package is opened.
Storage coditions: 25 °C and relative humidity at 65 % or less.
Note Do not apply more than a single process at once, except for “Partial heating method.”
11
µPD16310
[MEMO]
12
µPD16310
[MEMO]
13
µPD16310
[MEMO]
No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
Anti-radioactive design is not implemented in this product.
M4 96.5
2