DATA SHEET MOS INTEGRATED CIRCUIT µPD16334 96-Bit AC-PDP DRIVER The µPD16334 is a high-voltage CMOS driver designed for flat display panels such as PDPs, VFDs and ELs. It consists of a 96-bit bi-directional shift register, 96-bit latch and high-voltage CMOS driver. The logic block is designed to operate using a 5-V power supply/3.3-V interface enabling direct connection to a gate array or a microcontroller. In addition, the µPD16334 achieves low power dissipation by employing the CMOS structure while having a high withstand voltage output (80 V, 50 mA). FEATURES • Selectable by IBS pin; three 32-bit bi-directional shift register circuits configuration or six 16-bit bi-directional shift register circuits configuration • Data control with transfer clock (external) and latch • High-speed data transfer (fmax. = 25 MHz min. at data fetch) (fmax. = 15 MHz min. at cascade connection) • High withstand output voltage (80 V, 50 mA MAX.) • 3.3 V CMOS input interface • High withstand voltage CMOS structure • Capable of reversing all driver outputs by PC pin ORDERING INFORMATION Part Number Package µPD16334 COB* * Please consult with an NEC sales representative about COB. Document No. S12362EJ2V0DS00 (2nd edition) Date Published May 1998 N CP(K) Printed in Japan © 1997 µPD16334 BLOCK DIAGRAM (IBS = H, 3-BIT INPUT, 32-BIT LENGTH SHIFT REGISTER) OE PC BLK VDD2 LE SR1 A1 S1 S1 S4 S2 S3 A1 CLK CLK R/L R/L B1 B1 A2 A2 L1 O1 VSS2 S94 SR2 S2 S5 CLK R/L B2 B2 A3 A3 S95 SR3 S3 S6 VDD2 CLK B3 R/L S94 B3 S95 S96 S96 L96 O96 SRn: 32-bit shift register VSS2 2 µPD16334 BLOCK DIAGRAM (IBS = L, 6-BIT INPUT, 16-BIT LENGTH SHIFT REGISTER) OE PC BLK VDD2 LE A1 CLK R/L B1 A2 B2 A3 B3 A4 B4 A5 B5 A6 B6 SR1 A1 S1 S7 CLK R/L S91 B1 SR2 A2 S2 S8 CLK R/L S92 B2 S1 LE S2 L1 S3 S4 S5 S6 O1 VSS2 SR3 A3 S3 S9 CLK R/L S93 B3 SR4 A4 S4 CLK S10 R/L S94 B4 SR5 A5 S5 CLK S11 R/L S95 B5 SR6 A6 S6 CLK S12 R/L S96 B6 VDD2 S93 S94 S95 S96 L96 O96 SRn: 16-bit shift register VSS2 3 µPD16334 PIN DESCRIPTION Symbol PC Pin Name Description Polarity change input PC = L: All driver output invert BLK Blank input BLK = H : All output = H or L LE Latch enable input Automatically executes latch by setting high at rising edge OE Output enable of the clock A1 to A3 Make output high impedance by input H RIGHT data input/output (6) (Note) When R/L=H (values in parentheses are for 6-bit input) A1 to A3 (6) : Input B1 to B3 (6) : Output (Note) B1 to B3 (6) LEFT data input/output When R/L=L (values in parentheses are for 6-bit input) CLK Clock input Shift executed on fall R/L Shift control input Right shift mode when R/L= H A1 to A3 (6) : Output B1 to B3 (6) : Input SR1 : A1 → S1...S94 → B1 (Same direction for SR2 to SR6) Left shift mode when R/L= L SR1 : B1 → S94...S1 → A1 (Same direction for SR2 to SR6) IBS Input mode switch H: 32-bit length shift register, 3-bit input O1 to O96 High withstand voltage output 80 V, 50 mAMAX. VDD1 Power supply for logic block 5 V ± 10 % VDD2 Power supply for driver block 10 to 70 V V SS1 Logic GND Connect to system GND V SS2 Driver GND Connect to system GND L: 16-bit length shift register, 6-bit input Note When input mode is 3-bit, set unused input and output pins “L” level. TRUTH TABLE 1 (Shift Register Block) Input Output R/L CLK H ↓ H H or L L ↓ L H or L A Shift Register B Input Output Note1 Right shift execution Output Hold Output Note2 Input Left shift execution Output Hold Notes 1. The data of S91 to S93 (S85 to S90) shifts to S94 to S96 (S91 to S96) and is output from B1 to B3 (B1 to B6) at the falling edge of the clock, respectively. (Values in parentheses are for 6-bit input) 2. The data of S4 to S6 (S7 to S12) shifts to S1 to S3 (S1 to S6) and is output from A1 to A3 (A1 to A6) at the falling edge of the clock, respectively (Values in parentheses are for 6-bit input) TRUTH TABLE 2 (Latch Block) LE CLK H ↑ Latch Sn data and hold output data ↓ Hold latch data X Hold latch data L Output State of Latch Block (Ln) TRUTH TABLE 3 (Driver Block) Ln BLK PC OE X H H L H (All driver outputs: H) X H L L L (All driver outputs: L) X L H L Output latch data (Ln) X L L L Output inverted latch data (Ln) X X X H Set output impedance high X: H or L, H: High level, L: Low level 4 Output State of Driver Block µPD16334 TIMING CHART (WHEN IBS=”H”: 3-BIT INPUT, RIGHT SHIFT) Values in parentheses in the following chart are when R/L=L. CLK A1 (B3) ,, ,,, ,, ,,, A2 (B2) A3 (B1) S1 (S96) S2 (S95) S3 (S94) S4 (S93) S5 (S92) S6 (S91) LE BLK PC OE High impedance O1 (O96) O2 (O95) O3 (O94) O4 (O93) O5 (O92) O6 (O91) 5 µPD16334 TIMING CHART (WHEN IBS=”L”: 6-BIT INPUT, RIGHT SHIFT) Values in parentheses in the following chart are when R/L=L. CLK A1 (B6) A2 (B5) A3 (B4) A4 (B3) ,,, ,,, ,,, ,,, ,,,, A5 (B2) A6 (B1) S1 (S96) S2 (S95) S3 (S94) S4 (S93) S5 (S92) S6 (S91) S7 (S90) LE BLK PC OE O1 (O96) O2 (O95) O3 (O94) O4 (O93) O5 (O92) O6 (O91) O7 (O90) 6 High impedance µPD16334 ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, VSS1 = VSS2 = 0 V) Symbol Ratings Unit Logic Block Supply Voltage Parameter VDD1 –0.5 to +7.0 V Driver Block Supply Voltage VDD2 –0.5 to +80 V Logic Block Input Voltage VI –0.5 to VDD1 + 0.5 V Driver Block Output Current IO2 50 mA Junction Temperature Tj +125 °C Storage Temperature T stg. –65 to +150 °C RECOMMENDED OPERATING CONDITIONS (TA = –40 to +85 °C, V SS1 = VSS2 = 0 V) Parameter Symbol MIN. TYP. MAX. Unit Logic Block Supply Voltage VDD1 4.75 5.0 5.25 V Driver Block Supply Voltage VDD2 10 70 V High-Level Input Voltage VIH 2.7 VDD1 V Low-Level Input Voltage VIL 0 0.6 V Driver Output Current IOH2 –40 mA IOL2 +40 mA Caution In order to prevent latch-up breakage, be sure to enter the power to VDD1, logic signal and VDD2 in that order, and turn off the power in the reverse order, keep this order also during a transition period. ELECTRICAL SPECIFICATIONS (T A = 25 °C, VDD1 = 5.0 V, VDD2 = 70 V, VSS1 = VSS2 = 0 V) Parameter High-Level Output Voltage Symbol Conditions MAX. Unit 0.9 • VDD1 VDD1 V Logic, IOL1 = 1.0 mA 0 0.1 VDD1 V O1 to O96, IOH2 = –1 mA 69 V VOH22 O1 to O96, IOH2 = –10 mA 65 V VOL21 O1 to O96, IOL2 = 5 mA 1.0 V VOL22 O1 to O96, IOL2 = 40 mA 10 V ±1.0 µA VOH1 Logic, I OH1 = –1.0 mA Low-Level Output Voltage VOL1 High-Level Output Voltage VOH21 Low-Level Output Voltage Input Leakage Current IIL VI = VDD1 or VSS1 High-Level Input Voltage VIH VDD1 = 4.75 to 5.25 V Low-Level Input Voltage VIL VDD1 = 4.75 to 5.25 V Static Current Dissipation MIN. TYP. 2.7 V 0.6 V Note mA IDD1 Logic, TA = –40 to +85 °C 10 IDD1 Logic, T A = 25 °C 10 Note mA IDD2 Driver, TA = –40 to +85 °C 1000 µA IDD2 Driver, TA = 25 °C 100 µA Note When all inputs are high-level (VIH = 2.7 V to VDD1, the R/L and IBS pins are fixed to VI = VSS1 or VDD1) 7 µPD16334 SWITCHING CHARACTERISTICS (TA = 25 °C, VDD1 = 5 V, VDD2 = 70 V, VSS1 = VSS2 = 0 V, Logic CL = 15 pF, Driver CL = 50 pF, tr = tf = 6.0 ns) Parameter Symbol Transmission t PHL1 Delay time t PLH1 t PHL2 Conditions MIN. TYP. CLK ↓ → A/B CLK ↑ (LE = H) → O1 to O96 t PLH2 t PHL3 BLK → O1 to O96 t PLH3 t PHL4 PC → O1 to O96 t PLH4 Maximum Clock ns 180 ns 180 ns 165 ns 165 ns 160 ns 160 ns 300 ns tPZH RL = 10 kΩ 180 ns 300 ns 180 ns 150 ns 3 µs tTLH O1 to O96 tTLZ RL = 10 kΩ tTZH O1 to O96 150 ns tTHL O1 to O96 150 ns tTHZ RL = 10 kΩ tTZL O1 to O96 fmax. When data is read, duty 50 % 25 MHz cascade connection, Duty 50 % 15 MHz Frequency Input Capacitance ns 55 OE → O1 to O96 tPZL Fall Time Unit 55 tPHZ tPLZ Rise Time MAX. CI 3 µs 150 ns 15 pF TIMING REQUIREMENT (TA = –40 to +85 °C, VDD1 = 4. 75 to 5. 25 V, VSS1,2 = 0 V, tr = tf = 6.0 ns) Parameter 8 Symbol Conditions MIN. TYP. MAX. Unit Clock Pulse Width PWCLK 20 ns Latch Enable Pulse Width PWLE 30 ns Blank Pulse Width PWBLK 200 ns PC Pulse Width PWPC 200 ns OE Pulse Width PWOE 3.3 µs Data Setup Time tsetup 10 ns Data Hold Time thold 10 ns Latch Enable Time 1 tLE1 25 ns Latch Enable Time 2 tLE2 5 ns Latch Enable Time 3 tLE3 25 ns Latch Enable Time 4 tLE4 5 ns RL = 10 kΩ µPD16334 SWITCHING CHARACTERISTICS WAVEFORM 1/fmax. PWCLK (H) PWCLK (L) 3.3 V 50 % 50 % 50 % CLK VSS1 tsetup thold 3.3 V An/Bn (Input) 50 % 50 % VSS1 tPHL1 tPLH1 Bn/An (Output) VOH1 50 % 50 % VOL1 3.3 V 50 % 50 % VSS1 LE PWLE tLE1 tLE2 tLE3 tLE4 3.3 V 50 % 50 % 50 % CLK VSS1 tPHL2 90 % VOH2 On VOL2 tPLH2 On VOH2 10 % VOL2 9 µPD16334 PWBLK 3.3 V BLK 50 % 50 % VSS1 tPHL3 tPLH3 VOH2 90 % On 10 % VOL2 PWPC 3.3 V PC 50 % 50 % VSS1 tPHL4 tPLH4 VOH2 90 % On 10 % VOL2 PWOE 3.3 V 50 % 50 % VSSI OE tPLZ tTLZ tPZL tTZL VO(H) 90 % 90 % On 10 % 10 % VOL2 VOH2 90 % On 10 % tPHZ 10 90 % tTHZ 10 % tPZH tTZH VO (L) µPD16334 [MEMO] 11 µPD16334 No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product. M4 96. 5