DATA SHEET MOS INTEGRATED CIRCUIT µPD16641 SOURCE DRIVER FOR 240-OUTPUT TFT-LCD (64 GRAY SCALES) DESCRIPTION The µPD16641 is a source driver for TFT-LCD 64 gray scale displays. Its logic circuit operates at 3.3 V and the driver circuit operates at 3.3 or 5.0 V (selectable). The input data is digital data at 6 bits × 3 dots, and 260,000 colors can be displayed in 64-value outputs γ-corrected by the internal D/A converter and 11 external power supplies. Because the clock frequency is 33 MHzMIN, the µPD16641 can be used in TFT-LCD panels conforming to the VGA standards. FEATURES • Precharge-less output buffer • 64-value output by 11 external power supplies and internal D/A converter • Level of γ-corrected power supply can be inverted • Output voltage range: 2.8 VP-PMAX. (at supply voltage VDD2 of driver circuit = 3.0 V) 4.3 VP-PMAX. (at supply voltage VDD2 of driver circuit = 4.5 V) • CMOS level input • 6 bit (gray scale data) × 3 dot input • High-speed data transfer: fmax. = 33 MHzMIN. (internal data transfer rate at supply voltage VDD1 of logic circuit = 3.0 V) • 240 outputs • Supply voltage of driver circuit selectable (Vsel = H: 3.3 V, Vsel = L: 5.0 V) • Slim TCP ORDERING INFORMATION Part No. Package µPD16641N-××× TCP (TAB package) The TCP is custom-made. For details, consult NEC Document No. S10565EJ1V0DS00 (1st edition) Date Published May 1998 N CP(K) Printed in Japan © 1998 µPD16641 1. BLOCK DIAGRAM STHR R/L CLK STHL VDD1 (3.3 V) VSS1 80-bit bidirectional shift register C1 C2 C79 C80 D00 to 05 D10 to 15 D20 to 25 Data register Latch STB VDD2 (3.3/5.0 V) Vsel D/A converter V0 to V10 VSS2 Output buffer S1 2 S2 S3 S240 µPD16641 2. PIN CONFIGURATION (standard TCP: µPD16641N-××× ×××) ××× COMMON COMMON Vsel VSS2 VDD2 V10 V8 V6 V4 V2 V0 R/L D20 D21 D22 D23 D24 D25 STB STHL VDD1 CLK VSS1 STHR D10 D11 D12 D13 D14 D15 D00 D01 D02 D03 D04 D05 V1 V3 V5 V7 V9 VDD2 VSS2 COMMON Monitor pin COMMON COMMON COMMON NC NC NC COMMON COMMON COMMON NC NC NC NC S240 S239 (Copper foil surface) Monitor pin S2 S1 NC NC NC NC COMMON COMMON COMMON NC NC NC COMMON COMMON COMMON Vsel pin is internally pulled up. Therefore, the number of input pins can be reduced by opening or short-circuiting these pins to VSS2 by means of TCP wiring. 3 µPD16641 3. PIN DESCRIPTION Pin Symbol Pin Name Description S1 to S240 Driver output Output 64 gray scale analog voltages converted from digital signals. D00 to D05 Display data input Inputs 18-bit-wide display gray scale data (6 bits) × 3 dots (RGB). DX0: LSB, DX5: MSB R/L Shift direction select input This pin inputs/outputs start pulses when two or more µPD16641s are connected in cascade. Shift direction of shift register is as follows: R/L = H : STHR input, S1 → S240, STHL output R/L = L : STHL input, S240 → S1, STHR output STHR Right shift start pulse I/O R/L = H : Inputs start pulse. R/L = L : Outputs start pulse. STHL Left shift start pulse I/O R/L = H : Outputs start pulse. R/L = L : Inputs start pulse. Vsel Driver voltage selection Selects driver voltage. This pin is internally pulled up to VDD2. Vsel = VDD2 or OPEN: VDD2 = 3.3 V ± 0.3 V, Vsel = L: VDD2 = 5.0 V ± 0.5 V CLK Shift clock input Inputs shift clock to shift register. Display data is loaded to data register at rising edge of this pin. Start pulse output goes high at rising edge of 80th clock after start pulse has been input, and serves as start pulse to driver in next stage. 80th clock of driver in first stage serves as start pulse of driver in next stage. STB Latch input Contents of data register are latched at rising edge, transferred to D/A converter, and output as analog voltage corresponding to display data. Contents of initial shift register are cleared after STB has been input. One pulse of this signal is input when µPD16641 is started, and then device operates normally. For STB input timing, refer to Relations between STB, Start Pulse, and Blanking Period in Switching Characteristic Waveform. V0 to V10 γ-corrected power supply Inputs γ-corrected power from external source. VSS2 ≤ V10 ≤ V9 ≤ V8 ≤ V7 ≤ V6 ≤ V5 ≤ V4 ≤ V3 ≤ V2 ≤ V1 ≤ V0 ≤ VDD2 VSS2 ≤ V0 ≤ V1 ≤ V2 ≤ V3 ≤ V4 ≤ V5 ≤ V6 ≤ V7 ≤ V8 ≤ V9 ≤ V10 ≤ VDD2 Maintain gray scale power supply during gray scale voltage output. VDD1 Logic circuit power supply 3.3 V ± 0.3 V VDD2 Driver circuit power supply Vsel = VDD2 or OPEN : VDD2 = 3.3 V ± 0.3 V : VDD2 = 5.0 V ± 0.5 V Vsel = L VSS1 Logic ground Ground VSS2 Driver ground Ground D10 to D15 D20 to D25 Caution Be sure to turn on power in the order VDD1, logic input, VDD2, and gray scale power (V0 to V10), and turn off power in the reverse order, to prevent the µPD16641 from being damaged by latchup. Be sure to observe this power sequence even during a transition period. 4 µPD16641 4. RELATION BETWEEN INPUT DATA AND OUTPUT VOLTAGE VALUE The 11 major points on the γ characteristic curve of the LCD panel are arbitrarily set by external power supplies V0 through V10. If the display data is 00H or 3FH, gray scale voltage V0 or V10 is output. If the display data is in the range 01H to 3EH, the high-order 3 bits select an external powers pair Vn+1, Vn. The low-order 3 bits evenly divide the range of Vn+1 to Vn into eight segments by means of D/A conversion (however, the ranges from V9 to V8 and from V2 to V1 are divided into seven segments) to output a 64 gray scale voltage. DX5 (MSB) DX3 DX2 DX1 DX0 (LSB) High-order 3 bits: γ-corrected power selected Low-order 3 bits: 3bit D/A (Vn+1, Vn) (range Vn to Vn+1 is divided into 7 or 8 segments) DX5 0 0 0 0 1 1 1 1 VDD2 DX4 DX4 0 0 1 1 0 0 1 1 DX3 0 1 0 1 0 1 0 1 Vn Vn+1 to Vn V1 to V2 V2 to V3 V3 to V4 V4 to V5 V5 to V6 V6 to V7 V7 to V8 V8 to V9 1 2 3 4 5 6 7 8 Vn+1 000 001 010 011 100 101 110 111 DX2 to DX0 V0 gray scale supply specified by 00H V1 7 segments V2 8 segments V3 8 segments V4 8 segments V5 8 segments V6 8 segments V7 8 segments V8 7 segments V9 VSS2 V10 0 7 F 17 1F 27 2F 37 3F gray scale supply specified by 3FH Input data (HEX) 5 µPD16641 Relation between Input Data and Output Voltage 6 Input Data DX5 DX4 DX3 DX2 DX1 DX0 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Output Voltage V0 V2 + (V1 – V2) × 6/7 V2 + (V1 – V2) × 5/7 V2 + (V1 – V2) × 4/7 V2 + (V1 – V2) × 3/7 V2 + (V1 – V2) × 2/7 V2 + (V1 – V2) × 1/7 V2 V3 + (V2 – V3) × 7/8 V3 + (V2 – V3) × 6/8 V3 + (V2 – V3) × 5/8 V3 + (V2 – V3) × 4/8 V3 + (V2 – V3) × 3/8 V3 + (V2 – V3) × 2/8 V3 + (V2 – V3) × 1/8 V3 V4 + (V3 – V4) × 7/8 V4 + (V3 – V4) × 6/8 V4 + (V3 – V4) × 5/8 V4 + (V3 – V4) × 4/8 V4 + (V3 – V4) × 3/8 V4 + (V3 – V4) × 2/8 V4 + (V3 – V4) × 1/8 V4 V5 + (V4 – V5) × 7/8 V5 + (V4 – V5) × 6/8 V5 + (V4 – V5) × 5/8 V5 + (V4 – V5) × 4/8 V5 + (V4 – V5) × 3/8 V5 + (V4 – V5) × 2/8 V5 + (V4 – V5) × 1/8 V5 V6 + (V5 – V6) × 7/8 V6 + (V5 – V6) × 6/8 V6 + (V5 – V6) × 5/8 V6 + (V5 – V6) × 4/8 V6 + (V5 – V6) × 3/8 V6 + (V5 – V6) × 2/8 V6 + (V5 – V6) × 1/8 V6 V7 + (V6 – V7) × 7/8 V7 + (V6 – V7) × 6/8 V7 + (V6 – V7) × 5/8 V7 + (V6 – V7) × 4/8 V7 + (V6 – V7) × 3/8 V7 + (V6 – V7) × 2/8 V7 + (V6 – V7) × 1/8 V7 V8 + (V7 – V8) × 7/8 V8 + (V7 – V8) × 6/8 V8 + (V7 – V8) × 5/8 V8 + (V7 – V8) × 4/8 V8 + (V7 – V8) × 3/8 V8 + (V7 – V8) × 2/8 V8 + (V7 – V8) × 1/8 V8 V9 + (V8 – V9) × 6/7 V9 + (V8 – V9) × 5/7 V9 + (V8 – V9) × 4/7 V9 + (V8 – V9) × 3/7 V9 + (V8 – V9) × 2/7 V9 + (V8 – V9) × 1/7 V9 V10 µPD16641 γ-Corrected Power Circuit The reference power supply of the D/A converter consists of a ladder circuit with a total of 64 resistors, and resistance Σri between γ-corrected power pins differs depending on each pair of γ-corrected power pins. One pair of γ-corrected power pins consists of seven or eight series resistors, and resistance Σri in the figure below is indicated as the sum of the seven of eight resistors. The resistance ratio between the γ-corrected power pins (Σri ratio) is designed to be a value relatively close to the ratio of the γ-corrected voltages V1 through V9 (gray scale voltages in 8 steps) used in an actual LCD panel. Under ideal conditions where there is no difference between the two, therefore, there is no voltage difference between the voltage of the γ-corrected power supplies and the gray scale voltages in 8 steps of the resistor ladder circuits of the µPD16641, and no current flows into the γ-corrected power pins V1 through V9. As a result, a voltage follower circuit is not necessary. γ-corrected power pin γ-corrected resistor – + V0 i0 – + V1 i1 µ PD16641 R0 = 1.81 kΩ 7 R1 = Σri = 3.57 kΩ i=1 – + V2 i2 8 R2 = Σri = 3.12 kΩ i=1 – + V3 Sum of eight γ-corrected resistors i3 8 R3 = Σri = 3.08 kΩ i=1 – + V4 i4 8 R4 = Σri = 2.90 kΩ i=1 – + V5 i5 8 R5 = Σri = 2.32 kΩ i=1 – + V6 i6 8 R6 = Σri = 3.35 kΩ i=1 – + V7 i7 8 R7 = Σri = 3.23 kΩ i=1 – + V8 i8 7 R8 = Σri = 4.75 kΩ i=1 – + V9 i9 R9 = 13.5 kΩ – + V10 i10 7 µPD16641 Relation between Input Data and Output Data Data format : 1 pixel data (6 bits) × RGB (3 dots) Input width : 18 bits R/L = H (right shift) Output S1 S2 S3 ··· S239 S240 Data D00 to D05 D10 to D15 D20 to D25 ··· D10 to D15 D20 to D25 Output S1 S2 S3 ··· S239 S240 Data D00 to D05 D10 to D15 D20 to D25 ··· D10 to D15 D20 to D25 R/L = L (left shift) 5. OPERATION OF OUTPUT BUFFER The output buffer consists of an operational amplifier circuit that does not perform precharge operation. Therefore, driver output current IVOH1/2 is the charging current to the LCD, and IVOL1/2 is the discharging current. The chip has the driving capability to charge or discharge a liquid load with CL = 80 pF to 3 τ in less than 10 µs. <LCD panel driving waveform of µPD16641> VDD2 Sn VSS2 Write (IVOL/IVOH) Write (IVOL/IVOH) 1 horizontal period 8 µPD16641 6. ELECTRIC SPECIFICATION Absolute Maximum Ratings (VSS1 = VSS2 = 0 V) Parameter Symbol Rating Unit Supply voltage VDD1 –0.3 to +4.5 V Supply voltage VDD2 –0.3 to +7.0 V Input voltage VI –0.3 to VDD1, 2 + 0.3 V Output voltage VO –0.3 to VDD1, 2 + 0.3 V Permissible dissipation PD 150 mW Operating temperature range TA –10 to +75 °C Storage temperature range Tstg. –55 to +125 °C Recommended Operating Range (TA = –10 to +75°C, VSS1 = VSS2 = 0 V) Parameter Symbol Condition MIN. TYP. MAX. Unit 3.0 3.3 3.6 V Logic supply voltage VDD1 Driver supply voltage VDD2 Vsel = H 3.0 3.3 3.6 V Driver supply voltage VDD2 Vsel = L 4.5 5.0 5.5 V VDD2 – 0.1 V γ-corrected power V0 to V10 VSS2 + 0.1 Maximum clock frequency fmax. 33 Output load capacitance CL MHz 150 pF 9 µPD16641 Electrical Characteristics (TA = –10 to +75°C, VDD1 = 3.0 to 3.6 V, VDD2 = 3.0 to 3.6 V or 4.5 to 5.5 V, VSS1 = VSS2 = 0 V) Parameter Symbol High-level input voltage VIH Low-level input voltage VIL Input leakage current IL Condition MIN. R/L, CLK, STB, STHR (L), D00-05, D10-15, D20-25 RPU Vsel, VDD2 = 5.0 V, Vsel, = 0 V High-level output voltage VOH STHR (L), IO = –1.0 mA Low-level output voltage VOL STHR (L), IO = +1.0 mA Static current consumption of γ-corrected power (VDD2 = 3.3 V) IVn1 VDD1 = 3.3 V, VDD2 = 3.3 V V0 = 3.20 V, V6 = 1.95 V V1 = 3.07 V, V7 = 1.70 V V2 = 2.80 V, V8 = 1.46 V V3 = 2.57 V, V9 = 1.11 V V4 = 2.34 V, V10 = 0.10 V V5 = 2.12 V,Note V10 VDD1 = 3.3 V, VDD2 = 5.0 V V0 = 4.90 V, V6 = 2.96 V V1 = 4.69 V, V7 = 2.58 V V2 = 4.28 V, V8 = 2.20 V V3 = 3.92 V, V9 = 1.66 V V4 = 3.56 V, V10 = 0.1 V V5 = 3.23 V,Note V10 IVn2 MAX. Unit 0.7VDD1 VDD1 V 0 0.3VDD1 V ±1.0 µA 250 kΩ D00-05, D10-15, D20-25 R/L, CLK, STB, STHR (L) Pull-up resistor Static current consumption of γ-corrected power (VDD2 = 5.0 V) TYP. 40 100 VDD1 – 0.5 V 0.5 –200 V9 V –150 µA ±10 µA to V1 V0 150 –300 V9 200 µA –250 µA ±10 µA to V1 V0 250 300 µA (VX is output voltage of analog output pin S1 to S240. VOUT is the voltage applied to analog output pin S1 to S240.) Note Apply ideal voltage to V1 to V9 that is calculated from internal resistor. 10 µPD16641 Electrical Characteristics (TA = –10 to +75°C, VDD1 = 3.0 to 3.6 V, VDD2 = 3.0 to 3.6 V or 4.5 to 5.5 V, VSS1 = VSS2 = 0 V) Parameter Driver output current (VDD2 = 3.3 V) Driver output current (VDD2 = 5.0 V) Output voltage deviation Output voltage range Dynamic logic current consumption Dynamic driver current consumption Dynamic driver current consumption Symbol Condition MIN. TYP. MAX. Unit –0.3 –0.075 mA IVOH1 STB = 3.3 V VOUT = 2.2 V, VX = 3.2 V VDD1 = VDD2 = 3.3 V IVOL1 STB = 3.3 V VOUT = 1.1 V, VX = 0.1 V VDD1 = VDD2 = 3.3 V IVOH2 STB = 5.0 V VOUT = 3.9 V, VX = 4.9 V VDD1 = 3.3 V, VDD2 = 5.0 V IVOL2 STB = 5.0 V VOUT = 1.1 V, VX = 0.1 V VDD1 = 3.3 V, VDD2 = 5.0 V ∆VO VDD1 = 3.3 V, VDD2 = 3.3 V VOUT = 1.65 ±20 ±25 mV VDD1 = 3.3 V, VDD2 = 5.0 V VOUT = 2.50 V ±20 ±25 mV VDD2 – 0.1 V VO 0.075 –0.3 0.1 Input data: 00H to 3FH VSS2 + 0.1 Note IDD1 No load IDD21 IDD22 0.25 mA –0.1 0.25 mA mA 2.0 mA No load, VDD2 = 3.3 V ± 0.3 V Note 5.0 mA No load, VDD2 = 5.0 V ± 0.5 V Note 6.5 mA Note The STB cycle is specified at 31 µs and fCLK = 16 MHz. Input data: 1010… (checkerboard pattern) Refers to current consumption per driver when cascades are connected under the assumption of VGA single-sided mounting (8 units). 11 µPD16641 Switching Characteristics (TA = –10 to +75°C, VDD1 = 3.0 to 3.6 V, VDD2 = 3.0 to 3.6 V or 4.5 to 5.5 V, VSS1 = VSS2 = 0 V, tr = tf = 3.0 ns) Parameter Symbol Condition MIN. TYP. MAX. Unit Start pulse delay time tPLH1 CL = 15 pF 2.0 17 ns Start pulse delay time tPHL1 CL = 15 pF 2.0 17 ns Driver output delay time 1 tPLH21 6.0 12 µs Driver output delay time 2 tPLH31 VO: 0.1 V → 3.2 V VDD2 = 3.3 V 2 kΩ + 75 pF × 2 8.0 14 µs Driver output delay time 1 tPHL21 VO: 3.2 V → 0.1 V 6.0 10 µs Driver output delay time 2 tPHL31 8.0 12 µs Driver output delay time 1 tPLH22 6.0 10 µs Driver output delay time 2 tPLH32 VO: 0.1 V → 4.9 V VDD2 = 5.0 V 2 kΩ + 75 pF × 2 8.0 12 µs Driver output delay time 1 tPHL22 VO: 4.9 V → 0.1 V 6.0 8.0 µs Driver output delay time 2 tPHL32 8.0 10 µs Input capacitance CI1 V0 to V10, TA = 25°C 100 pF Input capacitance CI2 STHR (L), TA = 25°C 10 15 pF Input capacitance CI3 STHR (L), other than V0 to V10 TA = 25°C 7.0 10 pF Timing Requirements (TA = –10 to +75°C, VDD1 = 3.0 to 3.6 V, VDD2 = 3.0 to 3.6 V or 4.5 to 5.5 V, VSS1 = VSS2 = 0 V, tr = tf = 3.0 ns) Parameter Symbol Condition MIN. TYP. MAX. Unit Clock pulse width PWCLK 22 ns Clock low period PWCLK(L) 4.0 ns Clock high period PWCLK(H) 4.0 ns Data setup time tSETUP1 2.0 ns Data hold time tHOLD1 2.0 ns Start pulse setup time tSETUP2 2.0 ns Start pulse hold time tHOLD2 2.0 ns Start pulse low period tSPL 2 CLK Start pulse rise time tSPR STB setup time 80 tSETUP3 Data invalid period tINV Final data timing tLDT CLK 1 CLK 1 CLK 1 CLK CLK-STB time tCLK-STB CLK ↑ → STB ↑ or ↓ 7.0 ns STB-CLK time tSTB-CLK STB ↑ or ↓ → CLK ↑ 7.0 ns 12 µPD16641 7. SWITCHING CHARACTERISTIC WAVEFORM (R/L = H) Unless otherwise specified, the input level is VIH = 0.7 VDD1, VIL = 0.3 VDD1. PWCLK PWCLK (H) The figures in parenthesis indicate R/L = L PWCLK (L) tf tr VDD1 90 % 10 % CLK 90 % 10 % VSS1 tSETUP1 tHOLD1 VDD1 DXX VSS1 tHOLD2 tSPL tSETUP2 tHOLD2 VDD1 STHR (STHL) VSS1 tSETUP3 tSPR1/2 tPLH1 tPHL1 VDD1 STHL (STHR) VSS1 VDD1 STB VIH VSS1 tPHL31/32 tPHL21/22 Targeted output voltage ± 0.1VDD2 Sn tPHL31/32 Targeted output voltage (6-bit accuracy) tPHL21/22 Sn Targeted output voltage ± 0.1VDD2 13 µPD16641 Switching Characteristic Waveform tINV VDD1 1 CLK 2 3 4 VSS1 tSETUP2 tHOLD2 VDD1 STHR (STHL) VSS1 tSETUP1 tHOLD1 VDD1 1 DXX 2 3 4 VSS1 tLDT (1 CLKMAX.) 638 639 640 641 642 VDD1 CLK VSS1 VDD1 STB VSS1 tSETUP1 tHOLD1 VDD1 638 DXX 639 640 VSS1 VDD1 CLK VSS1 tCLK-STB tSTB-CLK tCLK-STB tSTB-CLK VDD1 STB VSS1 14 µPD16641 8. RELATION BETWEEN STB/STHR, STHL AND BLANKING PERIOD 641 642 643 644 1 2 CLK DXX (640th Line) 640 tBLK (4 CLKMIN.) DXX (1st Line) 1 tCLK-STB (7 nsMIN.) tSTB-CLK (7 nsMIN.) tSETUP2 (4 nsMIN.) tLDT (1 CLKMIN.) STB 2 tHOLD2 (0 nsMIN.) VIH VIL tSETUP3 (2 CLKMIN.) 1st STHR (IN) VIH VIL 15 µPD16641 9. DATA INPUT TIMING IN CASCADE CONNECTION 79 78 80 81 82 83 84 1 2 3 CLK 1st DXX (IN) 77 78 79 80 1st STHL (OUT) 2nd STHR (IN) 2nd DXX (IN) CLK STB Output Hi-z 16 Output µPD16641 10. RECOMMENDED MOUNTING CONDITIONS Mounting this product under the following conditions is recommended. For the mounting methods and conditions other than those recommended, consult NEC. Mounting Conditions Thermocompression bonding Mounting Method Conditions Soldering Heating tool: 300 to 350°C, Heating time: 2 to 3 seconds, Pressure: 100 g (per product) ACF (sheet adhesive) Preliminary adhesion: 70 to 100°C, Pressure: 3 to 8 kg/cm , Time: 3 to 5 seconds 2 Real adhesion: 165 to 180°C, Pressure: 25 to 45 kg/cm , Time 30 to 40 seconds (when SUMIZAC1003 of Sumitomo Bakelite is used) 2 Note For the mounting conditions for ACF, consult the ACF manufacturer. Do not use two or more mounting methods in combination. Reference NEC Semiconductor Device Reliability/Quality Control System (C10983E) Quality Grades to NEC’s Semiconductor Devices (C11531E) 17 µPD16641 [MEMO] 18 µPD16641 [MEMO] 19 µPD16641 No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product. M4 96. 5