DATA SHEET MOS INTEGRATED CIRCUITS µPD16663 240-OUTPUT LCD COLUMN (SEGMENT) DRIVER WITH BUILT-IN RAM DESCRIPTION The µPD16663 is a column (segment) driver device with built-in RAM. It is capable of driving a full-dot LCD. There are 240 outputs that, with the 240 × 160 × 4-bit built-in display RAM, enable a 16-gray scale display. The sixteen gray scales can be selected arbitrarily from a 49-stage palette. When combined with the µPD16667, this device can drive displays of 240 × 160 to 480 × 320 dots. FEATURES • Built-in display RAM: 240 × 160 × 4 bits • Logic voltage: 3.0 to 3.6 V • Duty cycle: 1/160 • Number of outputs: 240 • Gray scales: 16 (selectable from a palette of 49) • Memory management: Packed pixel • Compatible with 8-bit/16-bit data buses ORDERING INFORMATION ★ Part number Package µPD16663N-××× TCP (TAB) µPD16663N-051 2-side standard TCP Remark The TCP's external shape is customized. To order the required shape, please contact an NEC salesperson. The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. Date Published Printed in Japan S13392EJ1V0DS00 (1st edition) December 1999 NS CP(K) The mark ★ shows major revised points. © 1998, 1999 µPD16663 BLOCK DIAGRAM DIR PL0, PL1 A0 - A16 Address input control TEST Address management circuit Arbiter RAM 240 x 160 x 4 bits Control /CS, /OE, /WE, /UBE RDY D0 - D15 Data bus control BMODE /REFRH Data latch (1) /RESET MS STOP Gray scale generation circuit Data latch (2) OSC1 CR oscillator Internal timing generator OSC2 /DOFF Gray scale control LCD timing generator 3.3-V operation PULSE /FRM STB Self-diagnostic circuit 3.3-V operation Level shifter 5.0-V operation 5.0-V operation DEC V0 240 outputs of LCD driver circuit PULSE /FRM STB /DOUT L1 L2 Remark /××× indicates active low signal. 2 Data Sheet S13392EJ1V0DS00 Y 1 Y2 Y3 V1 V2 Y240 µPD16663 1. PIN FUNCTIONS Note Pin name Classification CPU Interface 3.3 V Control signals 3.3 V I/O Function D0 to D15 I/O Data bus : 16 bits A0 to A16 I Address bus : 17 bits /CS I Chip select /OE I Read signal /WE I Write signal /UBE I Upper byte enable RDY O Ready signal issued to CPU ("H" sets ready status) PL0 I Specifies the LSI placement position (No. 0 to 3) PL1 I Specifies the LSI placement position (No. 0 to 3) DIR I Specifies the direction of the LCD panel placement MS I Selects between master/slave ("H" sets master mode) BMODE I Selects the data bus bit ("H" sets 8 bits, "L" sets 16 bits) /REFRH I/O Self-diagnostics reset pin (Wired-OR connection) TEST I Test pin ("H" sets test mode, pull-down resistor is built-in) /RESET I Reset signal /DOFF I Display OFF input signal OSC1 - For external resistor for oscillator OSC2 - For external resistor for oscillator STB I/O Column driving signal (MS pin "H" sets output, MS pin "L" sets input) /FRM I/O Frame signal (MS pin "H" sets output, MS pin "L" sets input) PULSE I/O 25-gray-scale pulse modulation clock L1 I/O Row driver driving level select signal (line 1) L2 I/O Row driver driving level select signal (line 2) /DOUT O Display OFF output signal LCD drive Y1 to Y240 O LCD drive output Power supply GND - Ground (× 2 for 5 V, × 3 for 3.3 V) VCC1 - 5-V power supply VCC2 - 3.3-V power supply V0 - LCD drive analog power supply V1 - LCD drive analog power supply V2 - LCD drive analog power supply 5.0 V Note 3.3-V pins : D0 to D15, A0 to A16, /CS, /OE, /WE, /UBE, RDY, BMODE, PL0, PL1, DIR, OSC1, OSC2, /RESET, /DOFF, TEST, MS 5-V pins :STB, /FRM, L1, L2, /DOUT, PULSE Remark N.C. = Non-connection Data Sheet S13392EJ1V0DS00 3 µPD16663 2. BLOCK FUNCTION (1) Address management circuit Converts an address transferred from the system via A0 to A16 to an address that corresponds to the onchip RAM memory map. This function enables address management for a display size of up to 480 x 320 dots using four µPD16663 LSIs, thus facilitating the configuration of LCD systems. The allocation of addresses 1FFF80H to 1FFFEH (even addresses only) to the gray scale palette register also allows the user to select any 16 gray scales from a palette of 49. (2) Arbiter Resolves a conflict between a RAM access from the system and a RAM read on the LCD drive side. (3) RAM 240 x 160 x 4 bits of static RAM (single port). (4) Data bus control Controls the direction in which data is transferred according to whether the system is reading or writing. The bus width can also be switched between 8 and 16 bits with the BMODE pin. (5) Gray scale generation circuit Culls frames and modulates the pulse width to realize 49 gray scales. (6) Internal timing generator Generates the internal timing for each block from the /FRM and STB signals. (7) CR oscillator In master mode, this oscillator generates the clock referenced for the frame frequency. The frame frequency is determined by dividing this clock by 2592. To obtain a frame frequency of 70 Hz, therefore, an oscillation frequency of 181.44 kHz is required. Because the CR oscillator is on chip, adjust the oscillation frequency using an external resistor. Oscillation is stopped in slave mode. (8) LCD timing generator In master mode, this generator generates /FRM (the frame signal), STB (the column driver signal strobe), and PULSE (the 49-gray-scale pulse modulation clock). (9) Gray scale control This is a circuit for realizing a 16-gray-scale display. 4 Data Sheet S13392EJ1V0DS00 µPD16663 (10) Data latch (1) Latches 240-pixel data read from RAM. (11) Data latch (2) Latches 240-pixel data in synchronization with the STB signal. (12) Level shifter Converts the internal circuit operating voltage (3.3 V) to the voltage required by the LCD driver and row driver interface (5 V). (13) DEC Decodes the gray scale display data into the corresponding LCD drive voltages V0, V1, and V2. (14) LCD driver circuit Creates the voltage to be applied to the LCD by selecting one of LCD drive power supplies V0, V1, or V2, according to the gray scale data and display off signal (/DOFF). (15) Self-diagnostic circuit Automatically detects any mismatch between the operation timings of the master and slave chips cause by noise, etc., and issues a refresh signal to all the column drivers. • Address Map Image (Half VGA Size) Column direction specified with A7 to A0 Y1 Y1 Y240 Y240 L1 Address increases in this direction Line direction specified with A16 to A8 No. 0 L160 No. 2 L1 Address increases in this direction No. 1 L160 No. 3 Y1 Y240 Y1 Y240 Data Sheet S13392EJ1V0DS00 5 µPD16663 3. DATA BUS The byte data ordering on the data bus is little endian, which is the format commonly used in most NEC and Intel products. (1) 16-bit data bus (BMODE = L) Byte access Address increases as shown → D0 to D7 D8 to D15 00000H 00001H 00002H 00003H 00004H 00005H : : : : D0 to D7 D8 to D15 Word access 00000H Address increases as shown → 00002H 00004H : : In the same way as access from the system can be performed in word (16-bit) and byte (8-bit) units, valid data is indicated by D0 to D7 and/or D8 to D15, by means of the /UBE signal (higher byte enable) and A0. I/O /CS /OE /WE /UBE A0 D0 to D7 D8 to D15 H × × × × Not Selected Hi-z Hi-z L L H L L Read Dout Dout L H Hi-z Dout H L Dout Hi-z L L Din Din L H × Din H L Din × Hi-z Hi-z Hi-z Hi-z L H L L H H × × L × × H H Remark ×= Don't Care, Hi-z= High impedance 6 MODE Data Sheet S13392EJ1V0DS00 Write Output Disable µPD16663 (2) 8-bit data bus (BMODE = H) D0 to D7 00000H Address increases as shown → 00001H 00002H : : I/O /CS /OE /WE MODE D0 to D7 D8 to D15 H × × Not Selected Hi-z Note L L H Read Dout Note L H L Write Din Note L H H Output Disable Hi-z Note Note When BMODE = H, D8 to D15 can be either left open or connected to GND because they and /UBE are pulled down internally. Remark ×= Don't Care, Hi-z= High impedance Data Sheet S13392EJ1V0DS00 7 µPD16663 4. RELATIONSHIP BETWEEN DATA BITS AND PIXELS 16-gray scale display consists of 4 bits per pixel. In the packed pixel format, RAM is configured with 2 pixels (4 pixels per word). (1) BMODE = L Byte (8-bit) access D0 D1 D2 D3 D4 Pixel 1 D5 D6 D7 D8 Pixel 2 D9 D10 D11 Pixel 3 D13 D14 D15 Pixel 4 00000H LCD panel D12 00001H Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 00000H 00001H 00002H 00003H 00004H 00005H 00006H 00007H D12 D14 Word (16-bit) access D0 D1 D2 D3 D4 Pixel 1 D5 D6 D7 D8 Pixel 2 D9 D10 D11 Pixel 3 D13 D15 Pixel 4 00000H LCD panel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 00000H 00002H 00004H 00006H (2) BMODE = H D0 D1 D2 D3 D4 Pixel 1 D5 D6 D7 D0 Pixel 2 D1 D2 D5 D6 D7 Pixel 4 00001H Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 00000H 8 D4 Pixel 3 00000H LCD panel D3 00001H 00002H 00003H Data Sheet S13392EJ1V0DS00 00004H 00005H 00006H 00007H µPD16663 5. GRAY SCALE CONTROL Gray scale control in the µPD16663 realizes a palette of 49 gray scales, generated by culling frames and modulating the pulse width. From these 49 gray scales, 16 can be selected and recorded in the gray scale palette register. 5.1 Gray Scale Palette Register The gray scale palette register is used to preselect 16 gray scales from a palette of 49. This register is allocated to addresses 1FF80H to 1FFFEH (even addresses only) and has the following relationship with gray scale data. The gray scale palette register can be set according to the mapping positions of column drivers 0 to 3, as determined by PL0 and PL1. Data Sheet S13392EJ1V0DS00 9 µPD16663 ★ Gray Scale Palette Register (1/2) Address LSI placement position No. Gray scale data (Display data) Initial value D3/D7 D2/D6 D1/D5 D0/D4 1FF80 H 0 0 0 0 Gray scale 0 1FF82 H 0 0 0 1 Gray scale 4 1FF84 H 0 0 1 0 Gray scale 8 1FF86 H 0 0 1 1 Gray scale 12 1FF88 H 0 1 0 0 Gray scale 16 1FF8A H 0 1 0 1 Gray scale 19 1FF8C H 0 1 1 0 Gray scale 21 0 1 1 1 Gray scale 23 1FF90 H 1 0 0 0 Gray scale 25 1FF92 H 1 0 0 1 Gray scale 27 1FF94 H 1 0 1 0 Gray scale 29 1FF96 H 1 0 1 1 Gray scale 32 1FF98 H 1 1 0 0 Gray scale 36 1FF9A H 1 1 0 1 Gray scale 40 1FF9C H 1 1 1 0 Gray scale 44 1FF9E H 1 1 1 1 Gray scale 48 1FFA0 H 0 0 0 0 Gray scale 0 1FFA2 H 0 0 0 1 Gray scale 4 1FFA4 H 0 0 1 0 Gray scale 8 1FFA6 H 0 0 1 1 Gray scale 12 1FFA8 H 0 1 0 0 Gray scale 16 1FFAA H 0 1 0 1 Gray scale 19 1FFAC H 0 1 1 0 Gray scale 21 0 1 1 1 Gray scale 23 1FFB0 H 1 0 0 0 Gray scale 25 1FFB2 H 1 0 0 1 Gray scale 27 1FFB4 H 1 0 1 0 Gray scale 29 1FFB6 H 1 0 1 1 Gray scale 32 1FFB8 H 1 1 0 0 Gray scale 36 1FFBA H 1 1 0 1 Gray scale 40 1FFBC H 1 1 1 0 Gray scale 44 1FFBE H 1 1 1 1 Gray scale 48 1FF8E H No. 0 1FFAE H No. 1 Remark The gray scale palette register is initialized by the /RESET signal. 10 Data Sheet S13392EJ1V0DS00 µPD16663 ★ Gray Scale Palette Register (2/2) Address LSI placement position No. Gray scale data (Display data) Initial value D3/D7 D2/D6 D1/D5 D0/D4 1FFC0 H 0 0 0 0 Gray scale 0 1FFC2 H 0 0 0 1 Gray scale 4 1FFC4 H 0 0 1 0 Gray scale 8 1FFC6 H 0 0 1 1 Gray scale 12 1FFC8 H 0 1 0 0 Gray scale 16 1FFCA H 0 1 0 1 Gray scale 19 1FFCC H 0 1 1 0 Gray scale 21 0 1 1 1 Gray scale 23 1FFD0 H 1 0 0 0 Gray scale 25 1FFD2 H 1 0 0 1 Gray scale 27 1FFD4 H 1 0 1 0 Gray scale 29 1FFD6 H 1 0 1 1 Gray scale 32 1FFD8 H 1 1 0 0 Gray scale 36 1FFDA H 1 1 0 1 Gray scale 40 1FFDC H 1 1 1 0 Gray scale 44 1FFDE H 1 1 1 1 Gray scale 48 1FFE0 H 0 0 0 0 Gray scale 0 1FFE2 H 0 0 0 1 Gray scale 4 1FFE4 H 0 0 1 0 Gray scale 8 1FFE6 H 0 0 1 1 Gray scale 12 1FFE8 H 0 1 0 0 Gray scale 16 1FFEA H 0 1 0 1 Gray scale 19 1FFEC H 0 1 1 0 Gray scale 21 0 1 1 1 Gray scale 23 1FFF0 H 1 0 0 0 Gray scale 25 1FFF2 H 1 0 0 1 Gray scale 27 1FFF4 H 1 0 1 0 Gray scale 29 1FFF6 H 1 0 1 1 Gray scale 32 1FFF8 H 1 1 0 0 Gray scale 36 1FFFA H 1 1 0 1 Gray scale 40 1FFFC H 1 1 1 0 Gray scale 44 1FFFE H 1 1 1 1 Gray scale 48 1FFCE H No. 2 1FFEE H No. 3 Remark The gray scale palette register is initialized by the /RESET signal. Data Sheet S13392EJ1V0DS00 11 µPD16663 5.2 Relationship Between Gray Scales and Gray Scale Palette Data The relationship between the gray scales and gray scale palette data set with the gray scale palette register is shown in the table below. Gray Scale Palette Data (1/2) Gray scale palette data PMODE Remark D5 D4 D3 D2 D1 D0 Gray scale 0 0 0 0 0 0 0 Gray scale 1 0 0 0 0 0 1 Gray scale 2 0 0 0 0 1 0 Gray scale 3 0 0 0 0 1 1 Gray scale 4 0 0 0 1 0 0 Gray scale 5 0 0 0 1 0 1 Gray scale 6 0 0 0 1 1 0 Gray scale 7 0 0 0 1 1 1 Gray scale 8 0 0 1 0 0 0 Gray scale 9 0 0 1 0 0 1 Gray scale 10 0 0 1 0 1 0 Gray scale 11 0 0 1 0 1 1 Gray scale 12 0 0 1 1 0 0 Gray scale 13 0 0 1 1 0 1 Gray scale 14 0 0 1 1 1 0 Gray scale 15 0 0 1 1 1 1 Gray scale 16 0 1 0 0 0 0 Gray scale 17 0 1 0 0 0 1 Gray scale 18 0 1 0 0 1 0 Gray scale 19 0 1 0 0 1 1 Gray scale 20 0 1 0 1 0 0 Gray scale 21 0 1 0 1 0 1 Gray scale 22 0 1 0 1 1 0 Gray scale 23 0 1 0 1 1 1 Gray scale 24 0 1 1 0 0 0 Gray scale 25 0 1 1 0 0 1 Gray scale 26 0 1 1 0 1 0 Gray scale 27 0 1 1 0 1 1 Gray scale 28 0 1 1 1 0 0 Gray scale 29 0 1 1 1 0 1 Gray scale 30 0 1 1 1 1 0 12 Data Sheet S13392EJ1V0DS00 OFF µPD16663 Gray Scale Palette Data (2/2) Gray scale palette data PMODE Remark D5 D4 D3 D2 D1 D0 Gray scale 31 0 1 1 1 1 1 Gray scale 32 1 0 0 0 0 0 Gray scale 33 1 0 0 0 0 1 Gray scale 34 1 0 0 0 1 0 Gray scale 35 1 0 0 0 1 1 Gray scale 36 1 0 0 1 0 0 Gray scale 37 1 0 0 1 0 1 Gray scale 38 1 0 0 1 1 0 Gray scale 39 1 0 0 1 1 1 Gray scale 40 1 0 1 0 0 0 Gray scale 41 1 0 1 0 0 1 Gray scale 42 1 0 1 0 1 0 Gray scale 43 1 0 1 0 1 1 Gray scale 44 1 0 1 1 0 0 Gray scale 45 1 0 1 1 0 1 Gray scale 46 1 0 1 1 1 0 Gray scale 47 1 0 1 1 1 1 Gray scale 48 1 1 0 0 0 0 Data Sheet S13392EJ1V0DS00 ON 13 µPD16663 6. LSI MAPPING AND ADDRESS MANAGEMENT Addresses can be managed when using up to four µPD16663 LSIs, which enables the configuration of a half VGA size LCD (320 x 480 dots). In this case, the data bus and /CS, /WE, and /OE pins can be used commonly. The system can handle each LCD screen as a single area in memory, eliminating the need to decode multiple µPD16663 LSIs. The LSI No. and layout are specified by the PL0 and PL1 pins, and the DIR pin is used to determine the direction of the LCD contents (height, width). 14 PL1 PL0 LSI placement position No. 0 0 No. 0 0 1 No. 1 1 0 No. 2 1 1 No. 3 Data Sheet S13392EJ1V0DS00 µPD16663 6.1 Addresses for Half-VGA Size Horizontal Rectangle DIR = "0" Specified with A7 to A0 µ PD16663 µ PD16663 Y1 Specified with A16 to A8 X1 00000 Y240 00002 00074 µ PD16667 00100 Y1 00076 00078 00176 00178 Y240 0007A 000EC 000EE 001EE No.0 No.2 09E00 09E76 09E78 09F00 09F02 09F74 09F76 09F78 09F7A 09FEC X1 0A000 0A002 0A074 0A076 0A078 0A07A 0A0EC 0A0EE 0A176 0A178 X160 µ PD16667 0A100 09EEE 0A1EE No.1 No.3 13E00 X160 13F00 13F02 Y240 09FEE 13F74 13E76 13E78 13F76 13F78 Y1 µ PD16663 Data Sheet S13392EJ1V0DS00 13EEE 13F7A Y240 13FEC 13FEE Y5 µ PD16663 15 16 Data Sheet S13392EJ1V0DS00 Y240 µ PD16663 Y1 13F78 13F7A 13FEE 13FEC 13E78 No.3 0A178 Y240 13F76 13E76 0A176 0A076 13F74 0A074 09F74 00074 µ PD16663 No.1 No.0 13F02 0A002 09F02 00002 Y1 13F00 13E00 0A100 0A000 09F00 09E00 00100 00000 Y240 X1 X160 X1 X160 µ PD16667 13EEE 0A1EE 0A078 0A0EC 0A0EE 09F76 09E76 00176 00076 Y1 6.2 Addresses for Half-VGA Size Vertical Rectangle 0A07A 09F78 09F7A 09FEC 09FEE 00178 00078 09E78 No.2 0007A 09EEE 001EE 000EC Y240 µ PD16663 Specified with A7 to A0 000EE Y1 µ PD16663 µPD16663 DIR = "1" Specified with A16 to A8 µ PD16667 µPD16663 7. CPU INTERFACE 7.1 RDY (Ready) Pin Functions Single port RAM is used as the on-chip RAM in the µPD16663. The RDY pin is used to make the CPU wait, in order to prevent contention between a CPU access and a read on the LCD side. 7.1.1 Timing A0 to A16,/UBE /CS /OE,/WE Hi-z Hi-z RDY Wait Ready Wait 7.1.2 RDY pin connection The RDY pin uses a 3-state buffer. Connect an external pull-up resistor to the RDY pin. When more than one µPD16663 LSI is being used, use a wired-OR connection for the RDY pin of each LSI. VCC2 CPU Pull-up resistor Ready input Data Sheet S13392EJ1V0DS00 RDY Column driver RDY Column driver 17 µPD16663 7.2 Access Timing (1) Display data read timing A16 to A0 /UBE /CS /OE Hi-z Hi-z RDY Hi-z D15 to D0 Hi-z Dout (2) Display data write timing A0 to A16 /UBE /CS /WE RDY Hi-z Hi-z Din D15 to D0 (3) Gray scale palette data write timing A0 to A16 /UBE /CS /WE RDY Hi-z D5 to D0 18 Din Data Sheet S13392EJ1V0DS00 µPD16663 ★ 8. INITIALIZATION FUNCTION Two initialization functions are available in the µPD16663. 8.1 Initialization by /RESET /RESET is used for forcible external initialization of the LSI. When /RESET = L, the internal statuses of the µPD16663 are as follows. ìOscillation stopped ìLCD timing generator initialized ìInternal timing generator initialized ìSelf-diagnostic circuit initialized ìGray scale palette register initialized ìDisplay off The display remains off for 4 frame cycles after /RESET release, even if the /DOFF pin is H. /RESET 1 2 3 4 5 6 /FRM /DOUT Internal status Display off Display on Be sure to initialize the LSI by /RESET when turning on the power. 8.2 Initialization by /REFRH /REFRH is a pin used by the internal self-diagnostic circuit to initialize the LSI when there are mismatches in the timing of the column drivers due to external noise, etc. When /REFRH = L, the internal statuses of the µPD16663 are as follows. ìOscillation stopped ìLCD timing generator initialized ìInternal timing generator initialized ìDisplay off Data Sheet S13392EJ1V0DS00 19 µPD16663 The display remains off for 4 frame cycles after /REFRH release, even if the /DOFF pin is H. /REFRH 1 2 3 4 5 6 /FRM /DOUT Internal status Display off Display on ★ 9. DISPLAY OFF FUNCTION When /DOFF = L, the column driver outputs (Yn) are all at the V1 level. Moreover, because the /DOUT output is also L, the /DOFF’ signal of the row driver becomes L, causing all the row driver outputs (Xn) to also be at the V1 level. The display is therefore forcibly put in the off status, regardless of the display data. Remark /DOFF’ is the row driver input pin. 20 Data Sheet S13392EJ1V0DS00 µPD16663 10. LCD TIMING GENERATOR CIRCUIT If master mode is entered by setting MS to H, /FRM and STB are generated at a timing that is 1/160 of the duty ratio, and driver voltage selection signals L1 and L2 are generated for the row driver. /FRM is generated twice per frame, STB 81 times per 1/2 frame or 162 times per frame. (1) /FRM, STB signal generation OSC1 PULSE STB 1 2 /FRM STB 81 1 2 81 1 2 81 1 2 Frame (2) L1, L2 signal generation STB 1 2 3 4 … 1 2 3 4 … 1 2 3 4 … 1 2 3 4 … L1 1 1 1 1 … 1 1 1 1 … 0 0 0 0 … 0 0 0 0 … L2 1 0 1 0 … 0 1 0 1 … 0 1 0 1 … 1 0 1 0 … Data Sheet S13392EJ1V0DS00 21 µPD16663 11. SELF-DIAGNOSTIC FUNCTION This function is provided to monitor whether there are any mismatches in the timing of the column drivers due to factors such as external noise. The slave chip compares L1 and L2 of the master chip with its own internally generated L1 and L2, and if a mismatch is detected, it issues a refresh signal to all the column drivers. Upon the receipt of a refresh signal, an internal reset is instigated, and the timing is initialized. At this time, the display remains off for a period equal to 4 frame cycles plus the time /REFRH is L. Monitoring for an L1, L2 mismatch takes place every 1/2 frame at the rising edge of /FRM. L1 (Master) Mismatch L2 (Master) L1 (Slave) Mismatch L2 (Slave) /REFRH Initialization Initialization Block Configuration (Slave) /RESET Internal reset /REFRH Self-diagnostic circuit 22 L1 Internal L1 signal L2 Internal L2 signal Data Sheet S13392EJ1V0DS00 µPD16663 12. EXAMPLE SYSTEM CONFIGURATION The following example shows the configuration of a system using four µPD16663 LSIs and two row drivers to drive a half VGA size (480 x 320 dots, landscape) LCD panel. ìThe LSI No. is set for each column driver using the PL0 and PL1 pins. ìThe DIR pin on each column driver is set to low. ìOne of the column drivers is specified as the master; the remaining are all slaves. The master column driver supplies signals to the slave column drivers and the row drivers. ìAn oscillator resistor is attached across the OSC1 and OSC2 pins of the master, while those of the slaves are left open. ìThe signals issued by the system (D0 to D15, A0 to A16, /CS, /OE, /WE, /UBE, RDY, /RESET, /DOFF) are connected in parallel to all the column drivers. A pull-up resistor is connected to the RDY signal. ìThe TEST pin is used for testing the LSI, so either leave it open or connect it to GND when configuring the system. VCC2 PULSE STB /FRM , /DOUT,/DOFF L1 L2 RDY /DOFF /RESET D0 to D15 A0 to A16 Control /CS, /OE, /WE, /UBE OSC1 Master No.0 /REFRH Slave No.2 OSC2 Y240 Y1 Y240 Row driver 160 Row driver 160 Scan direction Scan direction Y1 Y240 Y1 Y240 Slave No.1 Y1 Slave No.3 Remark The /DOFF’ pin is an input pin of row driver. Data Sheet S13392EJ1V0DS00 23 µPD16663 13. CHIPSET POWER APPLICATION It is recommended that the power be applied to the chipset in the following order. VCC2 → VCC1 → CPU interface → VDD, VEE → V1, V2 The LCD drive power supplies V1 and V2 must be applied last. ON VCC2 VCC1 CPU InterfaceNote 1 (A0 to A16, /CS, /OE, /WE, /UBE, D0 to D15, /DOFF) /RESET OFF ON 4.5 V OFF 0 s or more 3.3 V 0V 3.3 V 0V 100 ns or more VDDNote 2 0.3VCC2 0 s or more ON OFF OFF V EENote 2 V1 ON OFF 0 s or more ON ON V2 OFF Notes1. The select signals (PL0, PL1, DIR, MS, and BMODE) can be input at the same time as V CC2. 2. VDD and VEE do not have to be ON at the same time. VDD and VEE are the row driver LCD power supplies. Caution Turn off the power of the chipset in the reverse order to the one above. 24 Data Sheet S13392EJ1V0DS00 µPD16663 14. EXAMPLE OF SCHOTTKY BARRIER DIODE LAYOUT FOR POWER SUPPLY PROTECTION WITHIN THE MODULE (Use Schottky barrier diodes that are Vf = 0.5 V or less.) VDDNote VCC1 V2 V1 V0 VSS VEENote Those diodes within the dotted line must be placed when V0 is 0 V (GND) or less. Note VDD and VEE are the row driver LCD power supplies. Data Sheet S13392EJ1V0DS00 25 µPD16663 15. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (TA = +25°C) Item Symbol Rating Units Note 1 VCC1 −0.5 to +6.5 V Note 2 Power supply voltage (1) VCC2 −0.5 to +4.5 V Note 1 VI/O1 −0.5 to VCC1 + 0.5 V Note 2 VI/O2 −0.5 to VCC2 + 0.5 V Note 3,4 VI/O3 −0.5 to VCC1 + 0.5 V Operating ambient temperature TA −20 to +70 °C Storage temperature Tstg −40 to +125 °C Power supply voltage (2) Input/output voltage (1) Input/output voltage (2) Input/output voltage (3) Notes 1. 2. 5-V signals (/FRM, STB, /DOUT, L1, L2, PULSE) 3.3-V signals (MS, DIR, PL0 to PL1, A0 to A16, /CS, /OE, /WE, /UBE, RDY, D0 to D15, /RESET, OSC1, OSC2, /DOFF, TEST, BMODE, /REFRH) 3. LCD driver power supply (V0, V1, V2, Y1 to Y240) 4. Ensure that V0 < V1 < V2. Caution If the absolute maximum rating of even one of the above parameters is exceeded even momentarily, the quality of the product may be degraded. Absolute maximum ratings, therefore, specify the values exceeding which the product may be physically damaged. Be sure to use the product within the range of the absolute maximum ratings. Recommended Operating Ranges (TA = −20°C to +70°C, V0 = 0 V) Item Symbol MIN. TYP. MAX. Units Power supply voltage (1) VCC1 4.5 5.0 5.5 V Power supply voltage (2) 3.3 3.6 V VCC2 3.0 Note 1 VI1 0 VCC1 V Input voltage (2) Note 2 VI2 0 VCC2 V V1 input voltage V1 V0 V2 V V2 input voltage V2 V1 VCC1 V ROSC 30 90 kΩ Input voltage (1) OSC external resistor Notes 1. 2. 5-V signals (/FRM, STB, L1, L2, PULSE) 3.3-V signals (MS, DIR, PL0 to PL1, A 0 to A16, /CS, /OE, /WE, /UBE, RDY, D0 to D15, /RESET, OSC1, OSC2, /DOFF, TEST, BMODE, /REFRH) 26 62 Data Sheet S13392EJ1V0DS00 µPD16663 DC Characteristics (Unless Specified Otherwise, VCC1 = 4.5 to 5.5 V, VCC2 = 3.0 to 3.6 V, V0 = 0 V, V1 = 1.4 to 2.0 V, V2 = 2.8 to 4.0 V, TA = −20°C to +70°C) Item Symbol High-level input voltage (1) for VCC1 Low-level input voltage (1) for VCC1 Note 1 High-level input voltage (2) for VCC2 Low-level input voltage (2) for VCC2 Note 2 Note 2 High-level input voltage (2) for VCC2 Low-level input voltage (2) for VCC2 Note 1 Note 4 Note 4 High-level output voltage (1) for VCC1 Low-level output voltage (1) for VCC1 Note 3 High-level input voltage (3) for VCC2 0.3VCC1 VIH2 0.7VCC2 0.3VCC2 0.8VCC2 0.2VCC2 IOH = -1 mA V V VIL3 VOH1 V V VIL2 VIH3 Units V VIL1 VCC1 − 0.4 V V IOL = 2 mA VOH2 IOH = -2 mA Note 1, 4 VOL2 IOL = 4 mA VOH3 IOH = -1 mA VOL3 IOL = 2 mA 0.4 V ±10 µA 100 µA Note 6 150 µA Note 6 350 µA Note 6 100 µA Note 6 250 µA 2 kΩ Note 5 0.4 VCC1 − 0.4 VCC2 − 0.4 For other than TEST pin, VI = VCC2 or GND Input leakage current (2) II2 Pull-down (TEST pin) VI = VCC2 Display current drain (1) IMAS1 IMAS2 Master, for VCC2 Display current drain (3) ISLV1 Slave, for VCC1 ISLV2 Note 7 40 Slave, for VCC2 RON V V Master, for VCC1 Display current drain (2) Display current drain (4) 10 V V 0.4 II1 Notes 1. MAX. 0.7VCC1 Input leakage current (1) LCD driver output ON resistance TYP. VOL1 Note 5 Low-level output voltage (3) for VCC2 VIH1 MIN. Note 1 High-level output voltage (2) for VCC1 Low-level output voltage (2) for VCC1 Note 3 Conditions 1 5-V signals (/FRM, STB, L1, L2, PULSE) 2. 3.3-V signals (MS, DIR, PL0, PL1, A0 to A16, /CS, /OE, /WE, /UBE, RDY, D0 to D15, /RESET, /DOFF, TEST, BMODE) 3. /DOUT pin 4. /REFRH pin 5. D0 to D15, RDY, OSC2 pins 6. Frame frequency 70 Hz, no-load output, CPU not being accessed (D0 to D15, A0 to A16, /UBE = GND, /CS, /OE, /WE = VCC2) 7. Resistance across Y pin and V pin (V0, V1, or V2) when a load current (ION = 100 µA) is flowing through any one of pins Y1 to Y240. Data Sheet S13392EJ1V0DS00 27 µPD16663 AC Characteristics 1 Display Data Send Timing (1) Master mode (Unless specified otherwise, VCC1 = 4.5 to 5.5 V, VCC2 = 3.0 to 3.6 V, V0 = 0 V, V1 = 1.4 to 2.0 V, V2 = 2.8 to 4.0 V, TA = −20°C to +70°C, frame frequency 70 Hz (fOSC = 181.44 kHz), output load: 100 pF) Item Symbol Conditions MIN. TYP. MAX. Units STB clock cycle time tCYC 87 16/fOSC µs STB high level width tCWH 43 8/fOSC µs STB low level width tCWL 43 8/fOSC µs STB rise time tR 100 ns STB fall time tF 100 ns STB-/FRM delay tPSF 20 µs /FRM-STB delay tPFS 20 µs tCYC tCWL STB (Output) tCWH tR tF 0.9VCC1 0.1VCC1 tPSF /FRM (Output) tPFS tPSF tPFS 0.9VCC1 0.1VCC1 28 Data Sheet S13392EJ1V0DS00 µPD16663 (2) Slave mode (Unless specified otherwise, VCC1 = 4.5 to 5.5 V, VCC2 = 3.0 to 3.6 V, V0 = 0 V, V1 = 1.4 to 2.0 V, V2 = 2.8 to 4.0 V, TA = −20°C to +70°C) Item Symbol Conditions MIN. TYP. MAX. Units STB clock cycle time tCYC 10 µs STB high level width tCWH 4 µs STB low level width tCWL 4 µs STB rise time tR 150 ns STB fall time tF 150 ns /FRM setup time tSFR 1 µs /FRM hold time tHFR 1 µs tCYC tCWL STB (Input) tCWH tF tR 0.7VCC1 0.3VCC1 tSFR /FRM (Input) tHFR tSFR tHFR 0.7VCC1 0.3VCC1 Data Sheet S13392EJ1V0DS00 29 µPD16663 (3) Items common to both master and slaves (Unless specified otherwise, VCC1 = 4.5 to 5.5 V, VCC2 = 3.0 to 3.6 V, V0 = 0 V, V1 = 1.4 to 2.0 V, V2 = 2.8 to 4.0 V, TA = −20°C to +70°C) Item Symbol Output delay (L1, L2, /DOUT) tDOUT1 Output delay (Y1 to Y240) tDOUT2 Conditions TYP. MAX. Units No-load output 50 100 ns No-load output 90 150 ns STB (Output) MIN. 0.9VCC1 tDOUT1 tDOUT1 L1, L2 /DOUT 0.9VCC1 tDOUT2 tDOUT2 0.9V2 0.1V2 Y1 to Y240 0.9V2 0.1V2 30 Data Sheet S13392EJ1V0DS00 µPD16663 AC Characteristics 2 Drawing Access Timing (Unless specified otherwise, VCC1 = 4.5 to 5.5 V, VCC2 = 3.0 to 3.6 V, V0 = 0 V, V1 = 1.4 to 2.0 V, V2 = 2.8 to 4.0 V, TA = −20°C to +70°C, tr = tf = 5 ns) Item Symbol Conditions MIN. TYP. MAX. Units /OE//WE recovery time tRY 30 ns Address setup time tAS 10 ns Address hold time tAH RDY output delay time tRYR RDY float time Note 3 Wait status time Note 1 20 ns CL = 15 pF 30 ns tRYZ 30 ns tRYW 35 ns Ready status time (no contention) Note 1 tRYF1 60 100 ns Ready status time (contention) Note 1 tRYF2 650 1,200 ns tACS 100 ns tHZ 40 ns Data access time (read cycle) Data float time (read cycle) Note 2 Note 3 /CS-/OE time (read cycle) tCSOE 10 ns /OE-/CS time (read cycle) tOECS 20 ns Write pulse width 1 (write cycle 1) Note 1 tWP1 50 ns Write pulse width 2 (write cycle 2) Note 1 tWP2 50 ns Data setup time (write cycle 1, 2) tDW 20 ns Data hold time (write cycle 1, 2) tDH 20 ns /CS-/WE time (write cycle 1, 2) tCSWE 10 ns /WE-/CS time (write cycle 1, 2) tWECS 20 ns Reset pulse width tWRES 100 RDY-/OE time tRDOE Note 4 - RDY-/WE time tRDWE Note 4 - ns Notes 1. Load circuit VCC2 1.8 kΩ 1.0 kΩ 60 pF 2. Load circuit VCC2 1.8 kΩ 1.0 kΩ 100 pF Data Sheet S13392EJ1V0DS00 31 µPD16663 3. Load circuit VCC2 1.8 kΩ 1.0 kΩ 5 pF 4. If the time from the rising edge of RDY to /OE or /WE is long, the display may be adversely affected. It is therefore recommended that tRDOE and tRDWE be set to a value not exceeding 1000 ns. /OE, /WE Recovery Time tRY 0.7 VCC2 /OE,/WE Read Cycle 0.7 VCC2 A16 to A0 /UBE 0.3 VCC2 tAS tAH /CS 0.3 VCC2 tOECS tCSOE tRDOE 0.7 VCC2 /OE 0.3 VCC2 tRYR RDY tRYW tRYF 0.1VCC2 Hi-Z tACS D15 to D0 32 tHZ OUT Data Sheet S13392EJ1V0DS00 tRYZ 0.1 VCC2 0.9 VCC2 0.1 VCC2 µPD16663 Write Cycle 1 (Display Data Write) 0.7 VCC2 A16 to A0 /UBE 0.3 VCC2 tAS tAH /CS 0.3 VCC2 tCSWE tRDWE tWECS 0.7 VCC2 /WE 0.3 VCC2 tRYR tRYF RDY tRYW tRYZ 0.1 VCC2 0.1 VCC2 tWP1 Hi-Z 0.7 VCC2 IN D15 to D0 0.3 VCC2 tDW tDH Write Cycle 2 (Gray Scale Palette Data Write) A16 to A0 /UBE 0.7VCC2 0.3VCC2 tAH tAS /CS 0.3VCC2 tCSWE tWECS 0.7VCC2 /WE 0.3VCC2 tWP2 RDY Hi-Z 0.7VCC2 IN D15 to D0 tDW Data Sheet S13392EJ1V0DS00 0.3VCC2 tDH 33 µPD16663 Reset Pulse Width /RESET 0.3VCC2 tWRES AC Characteristics 3 CR Oscillator (VCC2 = 3.0 to 3.6 V, TA = −20°C to +70°C) Item Symbol Oscillation frequency Frame frequency Conditions MIN. TYP. MAX. Units fOSC External resistor (62 kΩ) 160 190 220 kHz - External resistor (62 kΩ) 61.7 73.3 84.9 Hz Relationship between oscillation frequency and frame frequency / STB frequency The relationship between the oscillation frequency and the frame frequency / STB frequency is as follows. Frame frequency = STB frequency = 34 1 162 × 2 × 8 1 2×8 × oscillation frequency × oscillation frequency Data Sheet S13392EJ1V0DS00 µPD16663 16. PACKAGE DRAWINGS Standard TCP Package Drawings (µPD16663N-051) (1/3) Data Sheet S13392EJ1V0DS00 35 µPD16663 Standard TCP Package Drawings (µPD16663N-051) (2/3) 0.6 ± 0.015 0.4 ± 0.015 Test pad details From PC 0.95 26.5 P0.2 0.24 0.35 0.35 16.25 16.25 0.3 0.15 0.3 0.15 0.3 0.15 From PC Alignment details Right and Left 0.05 ± 0.02 0.6 ± 0.05 TCP tape winding direction Output lead Wind-up direction The Cu pattern side is the underside of the tape. 36 Data Sheet S13392EJ1V0DS00 0.6 ± 0.05 0.6 ± 0.05 0.05 ± 0.02 0.05 ± 0.02 0.3 ± 0.05 0.05 ± 0.02 Center µPD16663 Standard TCP Package Drawings (µPD16663N-051) (3/3) Pin connection diagram No.1 No.2 No.3 No.4 No.5 No.6 No.7 No.8 No.9 No.10 No.11 No.12 No.13 No.14 No.15 No.16 No.17 No.18 No.19 No.20 No.21 No.22 No.23 No.24 No.25 No.26 No.27 No.28 No.29 No.30 No.31 No.32 No.33 No.34 No.35 No.36 No.37 No.38 No.39 No.40 No.41 No.42 No.43 No.44 No.45 No.46 No.47 No.48 No.49 No.50 No.51 No.52 No.53 No.54 No.55 No.56 No.57 No.58 No.59 No.60 No.61 No.62 No.63 No.64 No.65 No.66 No.67 No.68 No.69 No.70 No.71 No.72 No.73 N.C. V0 V1 V2 GND VCC1 L1 L2 /DOUT STB /FRM PULSE GND VCC2 MS BMODE TEST /DOFF RDY /WE /OE /CS /UBE /RESET /REFRH PL1 PL0 DIR GND OSC2 OSC1 VCC2 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 GND VCC2 GND VCC1 V2 V1 V0 N.C. N.C. N.C. N.C. Y1 Y2 Y3 No.1 No.2 No.3 No.4 No.5 No.6 Y118 Y119 Y120 N.C. N.C. N.C. N.C. Y121 Y122 Y123 No.121 No.122 No.123 No.124 No.125 No.126 No.127 No.128 No.129 No.130 Y238 Y239 Y240 N.C. N.C. N.C. No.245 No.246 No.247 No.248 No.249 No.250 DIE : FACE DOWN Data Sheet S13392EJ1V0DS00 37 µPD16663 [MEMO] 38 Data Sheet S13392EJ1V0DS00 µPD16663 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. Data Sheet S13392EJ1V0DS00 39 µPD16663 • The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. • No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. • NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. • Descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. • While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. • NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. M7 98. 8